Display device, driving method thereof and display terminal

Abstract

The invention provides a display device and a driving method thereof, and a display terminal, a level converter in the display device is used for generating a first clock signal, and a time schedule controller generates a control signal when a refresh rate is greater than a preset value for controlling the level converter to process the first clock signal to generate a second clock signal. The second clock signal comprises a plurality of second clock pulses in one-to-one correspondence with a plurality of first clock pulses in the first clock signal, and the ending time of the second clock pulses is later than the ending time of the corresponding first clock pulses, so that the risk of wrong charging under a low refresh rate is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and a driving method thereof, and a display terminal. Background Art

[0002] In display technology, CS (Charge Sharing) technology can realize charge sharing when two signals with opposite phases are switched between high and low potentials, thereby reducing the additional voltage difference required for active switching and lowering the power consumption of the driver.

[0003] However, the waveform of the signal after being affected by CS technology will change, causing the transistors in the pixel circuit to fail to be completely turned off in time, resulting in the subsequent data signals of other rows leaking into the pixel circuit of this row. The lower the refresh rate, the longer the leakage time, the greater the risk of mischarging, and the greater the impact on image quality. Summary of the invention

[0004] The object of the present invention is to provide a display device and a driving method thereof, and a display terminal, so as to solve the problem that the existing CS technology has a high risk of mischarging at a low refresh rate.

[0005] An embodiment of the present invention provides a display device, including:

[0006] Display panel;

[0007] A timing controller, configured to generate a control signal according to a refresh rate of the display panel, wherein the control signal is a first control signal when the refresh rate is greater than a preset value;

[0008] a level converter, electrically connected to the timing controller, for generating a first clock signal, and for processing the first clock signal to generate a second clock signal when the control signal is the first control signal;

[0009] The first clock signal includes a plurality of first clock pulses, the time period of the second clock pulse overlaps with the time period of the corresponding first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0010] In some embodiments, including:

[0011] A gate driver, integrated in the display panel or independently provided from the display panel, for generating a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and for generating a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

[0012] In some embodiments, the level converter comprises:

[0013] A level conversion module, used for generating the first clock signal;

[0014] The charge sharing module is electrically connected to the level conversion module, and is used for determining whether to process the first clock signal to generate the second clock signal according to the control signal.

[0015] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal which are inverted signals to each other, and the second clock signal includes a first shared sub-clock signal corresponding to the first sub-clock signal and a second shared sub-clock signal corresponding to the second sub-clock signal;

[0016] The charge sharing module comprises a first input module, a second input module, a first output module, a second output module and a first switch module:

[0017] The first input module is used to receive the first sub-clock signal, where the first sub-clock signal includes a plurality of first sub-clock pulses;

[0018] The second input module is used to receive the second sub-clock signal, wherein the second sub-clock signal includes a plurality of second sub-clock pulses corresponding to a plurality of the first sub-clock pulses;

[0019] The first switch module is used to control the first output module to output the first sub-clock signal and control the second output module to output the second sub-clock signal according to the control signal, or control the first output module to output the first shared sub-clock signal and control the second output module to output the second shared sub-clock signal.

[0020] In some embodiments, the charge sharing module further comprises:

[0021] a second switch module, configured to control, according to the control signal, whether the first input module transmits the first sub-clock signal to the first output module;

[0022] The third switch module is used to control the second input module to transmit the second sub-clock signal to the second output module according to the control signal.

[0023] In some embodiments, the timing controller is used to obtain the frame blanking duration of the previous frame, and to calculate the corresponding refresh rate according to the frame blanking duration;

[0024] Alternatively, the timing controller is used to calculate the corresponding refresh rate according to a frame start signal.

[0025] An embodiment of the present invention also provides a display terminal, comprising a display device as described above and a mainboard electrically connected to the display device, wherein the mainboard is used to at least transmit an image signal to the display device to control the display panel to display an image.

[0026] An embodiment of the present invention further provides a method for driving a display device, wherein the display device includes a display panel, a timing controller, and a level converter electrically connected to the timing controller. The method for driving the display device includes:

[0027] controlling the level converter to generate a first clock signal, wherein the first clock signal includes a plurality of first clock pulses;

[0028] Controlling the timing controller to obtain a refresh rate of the display panel, and generating a control signal according to the refresh rate, wherein the control signal is a first control signal when the refresh rate is greater than a preset value;

[0029] Control the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal, wherein the second clock signal includes multiple second clock pulses corresponding to multiple first clock pulses, the time period of the second clock pulse overlaps the time period of the first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0030] In some embodiments, the display device includes a gate driver integrated into the display panel or provided independently of the display panel;

[0031] Wherein, after the step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal, the step includes:

[0032] The gate driver is controlled to generate a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

[0033] In some embodiments, the level converter includes a level conversion module, a charge sharing module electrically connected to the level conversion module;

[0034] The step of controlling the level converter to generate a first clock signal includes:

[0035] Controlling the level conversion module to generate the first clock signal;

[0036] The step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal includes:

[0037] The charge sharing module is controlled to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

[0038] The present invention provides a display device and a driving method thereof, and a display terminal. The display device includes a display panel, a timing controller and a level converter. The timing controller generates a control signal according to the refresh rate of the display panel, and the control signal is a first control signal when the refresh rate is greater than a preset value. The level converter controls the processing of a first clock signal to generate a second clock signal when the control signal is the first control signal. That is, whether to adopt a charge sharing technology is determined according to the refresh rate of the display panel, rather than adopting the charge sharing technology to process the first clock signal to generate the second clock signal under all refresh rates. The charge sharing technology is only adopted at a high refresh rate and is avoided at a low refresh rate, so that the risk of mischarging at a low refresh rate can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural block diagram of a display device provided by an embodiment of the present invention.

[0040] Figure 2 Waveform diagram of some signals provided by an embodiment of the present invention.

[0041] Figure 3 Schematic diagram of enabled and disabled charge sharing technology provided by an embodiment of the present invention.

[0042] Figure 4 The power-refresh rate curve diagram of the display device when the charge sharing technology is turned on and off according to the embodiment of the present invention.

[0043] Figure 5 A charging rate-refresh rate curve diagram of a display device when the charge sharing technology is enabled and disabled according to an embodiment of the present invention.

[0044] Figure 6 A structural block diagram of a level converter provided by an embodiment of the present invention.

[0045] Figure 7 The present invention provides a flow chart of a method for driving a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0047] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0048] In addition, it should be noted that the drawings only provide structures and steps that are closely related to the present invention, and omit some details that are not closely related to the invention. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is exactly the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0049] The present invention provides a display panel, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0050] In some embodiments, in combination Figure 1 and Figure 2 As shown, the display device 100 includes: a display panel 10; a timing controller 20, used to obtain a refresh rate RS of the display panel 10, and used to generate a control signal con according to the refresh rate RS, wherein the control signal con is a first control signal when the refresh rate RS is greater than a preset value; a level converter 30, electrically connected to the timing controller 20, used to generate a first clock signal CK, and also used to process the first clock signal CK to generate a second clock signal CK' when the control signal con is the first control signal; wherein the first clock signal CK includes a plurality of first clock pulses, and the second clock signal CK' includes a plurality of second clock pulses corresponding to the plurality of first clock pulses, the time period of the second clock pulse overlaps the time period of the corresponding first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0051] The display panel 10 may be, but is not limited to, an organic self-luminous display panel, an inorganic self-luminous direct display panel, or a liquid crystal display panel. Figure 1As shown, here, the array arrangement of multiple sub-pixels P in the display panel 10 is taken as an example for explanation, for example, it can be arranged in n rows and m columns (n, m are both positive integers). Further, the display panel 10 may include a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm). The display device 100 may also include a source driver 50 electrically connected to the plurality of data lines and a gate driver 40 electrically connected to the plurality of gate lines. The gate driver 40 may be a gate driving circuit located on the substrate of the display panel 10 or a chip provided independently of the display panel 10.

[0052] Specifically, each gate line (any one of GL1 to GLn) is electrically connected to a plurality of sub-pixels P located in a corresponding row to output a corresponding gate signal Gate (including a gate effective pulse for controlling the sub-pixels to be turned on) thereto, and the sub-pixels P in the plurality of rows are turned on in sequence under the control of the plurality of gate signals Gate (the plurality of gate effective pulses therein), and each data line (any one of DL1 to DLm) is connected to a plurality of sub-pixels P located in a corresponding column to output a corresponding data signal data (each including a plurality of data voltages of the plurality of sub-pixels P in the corresponding column) thereto, and the plurality of data signals data corresponding to the plurality of columns of sub-pixels P are matched so that when the sub-pixels P in each row are turned on, the corresponding plurality of data voltages are respectively transmitted to the corresponding sub-pixels P through the plurality of data lines (DL1 to DLm).

[0053] Specifically, combined Figure 1 and Figure 2 As shown, the first clock signal CK generated by the level converter 30 may include a plurality of sub-clock signals (including at least Figure 2 In the gate driver 40, each gate driving unit 401 can be controlled by at least one sub-clock signal to generate a corresponding gate signal Gate. A plurality of gate effective pulses in the gate signal Gate can be formed according to pulses in a corresponding sub-clock signal, that is, a plurality of first clock pulses in the first clock signal CK acting on the gate driving unit 401 are used to determine the time periods of a plurality of gate effective pulses in a plurality of gate signals Gate.

[0054] like Figure 3As shown, in the charge sharing technology, by short-circuiting the two clock lines used to transmit the first sub-clock signal CKx (for example, sub-clock signal CK1) and the second sub-clock signal CKy (for example, sub-clock signal CKn), which are inverted signals in the first clock signal CK, at the rising edge and falling edge of both, that is, the transistor between the two clock lines is turned on, the potentials of the two clock lines can be integrated (the integrated potential CS is close to the average of the potential of the high-voltage signal VGH and the potential of the low-voltage signal VGL), and then further providing a higher or lower voltage signal through the chip to realize the switching of the potential of the first sub-clock signal CKx and the second sub-clock signal CKy from the potential of the high-voltage signal VGH to the potential of the low-voltage signal VGL, and from the potential of the low-voltage signal VGL to the potential of the high-voltage signal VGH, thereby reducing the power consumption of the chip.

[0055] like Figure 4 As shown, "ON" and "OFF" represent the power consumption-refresh rate curves of the chip when the charge sharing technology is turned on and turned off, respectively. It can be observed that when the charge sharing technology is turned on, the power consumption Poc of the chip is smaller at each refresh rate than when the charge sharing technology is turned off, which means that turning on the charge sharing technology can reduce the power consumption of the chip.

[0056] For the convenience of description, it is defined here that the first sub-clock signal CKx and the second sub-clock signal CKy are respectively formed into a first shared sub-clock signal CKx' and a second shared sub-clock signal CKy' through the above-mentioned charge sharing technology. Figure 3 It can be seen that the starting points of the pulses in the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy' are advanced and the ending points are delayed compared to the corresponding pulses in the first sub-clock signal CKx and the second sub-clock signal CKy.

[0057] It should be noted that, since the gate effective pulse in the gate signal Gate is formed according to the pulse in the corresponding sub-clock signal (both referred to as the above-mentioned first clock pulse), and the end points of the pulses of the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy' formed by the charge sharing technology are delayed, the end point of the gate effective pulse in the gate signal Gate generated thereby is also delayed, resulting in the transistor in the sub-pixel P not being completely closed in time, resulting in the subsequent data signals of other rows leaking into the sub-pixel P of the row, and the lower the refresh rate, the longer the leakage time (the leakage amount can be Figure 3 The normal charge required can be Figure 3 The greater the risk of mischarging, the greater the impact on image quality.

[0058] like Figure 5As shown, "ON" and "OFF" represent the charging rate-refresh rate curves of the chip when the charge sharing technology is turned on and turned off, respectively. It can be observed that when the charge sharing technology is turned on, the chip's power consumption charging rate is smaller at each refresh rate than when the charge sharing technology is turned off, that is, turning on the charge sharing technology will reduce the charging rate; but at high refresh rates, whether the charge sharing technology is turned on has little effect on reducing the charging rate. Only at low refresh rates, turning on the charge sharing technology will cause a larger reduction in the charging rate.

[0059] Combination Figure 2 and Figure 3 As shown, the second clock signal CK' in this embodiment includes a plurality of second clock pulses (having a first pulse width W') corresponding to a plurality of first clock pulses (having a first pulse width W), and the time period of the second clock pulses overlaps with the time period of the corresponding first clock pulses, and the end time of the second clock pulses is later than the end time of the corresponding first clock pulses, that is, the second clock signal CK' can be understood as being obtained by charge sharing in the first clock signal CK. Specifically, the first clock signal CK includes a first sub-clock signal CKx (for example, sub-clock signal CK1) and a second sub-clock signal CKy (for example, sub-clock signal CKn) which are inverted signals to each other. By adopting charge sharing technology for these two sub-clock signals, two corresponding sub-shared sub-clock signals (respectively, the sub-shared sub-clock signal CK1' corresponding to the sub-clock signal CK1, and the sub-shared sub-clock signal CKn' corresponding to the sub-clock signal CKn) can be obtained. Relative to the corresponding sub-clock signal, the end point (that is, the end time) of at least the second clock pulse of each sub-shared sub-clock signal is later than the end time of the corresponding first clock pulse.

[0060] Specifically, since the level converter 30 is used to process the first clock signal CK to generate the second clock signal CK' only when the control signal con is the first control signal, otherwise it can be considered that the second clock signal CK' is not generated, so it can be considered that the gate driver 40 is used to generate the first gate signal according to the first clock signal CK when the refresh rate is less than or equal to the preset value, and to generate the second gate signal according to the second clock signal CK' when the refresh rate is greater than the preset value. Combined with the above discussion, it can be seen that the gate effective pulse in the first gate signal is generated according to the first sub-clock signal CKx and the second sub-clock signal CKy, which are mutually inverted signals in the first clock signal CK, and the gate effective pulse in the second gate signal is generated according to the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy', which are mutually inverted signals in the second clock signal CK'.

[0061] It can be understood that, based on the function of the display device 100 to generate the second clock signal CK' according to the first clock signal CK, the refresh rate RS of the display panel 10 is further obtained through the timing controller 20 and the control signal con is generated according to the device, and the control signal con is the first control signal when the refresh rate RS is greater than the preset value, and the level converter 30 is also used to process the first clock signal CK to generate the second clock signal CK' when the control signal con is the first control signal (that is, when the refresh rate RS is large). That is, whether the charge sharing technology is adopted in the present embodiment is determined according to the refresh rate RS of the display panel 10, rather than adopting the charge sharing technology to process the first clock signal CK to generate the second clock signal CK' under all refresh rates, and the charge sharing technology is only turned on when the refresh rate RS is large, and the charge sharing technology is not turned on when the refresh rate RS is small, thereby avoiding the problem of poor image quality caused by the high risk of mischarging due to the use of the charge sharing technology at low refresh rates.

[0062] In some embodiments, the timing controller 20 is used to control the level converter 30 to process the first clock signal CK to generate the second clock signal CK' through the control signal con when the refresh rate RS is greater than a preset value (for example, but not limited to 144 Hz). Combined with the above discussion, it can be seen that if the charge sharing technology is used to process the first clock signal CK at a low refresh rate, the generated second clock signal CK' will cause a greater risk of mischarging. Therefore, in this embodiment, only when the refresh rate RS is greater than the preset value, the control signal con generated by the timing controller 20 controls the level converter 30 to process the first clock signal CK to generate the second clock signal CK', combined with Figure 1 , Figure 2 and Figure 5 As shown, at this time, due to the high refresh rate, short leakage time and low risk of wrong charging, even if the charge sharing technology is used to generate the second clock signal CK', it will not cause a significant reduction in the charging rate, but can also reduce the power consumption of the chip.

[0063] Of course, when the refresh rate RS is less than or equal to the preset value, the control signal con generated by the timing controller 20 can control the level converter 30 not to process the first clock signal CK to generate the second clock signal CK', but directly generate the gate signal Gate through the first clock signal CK, so as to avoid the following situation: Figure 5 The problem shown is that the charging rate is seriously insufficient due to the high refresh rate.

[0064] In some embodiments, in combination Figure 1 , Figure 2 and Figure 6As shown, the level converter 30 includes: a level conversion module 301, used to generate the first clock signal CK; a charge sharing module 302, electrically connected to the level conversion module 301, used to determine whether to process the first clock signal CK to generate the second clock signal CK' according to the control signal con.

[0065] Specific, combined Figure 1 and Figure 6 As shown, the display device 100 may further include a voltage generator 60, which is used to provide a high-voltage signal VGH and a low-voltage signal VGL to the level converter 30. The timing controller 20 is also used to provide a clock source signal CLK to the level converter 30. The level conversion module 301 can generate a first clock signal CK according to the high-voltage signal VGH, the low-voltage signal VGL and the clock source signal CLK. The high potential and low potential of multiple sub-clock signals (at least including sub-clock signal CK1 to sub-clock signal CKn+1) in the first clock signal CK can be respectively the same as the potential of the high-voltage signal VGH and the potential of the low-voltage signal VGL. The frequencies of the multiple sub-clock signals can be equal to the frequency of the clock source signal CLK, and there is a phase difference between each two of the multiple sub-clock signals.

[0066] Furthermore, the charge sharing module 302 can determine whether to process the first clock signal CK to generate the second clock signal CK' based on the control signal con. When it is necessary to generate the second clock signal CK', the charge sharing module 302 performs charge sharing processing on two of the multiple sub-clock signals that are inverted signals. That is, the line used to transmit the first sub-clock signal CKx (for example, the sub-clock signal CK1) and the line used to transmit the second sub-clock signal CKy (for example, the sub-clock signal CKn) are short-circuited, thereby generating the corresponding two shared sub-clock signals CK1' and CKn' (collectively referred to as the second clock signal CK'); when it is not necessary to generate the second clock signal CK', the charge sharing module 302 directly outputs the first clock signal CK.

[0067] In some embodiments, in combination Figure 2 and Figure 6As shown, the charge sharing module 302 includes: a first input module 3021, used to receive the first sub-clock signal CKx (for example, the sub-clock signal CK1), the first sub-clock signal CKx includes a plurality of first sub-clock pulses (for example, the pulse pc1 of the sub-clock signal CK1); a second input module 3022, used to receive the second sub-clock signal CKy, the second sub-clock signal CKy (for example, the sub-clock signal CKn), including a plurality of second sub-clock pulses corresponding to the plurality of first sub-clock pulses (for example, the pulse pc1 of the sub-clock signal CK1); a first output module 3023, electrically connected to the first input module 3021; ​​a second output module 3024, electrically connected to the second input module 3022; a first switch module 3025, electrically connected between the first input module 3021 and the second input module 3022; wherein the control signal con is used to control whether the first switch module 3025 is turned on at the end of the first sub-clock pulse (for example, the pulse pc1 of the sub-clock signal CK1). That is, the first switch module 3025 is used to control the first output module 3023 to output the first sub-clock signal CKx and control the second output module 3024 to output the second sub-clock signal CKy according to the control signal con, or control the first output module 3023 to output the first shared sub-clock signal CKx' and control the second output module 3024 to output the second shared sub-clock signal CKy'.

[0068] In combination with the above discussion, it can be known that since the first switch module 3025 is electrically connected between the first input module 3021 and the second input module 3022, its conduction condition can determine whether the first sub-clock signal CKx and the second sub-clock signal CKy share charges. When the first switch module 3025 is turned on, the first sub-clock signal CKx and the second sub-clock signal CKy share charges, and the first shared sub-clock signal CKx' output by the first output module 3023 and the second shared sub-clock signal CKy' output by the second output module 3024 are the same, and their potentials are equal to the average of the potentials of the high-voltage signal VGH and the low-voltage signal VGL; when the first switch module 3025 is turned off, the first sub-clock signal CKx and the second sub-clock signal CKy do not share charges, and it can be considered that at this time, the first output module 3023 directly outputs the first sub-clock signal CKx, and the second output module 3024 directly outputs the second sub-clock signal CKy.

[0069] In some embodiments, in combination Figure 2 and Figure 6As shown, the charge sharing module 302 further includes: a second switch module 3026, electrically connected between the first input module 3021 and the first output module 3023; a third switch module 3027, electrically connected between the second input module 3022 and the second output module 3024; wherein the control signal con is used to control the second switch module 3026 and the third switch module 3027 to be turned off when the first switch module 3025 is turned on, and to be turned on when the first switch module 3025 is turned off. That is, the second switch module 3026 is used to control whether the first input module 3021 transmits the first sub-clock signal CKx to the first output module 3023 according to the control signal con; and the third switch module 3027 is used to control whether the second input module 3022 transmits the second sub-clock signal CKy to the second output module 3024 according to the control signal con.

[0070] It can be understood that in this embodiment, the above-mentioned second switch module 3026 and the third switch module 3027 are set, and when the first switch module 3025 is turned on, the first sub-clock signal CKx and the second sub-clock signal CKy share charges. At this time, by controlling the second switch module 3026 and the third switch module 3027 to be turned off, it is not only conducive to the above-mentioned charge sharing to adjust the voltage output by the first output module 3023 and the second output module 3024 to generate the first shared sub-clock signal CKx' and the second shared sub-clock signal CKy', but also it can stop driving the level converter 30 to continue to be driven by the timing controller 20 and the voltage generator 60, thereby reducing the power consumption of the chip.

[0071] Of course, when the first switch module 3025 is turned off, the first sub-clock signal CKx and the second sub-clock signal CKy do not share charges. At this time, by controlling the second switch module 3026 and the third switch module 3027 to be turned on, it is not only conducive to the above-mentioned charge sharing to adjust the voltage output by the first output module 3023 and the second output module 3024, but the level converter 30 continues to be driven by the timing controller 20 and the voltage generator 60, and the first output module 3023 directly outputs the first sub-clock signal CKx, and the second output module 3024 directly outputs the second sub-clock signal CKy.

[0072] In some embodiments, Figure 1 As shown, the timing controller 20 is used to obtain the frame blanking duration of the previous frame, and to determine the corresponding refresh rate RS according to the frame blanking duration; or, the timing controller 20 is used to determine the corresponding refresh rate RS according to a frame start signal.

[0073] As discussed above, the data signal Data includes multiple data voltages of multiple sub-pixels P in corresponding columns. The duration of the interval between two adjacent data voltages in a frame is called the row blanking duration. In two adjacent frames, the duration of the interval between the data voltage of the last row of sub-pixels P in the front frame and the data voltage of the first row of sub-pixels P in the rear frame is called the frame blanking duration. The duration of each frame can be composed of a scanning duration and a frame blanking duration. When the scanning duration is constant, it can be considered that the longer the frame blanking duration, the lower the refresh rate RS, and vice versa. Therefore, the current refresh rate RS can also be determined according to the frame blanking duration.

[0074] Among them, Figure 2 As shown, the frame start signal can also act on the gate driver 40 to drive the multi-stage gate driving unit 401 to generate multiple gate signals Gate step by step. The pulse in the frame start signal triggers one of the gate driving units 401 to generate a gate effective pulse in the corresponding gate signal Gate. Subsequently, the gate effective pulse drives the other stages of the gate driving unit 401 step by step, thereby performing a frame scan. It can be considered that the duration between two adjacent pulses in the frame start signal and the sum of the pulse width of the pulse are equal to the duration of one frame. Therefore, the corresponding refresh rate RS can also be determined according to the frame start signal.

[0075] The present invention also provides a display terminal, comprising a display device as described above and a mainboard electrically connected to the display device, wherein the mainboard is used to transmit at least an image signal to the display device to control the display panel to display an image. Specifically, the mainboard can receive image information and control information input from the front end of the display terminal to convert them into image signals and control signals acting on the display device, the gate signal Gate can be generated according to the control signal, and the data signal Dtaa can be considered to be generated jointly by the image signal and the control signal.

[0076] The present invention also provides a method for driving a display device. The display device 100 includes the display panel 10, a timing controller 20, and a level converter 30 electrically connected to the timing controller 20. Figure 7 As shown, the driving method of the display device includes but is not limited to the following steps.

[0077] S1, controlling the level converter to generate a first clock signal, wherein the first clock signal includes a plurality of first clock pulses.

[0078] In combination with the above discussion, it can be seen that no matter how large the refresh rate RS is, the level converter 30 needs to generate the first clock signal CK according to the clock source signal CLK provided by the timing controller 20 and the high voltage signal VGH and the low voltage signal VGL provided by the voltage generator 60, such as Figure 2 As shown, the first clock signal CK includes a plurality of sub-clock signals (including at least Figure 2 The sub-clock signal CK1 to the sub-clock signal CKn+1), the multiple pulses pc1 in the sub-clock signal CK1, the multiple pulses pc2 in the sub-clock signal CK2, the multiple pulses pcn in the sub-clock signal CKn, and the multiple pulses pcn+1 in the sub-clock signal CKn+1 are all referred to as first clock pulses.

[0079] S2, controlling the timing controller to obtain the refresh rate of the display panel, and generating a control signal according to the refresh rate, wherein the control signal is a first control signal when the refresh rate is greater than a preset value.

[0080] That is, the control signal con generated by the timing controller 20 according to the refresh rate RS of the display panel 10 may include the refresh rate RS information of the display panel 10, which is specifically reflected in that the control signal con is a first control signal when the refresh rate is greater than a preset value, and is a second control signal when the refresh rate is less than or equal to the preset value.

[0081] S3, controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal, wherein the second clock signal includes multiple second clock pulses corresponding to multiple first clock pulses, the time period of the second clock pulse overlaps with the time period of the first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

[0082] In combination with the above discussion, it can be seen that the second clock signal CK' is obtained by the charge sharing technology of the first clock signal CK, and whether to process the first clock signal CK to generate the second clock signal CK' in this embodiment is determined according to the control signal con, that is, whether to use charge sharing to generate the second clock signal CK' for the first clock signal CK is determined according to the refresh rate RS of the display panel 10.

[0083] Specifically, when the control signal con is the first control signal, it indicates that the refresh rate is high, and the first clock signal CK needs to be processed to generate the second clock signal CK'. When the control signal con is the second control signal, it indicates that the refresh rate is low, and the first clock signal CK does not need to be processed to generate the second clock signal CK'.

[0084] In some embodiments, after step S3, the following steps are included but not limited to:

[0085] S4, controlling the gate driver to generate a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

[0086] In combination with the above discussion, it can be seen that in this embodiment, only when the refresh rate RS is greater than the preset value, the control signal con generated by the timing controller 20 controls the level converter 30 to process the first clock signal CK to generate the second clock signal CK'. Figure 1 , Figure 2 and Figure 5 As shown, at this time, due to the high refresh rate, short leakage time and small risk of wrong charging, even if the charge sharing technology is used to generate the second clock signal CK', and further generate the second gate signal through the second clock signal CK' to control the opening status of multiple rows of sub-pixels P in the display panel 10, it will not cause a significant reduction in the charging rate. On the contrary, it can also reduce the power consumption of the chip.

[0087] In some embodiments, the level converter 30 includes a level conversion module 301 and a charge sharing module 302 electrically connected to the level conversion module 301; step S1 includes: controlling the level conversion module to generate the first clock signal; step S3 includes: controlling the charge sharing module to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

[0088] That is, the level conversion module 301 can generate the first clock signal CK according to the high-voltage signal VGH, the low-voltage signal VGL and the clock source signal CLK, and the charge sharing module 302 can determine whether to process the first clock signal CK to generate the second clock signal CK' according to the control signal con. When it is necessary to generate the second clock signal CK', the charge sharing module 302 performs charge sharing processing on two of the multiple sub-clock signals that are inverted signals to each other, that is, the line used to transmit the first sub-clock signal CKx (for example, the sub-clock signal CK1) and the line used to transmit the second sub-clock signal CKy (for example, the sub-clock signal CKn) are short-circuited, thereby generating the corresponding two shared sub-clock signals CK1', CKn' (collectively referred to as the second clock signal CK'); when it is not necessary to generate the second clock signal CK', the charge sharing module 302 directly outputs the first clock signal CK.

[0089] The display device and its driving method, as well as the structure of the display terminal provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: include: Display panel; A timing controller, configured to generate a control signal according to a refresh rate of the display panel, wherein the control signal is a first control signal when the refresh rate is greater than a preset value; a level converter, electrically connected to the timing controller, for generating a first clock signal, and for processing the first clock signal to generate a second clock signal when the control signal is the first control signal; Among them, the first clock signal includes multiple first clock pulses, the second clock signal includes multiple second clock pulses corresponding to the multiple first clock pulses, the time period of the second clock pulses overlaps with the time period of the corresponding first clock pulses, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

2. The display device according to claim 1, wherein: include: A gate driver, integrated in the display panel or independently provided from the display panel, for generating a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and for generating a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

3. The display device according to claim 1 or 2, characterized in that: The level converter comprises: A level conversion module, used for generating the first clock signal; The charge sharing module is used to determine whether to process the first clock signal to generate the second clock signal according to the control signal.

4. The display device according to claim 3, characterized in that The first clock signal includes a first sub-clock signal and a second sub-clock signal which are inverted signals to each other, and the second clock signal includes a first shared sub-clock signal corresponding to the first sub-clock signal and a second shared sub-clock signal corresponding to the second sub-clock signal; The charge sharing module comprises a first input module, a second input module, a first output module, a second output module and a first switch module: The first input module is used to receive the first sub-clock signal, where the first sub-clock signal includes a plurality of first sub-clock pulses; The second input module is used to receive the second sub-clock signal, wherein the second sub-clock signal includes a plurality of second sub-clock pulses corresponding to a plurality of the first sub-clock pulses; The first switch module is used to control the first output module to output the first sub-clock signal and control the second output module to output the second sub-clock signal according to the control signal, or control the first output module to output the first shared sub-clock signal and control the second output module to output the second shared sub-clock signal.

5. The display device according to claim 4, characterized in that The charge sharing module further comprises: a second switch module, configured to control, according to the control signal, whether the first input module transmits the first sub-clock signal to the first output module; The third switch module is used to control the second input module to transmit the second sub-clock signal to the second output module according to the control signal.

6. The display device according to claim 1, wherein: The timing controller is used to obtain the frame blanking duration of the previous frame, and to calculate the corresponding refresh rate according to the frame blanking duration; Alternatively, the timing controller is used to calculate the corresponding refresh rate according to a frame start signal.

7. A display terminal, characterized in that: It comprises a display device as claimed in any one of claims 1 to 6 and a mainboard electrically connected to the display device, wherein the mainboard is used to at least transmit an image signal to the display device to control the display panel to display an image.

8. A method for driving a display device, characterized in that: The display device comprises a display panel, a timing controller, and a level converter electrically connected to the timing controller. The driving method of the display device comprises: controlling the level converter to generate a first clock signal, wherein the first clock signal includes a plurality of first clock pulses; Controlling the timing controller to obtain a refresh rate of the display panel, and generating a control signal according to the refresh rate, wherein the control signal is a first control signal when the refresh rate is greater than a preset value; Control the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal, wherein the second clock signal includes multiple second clock pulses corresponding to multiple first clock pulses, the time period of the second clock pulse overlaps the time period of the first clock pulse, and the end time of the second clock pulse is later than the end time of the corresponding first clock pulse.

9. The method for driving a display device according to claim 8, wherein: The display device includes a gate driver integrated into the display panel or arranged independently of the display panel; Wherein, after the step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal, the step includes: The gate driver is controlled to generate a first gate signal according to the first clock signal when the refresh rate is less than or equal to the preset value, and to generate a second gate signal according to the second clock signal when the refresh rate is greater than the preset value.

10. The method for driving a display device according to claim 8 or 9, characterized in that: The level converter includes a level conversion module and a charge sharing module electrically connected to the level conversion module; The step of controlling the level converter to generate a first clock signal includes: Controlling the level conversion module to generate the first clock signal; The step of controlling the level converter to process the first clock signal to generate a second clock signal when the control signal is the first control signal includes: The charge sharing module is controlled to process the first clock signal to generate the second clock signal when the control signal is the first control signal.

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