Display panel and manufacturing method thereof

Abstract

The display panel manufacturing method of the present invention may comprise: a step of preparing a base layer including a plurality of pads; a step of etching a part of the base layer to form an opening to expose the plurality of pads; a step of preparing a circuit film including a preliminary circuit film wiring therein; a step of irradiating the circuit film with a laser beam to form a circuit film wiring from the preliminary circuit film wiring; a step of disposing the base layer and the circuit film on a stage in such a manner that the plurality of pads and the circuit film wiring overlap, and disposing a transfer substrate on the base layer; and a step of irradiating the transfer substrate with a first laser light to form a conductive pattern on the plurality of pads and the circuit film wiring.

Description

Technical Field

[0001] The invention relates to a display panel and a method for manufacturing the display panel. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] Recently, in response to market demands, research is being conducted to reduce the area in which an image is not displayed in a display panel, and at the same time, research is being conducted to expand the display area in which an image is displayed to a user. Summary of the invention

[0004] An object of the present invention is to provide a display panel with a reduced non-display area and a method for manufacturing the display panel.

[0005] It may be that a display panel manufacturing method according to an embodiment of the present invention includes: a step of preparing a base layer including a plurality of solder pads; a step of etching a portion of the base layer to form an opening to expose the plurality of solder pads; a step of preparing a circuit film including a prepared circuit film wiring inside; a step of irradiating a laser to the circuit film to form a circuit film wiring from the prepared circuit film wiring; a step of arranging the base layer and the circuit film on a workbench in such a manner that the plurality of solder pads and the circuit film wiring overlap and arranging a transfer substrate on the base layer; and a step of irradiating a first laser to the transfer substrate to form a conductive pattern on the plurality of solder pads and the circuit film wiring.

[0006] It may be that the step of forming the circuit film wiring includes the step of etching a portion of the circuit film to expose a portion of the preliminary circuit film wiring.

[0007] The transfer substrate may include a donor film and a transparent substrate disposed on the donor film.

[0008] It may be that the step of forming the conductive pattern includes: a step of irradiating the first laser in a first direction with a laser device; a step of changing the direction of the first laser to a direction toward the transparent substrate by a lens configured on the transfer substrate; and a step of transferring a portion of the donor film with the first laser irradiated toward the transparent substrate.

[0009] Alternatively, the step of forming the conductive pattern further includes: moving the laser device and the lens in the first direction or in a second direction intersecting the first direction.

[0010] Alternatively, the step of forming the conductive pattern further includes: moving the workbench in the first direction or in a second direction intersecting the first direction.

[0011] It may be that the step of forming the conductive pattern includes: a step of irradiating the first laser in a first direction by a laser device; a step of changing the direction of the first laser to a direction toward the transparent substrate by a scanner configured on the transfer substrate; and a step of transferring a portion of the donor film by continuously changing the direction of the first laser.

[0012] It may be that the step of forming the conductive pattern includes: a step of configuring a mask on the transfer substrate; a step of irradiating the first laser with a laser device along the mask; and a step of transferring a portion of the donor film by transmitting the first laser through the mask, wherein the first laser is a line laser.

[0013] Alternatively, the display panel manufacturing method further includes: irradiating a second laser onto an area where the circuit film wiring and the conductive pattern overlap, wherein the second laser passes through the conductive pattern to combine the circuit film wiring and the conductive pattern.

[0014] The second laser may be an infrared laser.

[0015] The base layer may include a first region and a second region, a plurality of pixels may be arranged in the first region, and the opening may overlap with the first region of the base layer.

[0016] The step of configuring the base layer and the circuit film and configuring the transfer substrate on the base layer may include the step of configuring the base layer and the circuit film so that the plurality of pads and the circuit film wiring overlap in the opening of the base layer.

[0017] It may be that the step of configuring the base layer and the circuit film and configuring the transfer substrate on the base layer includes: the step of configuring the base layer and the circuit film in a manner that the multiple pads, a portion of the circuit film, and the circuit film wiring overlap in the opening portion of the base layer.

[0018] It may be that the display panel according to one embodiment of the present invention includes: a base layer, defining a first area and a second area; a plurality of pixels, arranged on the first area of ​​the base layer; a plurality of pads, arranged between the upper and lower sides of the base layer; a circuit film, arranged on the plurality of pads and the lower side of the base layer; circuit film wiring, arranged on the plurality of pads, a portion of the circuit film wiring extending from the circuit film; and a conductive pattern, arranged on the circuit film wiring and the plurality of pads, defining an opening in the base layer in the thickness direction of the base layer, and the plurality of pads, the circuit film wiring and the conductive pattern being arranged within the opening.

[0019] A portion of the circuit film may be disposed in the opening.

[0020] It may be that the base layer includes: a first sub-base layer, including the bottom side of the base layer and defining the opening portion; a barrier layer, arranged on the first sub-base layer; and a second sub-base layer, arranged on the barrier layer and including the top side of the base layer, and the multiple pads are arranged in the barrier layer and exposed through the opening portion of the first sub-base layer.

[0021] On a plane, a width of the circuit film wiring is equal to or smaller than a width of each of the plurality of pads.

[0022] The width of the conductive pattern may be equal to or smaller than the width of the circuit film wiring on a plane.

[0023] The opening may overlap with the first region.

[0024] The opening may overlap with the first region and the second region.

[0025] It may be that the conductive pattern combines the circuit film wiring and the plurality of pads.

[0026] It may be that the conductive pattern is in the form of a thin film.

[0027] As described above, the area of ​​the non-display region can be reduced, and thus a display device with a reduced frame width can be provided.

[0028] The conductive pattern of the present invention can be formed by transferring a donor film. In this case, the spacing between the conductive patterns can be formed to be short compared to the case where the conductive material is coated with ink. In addition, the conductive pattern formed by transferring the donor film can be in the form of a thin film. In this case, compared to the case where the conductive material is coated in a hemispherical form, the damage to the base layer caused by the subsequent laser process can be reduced or removed.

[0029] In addition, the display panel manufacturing method of the present invention can reduce or remove the indentation that occurs in the subsequent process of combining the circuit film wiring and the pad by forming an opening in the base layer and forming the circuit film wiring exposed to the outside of the circuit film. Therefore, even if the circuit film is formed in an area overlapping the display area, the display quality of the display device of the present invention can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0031] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0032] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0033] Figure 4 is a plan view of a display panel according to an embodiment of the present invention.

[0034] Figure 5a is an enlarged view of an attachment area according to an embodiment of the present invention.

[0035] Figure 5b is a perspective view of an attachment area according to an embodiment of the present invention.

[0036] Figure 6 It is along Figure 5a A cross-sectional view taken along the I-I' line.

[0037] Figure 7 is a plan view of a display panel according to an embodiment of the present invention.

[0038] Figures 8 to 13 is a perspective view showing a part of a method for manufacturing a display panel according to an embodiment of the present invention.

[0039] (Explanation of Reference Numerals)

[0040] 1000: Display device 100: Display panel

[0041] 110: Base layer 110A1: First region

[0042] 110A2: Second area OP: Opening

[0043] COF: Circuit Film CFL: Circuit Film Wire

[0044] MF: Conductive pattern TF: Transfer substrate

[0045] DF: donor film TS: transparent substrate DETAILED DESCRIPTION

[0046] In this specification, when any constituent element (or region, layer, part, etc.) is mentioned as being "on" other constituent elements, "connected to" or "combined to" other constituent elements, it means that it can be directly configured / connected / combined to other constituent elements or a third constituent element can be configured between them.

[0047] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations that can be defined by the associated components.

[0048] The terms first, second, etc. may be used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are only used to distinguish one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Singular expressions include plural expressions unless otherwise expressly indicated in the context.

[0049] In addition, terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between components shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0050] The terms "including" or "having" should be understood as being used to specify the existence of the features, numbers, steps, tasks, constituent elements, parts or their combinations recorded in the specification, and do not preclude the existence or additional possibilities of one or more other features or numbers, steps, tasks, constituent elements, parts or their combinations.

[0051] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as too idealistic or too formalistic unless explicitly defined herein.

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view of a display device 1000 according to an embodiment of the present invention.

[0054] Reference Figure 1 , the display device 1000 may be a device activated by an electrical signal. For example, the display device 1000 may be a portable phone, a tablet, a car navigation system, a game console, or a wearable device, but is not limited thereto. Figure 1 In FIG. 1 , the display device 1000 is exemplarily shown to be a mobile phone.

[0055] The display device 1000 includes a display surface DSF defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The display device 1000 can provide an image IM to a user through the display surface DSF. The display surface DSF may include a display area 1000A and a non-display area 1000NA around the display area 1000A. It may be that the display area 1000A displays the image IM, and the non-display area 1000NA does not display the image IM. The non-display area 1000NA may surround the display area 1000A. However, it is not limited thereto, and the shape of the display area 1000A and the shape of the non-display area 1000NA may be deformed.

[0056] According to the present invention, the area of ​​the non-display region 1000NA can be reduced. Therefore, the ratio of the area occupied by the display region 1000A in the overall area of ​​the display surface DSF can be increased. Therefore, a display device 1000 with a reduced frame width can be provided. The specific description will be given later.

[0057] Hereinafter, a direction substantially perpendicularly intersecting a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 is a reference for distinguishing the front and back sides of each component. In this specification, "on a plane" may be defined as a state observed in the third direction DR3. Hereinafter, the first to third directions DR1, DR2, and DR3 are referred to as directions indicated by the first to third directional axes, respectively, and the same reference numerals are used.

[0058] Figure 2 is a schematic cross-sectional view of a display device 1000 according to an embodiment of the present invention.

[0059] Reference Figure 2, the display device 1000 may include a display panel 100, an optical film 200, a window 300 and a lower film 400. The display device 1000 may include a structure in which a window 300, an optical film 200, a display panel 100 and a lower film 400 are stacked in sequence. In one embodiment of the present invention, a part of the above-mentioned structure can be omitted, or other structures can be added. An adhesive layer can be configured between the components as needed. The adhesive layer can be an optically transparent adhesive component (OCA, Optically Clear Adhesive) or a pressure-sensitive adhesive film (PSA, Pressure Sensitive Adhesive film), but is not particularly limited thereto. The adhesive layer described below may also include the same substance as it, a conventional adhesive.

[0060] The display panel 100 can display an image and sense an external input applied from the outside. The external input may include various forms of input provided from the outside of the display device 1000. For example, the external input may include contact through a part of the user's body such as a hand, and may also include an external input applied close to or adjacent to the display device 1000 at a predetermined distance (e.g., hovering). In addition, the external input may have various forms such as force, pressure, temperature, light, etc. The external input may also be provided by a separate device, such as an active pen or a digital pen.

[0061] The optical film 200 may reduce the reflectivity of light incident from the outside. The optical film 200 may include a phase retarder and / or a polarizer. The optical film 200 may include at least a polarizing film. In this case, the optical film 200 may be attached to the display panel 100 through an adhesive layer.

[0062] Alternatively, the optical film 200 may include a color filter. The color filter may have a predetermined arrangement. It may be considered to be included in the display layer DPL (refer to Figure 3 ) determines the arrangement of the color filters. In addition, the optical film 200 may further include a black matrix adjacent to the color filters. In this case, the adhesive layer may be omitted between the optical film 200 and the display panel 100.

[0063] Alternatively, the optical film 200 may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer configured on different layers from each other. The first reflected light and the second reflected light respectively reflected in the first reflective layer and the second reflective layer may destructively interfere, and accordingly, the external light reflectivity may be reduced. In this case, the adhesive layer between the optical film 200 and the display panel 100 may be omitted.

[0064] The window 300 may be disposed on the optical film 200. The window 300 may include an optically transparent insulating material. For example, the window 300 may include glass or plastic. The window 300 may have a multi-layer structure or a single-layer structure. For example, the window 300 may include a plurality of plastic films bonded with an adhesive, or include a glass substrate and a plastic film bonded with an adhesive.

[0065] The lower film 400 may be disposed under the display panel 100. For example, the lower film 400 may be a protective layer that blocks or absorbs light incident to the display panel 100. For example, the lower film 400 may be a colored film. However, it is not particularly limited thereto.

[0066] Figure 3 is a cross-sectional view of a display panel 100 according to an embodiment of the present invention.

[0067] Reference Figure 3 , the display panel 100 may include a sensor layer ISL configured on the display layer DPL and on the display layer DPL. The display layer DPL may be a structure that substantially generates an image. The display layer DPL may be a light-emitting display layer, for example, the display layer DPL may be an organic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer. The sensor layer ISL may be configured on the display layer DPL. The sensor layer ISL may sense an external input applied from the outside. The sensor layer ISL may also be an external sensor attached to the display layer DPL, and the sensor layer ISL may be an integrated sensor continuously formed in the manufacturing process of the display layer DPL.

[0068] The display layer DPL may include a base layer 110 , a circuit layer 120 , a light emitting element layer 130 , and an encapsulation layer 140 .

[0069] The base layer 110 may be a component that provides a base surface for configuring the circuit layer 120. The base layer 110 may include a synthetic resin layer. The synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. In addition, the base layer 110 may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0070] At least one inorganic layer is formed on the base layer 110. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, the display layer DPL includes a buffer layer BFL.

[0071] The buffer layer BFL may improve the bonding force between the base layer 110 and the semiconductor pattern. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0072] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and the semiconductor pattern may also include amorphous silicon, low temperature polysilicon, or oxide semiconductor.

[0073] exist Figure 3 Only a portion of the semiconductor pattern is shown, and semiconductor patterns may be configured in other areas. The semiconductor pattern may be arranged in a specific rule across pixels. The semiconductor pattern may have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. It may be that a P-type transistor includes a doped region doped with a P-type dopant, and an N-type transistor includes a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a lower concentration than the first region.

[0074] The conductivity of the first region may be greater than that of the second region, and the first region may substantially function as an electrode or a signal line. The second region may substantially be equivalent to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and yet another portion may be a connecting electrode or a connecting signal line.

[0075] Each of the pixels may have an equivalent circuit including seven transistors, a capacitor, and a light emitting element, and the equivalent circuit of the pixel may be deformed in various forms. Figure 3 Schematically shows a transistor 100PC and a light emitting element 100PE included in a pixel.

[0076] The source SC, active region AL (or active area, activation region), and drain DR of the transistor 100PC may be formed from a semiconductor pattern. The source SC and the drain DR may extend from the active region AL in opposite directions to each other in a cross section. Figure 3 1 shows a portion of a connection signal wiring SCL formed from a semiconductor pattern. Although not shown separately, the connection signal wiring SCL can be connected to the drain DR of the transistor 100PC in a plane.

[0077] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap a plurality of pixels in common and cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit layer 120 described later may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned substances, but is not limited thereto.

[0078] The gate GT of the transistor 100PC is disposed on the first insulating layer 10. The gate GT may be a part of the metal pattern. The gate GT overlaps the active area AL. In the process of doping the semiconductor pattern, the gate GT may function as a mask.

[0079] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate electrode GT. The second insulating layer 20 may overlap the pixel in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0080] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single layer or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0081] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal wiring SCL through a contact hole CNT-1 penetrating the first, second, and third insulating layers 10, 20, and 30.

[0082] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single-layer silicon oxide layer. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0083] The second connection electrode CNE2 may be disposed on the fifth insulating layer 50 . The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT- 2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50 .

[0084] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0085] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element 100PE. For example, the light emitting element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED. Hereinafter, the light emitting element 100PE is an organic light emitting element as an example for explanation, but it is not particularly limited thereto.

[0086] The light emitting element 100PE may include a first electrode AE, a light emitting layer EL and a second electrode CE.

[0087] The first electrode AE ​​may be disposed on the sixth insulating layer 60 . The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT- 3 penetrating the sixth insulating layer 60 .

[0088] The pixel defining film 70 may be disposed on the sixth insulating layer 60 and cover a portion of the first electrode AE. An opening 70 -OP is defined in the pixel defining film 70. The opening 70 -OP of the pixel defining film 70 exposes at least a portion of the first electrode AE.

[0089] Display area DA (refer to Figure 4 ) may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. In the present embodiment, the light emitting region PXA is defined as a portion of the first electrode AE ​​exposed by the opening 70-OP.

[0090] The light-emitting layer EL may be disposed on the first electrode AE. The light-emitting layer EL may be disposed in a region corresponding to the opening 70-OP. That is, the light-emitting layer EL may be separately formed in each pixel. When the light-emitting layer EL is separately formed in each pixel, each of the light-emitting layers EL may emit light of at least one color of blue, red, and green. However, the invention is not limited thereto, and the light-emitting layer EL may also be connected and provided in common in the pixel. In this case, the light-emitting layer EL may also provide blue light, or provide white light.

[0091] The second electrode CE may be disposed on the light emitting layer EL. The second electrode CE may have an integral shape and be commonly disposed in a plurality of pixels.

[0092] Although not shown, a hole control layer may be configured between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may be commonly configured in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and further include a hole injection layer. An electron control layer may be configured between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and further include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in a plurality of pixels using an open mask.

[0093] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer stacked in sequence, but the layers constituting the encapsulation layer 140 are not limited thereto.

[0094] The inorganic layer may protect the light emitting element layer 130 from moisture and oxygen, and the organic layer may protect the light emitting element layer 130 from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic organic layer, but is not limited thereto.

[0095] The sensor layer ISL may include a first substrate layer 150 , a first conductive layer 160 , a sensing insulating layer 170 , a second conductive layer 180 , and a cover insulating layer 190 .

[0096] The first base layer 150 may be an inorganic layer including at least any one of silicon nitride, silicon oxynitride and silicon oxide. Alternatively, the first base layer 150 may also be an organic layer including epoxy resin, acrylic resin or imide resin. The first base layer 150 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. According to an embodiment, the first base layer 150 may also be omitted.

[0097] Each of the first conductive layer 160 and the second conductive layer 180 may have a single layer configuration, or a multi-layer configuration stacked along the third direction DR3.

[0098] The conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or alloys thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0099] The conductive layer of the multilayer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0100] At least one of the sensing insulating layer 170 and the capping insulating layer 190 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0101] At least one of the sensing insulating layer 170 and the cover insulating layer 190 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0102] Figure 4 is a plan view of a display panel 100 according to an embodiment of the present invention. Figure 4 is a plan view showing the lower surface B_110 of the display panel 100 .

[0103] Reference Figure 4 The display panel 100 may include a display area DA and a non-display area NDA. The first area 110A1 of the base layer 110 may overlap with the display area DA, and the second area 110A2 of the base layer 110 may overlap with the non-display area NDA. That is, the first area 110A1 of the base layer 110 may be a base surface for providing components arranged in the display area DA, and the second area 110A2 of the base layer 110 may be a base surface for providing components arranged in the non-display area NDA.

[0104] A plurality of pixels PX may be disposed in the display area DA. For example, a plurality of pixels PX may be disposed on the first area 110A1. A plurality of wirings may be disposed on the base layer 110 and electrically connected to the pixels PX.

[0105] On the upper surface of the base layer 110 U_110 (refer to Figure 5b ) and the bottom B_110 may be provided with a plurality of pads PD. An attachment area AA' to which a circuit film COF may be attached may be defined on the display panel 100. The circuit film COF may be provided under the display panel 100, and the circuit film COF may be attached to a plurality of pads PD exposed through an opening OP defined in the base layer 110.

[0106] The attachment area AA′ may overlap the display area DA. That is, the opening OP of the base layer 110 may overlap the first area 110A1 of the base layer 110. However, the position of the opening OP of the base layer 110 is an exemplary case and is not limited thereto.

[0107] Figure 5a FIG. 4 is an enlarged view of an attachment area AA′ according to an embodiment of the present invention. Figure 5b FIG. 4 is a perspective view of an attachment area AA′ according to an embodiment of the present invention. Figure 6 It is along Figure 5a A cross-sectional view taken along the I-I' line.

[0108] Reference Figures 4 to 6 The base layer 110 may include an upper surface U_110 and a lower surface B_110. The upper surface U_110 of the base layer 110 may be connected to the circuit layer 120 (see Figure 3 The lower surface B_110 of the base layer 110 may be a surface opposite to the upper surface U_110 of the base layer 110, and may be a surface of the display panel 100 (see Figure 3 ). An opening OP may be defined in the base layer 110 in a thickness direction (eg, third direction DR3) of the base layer 110. The base layer 110 may include polyimide (PI).

[0109] The base layer 110 may include a first sub-base layer PS1, barrier layers BL1, BL2, and a second sub-base layer PS2. The first sub-base layer PS1 may include a lower surface B_110 of the base layer 110, and an opening OP is defined in the first sub-base layer PS1. The barrier layers BL1 and BL2 may be disposed on the first sub-base layer PS1. The barrier layers BL1 and BL2 may include a first barrier layer BL1 and a second barrier layer BL2. The first barrier layer BL1 may be disposed on the first sub-base layer PS1, and the second barrier layer BL2 may be disposed on the first barrier layer BL1. The second sub-base layer PS2 may be disposed on the barrier layers BL1 and BL2, and may include an upper surface U_110 of the base layer 110.

[0110] The display panel 100 may include a plurality of pads PD, a circuit film COF, a circuit film wiring CFL, and a conductive pattern MF. The plurality of pads PD, a portion of the circuit film COF, the circuit film wiring CFL, and the conductive pattern MF may be disposed within the opening OP.

[0111] The plurality of pads PD may be disposed between the upper surface U_110 and the lower surface B_110 of the base layer 110. The plurality of pads PD may be disposed within the barrier layers BL1 and BL2. The plurality of pads PD may be exposed through the opening OP of the first sub-base layer PS1.

[0112] The circuit film COF may be disposed under the display panel 100. In detail, the circuit film COF may be disposed on the plurality of pads PD and the lower face B_110 of the base layer 110. The circuit film COF may include polyimide (PI).

[0113] The circuit film wiring CFL may be configured on a plurality of pads PD. A portion P1 (or a first portion) of the circuit film wiring CFL may be exposed to the outside of the circuit film COF, and another portion P2 (or a second portion) of the circuit film wiring CFL may be included in the circuit film COF. That is, a portion P1 of the circuit film wiring CFL may extend from the circuit film COF. The circuit film wiring CFL may include a metal substance. For example, the circuit film wiring CFL may include copper (Cu) or silver (Ag). The circuit film wiring CFL may be provided in plurality. For example, the circuit film wiring CFL may be provided in a one-to-one correspondence with a plurality of pads PD. On a plane, the width of one circuit film wiring CFL may be equal to or less than the width of each of the plurality of pads PD.

[0114] The conductive pattern MF can be arranged on the circuit film wiring CFL and the plurality of pads PD. The conductive pattern MF of the present invention can be transferred to the donor film DF (see Fig.12a ) is formed. When the donor film DF is transferred to form the conductive pattern MF, the spacing between the conductive patterns MF can be formed to be short. For example, the spacing between the two conductive patterns MF can be more than 10 microns and less than 20 microns. The conductive pattern MF can be in the form of a thin film. That is, it can be that the conductive pattern MF does not have a hemispherical shape and the thickness of the conductive pattern MF is constant. As the conductive pattern MF is in the form of a thin film, compared to the case where the conductive material is coated in a hemispherical form, damage to the base layer 110 caused by a subsequent laser process can be reduced or removed.

[0115] The conductive pattern MF may be combined with the circuit film wiring CFL and the plurality of pads PD. The conductive pattern MF may be provided in plurality. For example, the conductive pattern MF may be provided in one-to-one correspondence with the circuit film wiring CFL or the plurality of pads PD. On a plane, the width of one conductive pattern MF may be equal to or less than the width of one circuit film wiring CFL.

[0116] Figure 7 is a plan view of a display panel 100 a according to an embodiment of the present invention.

[0117] Reference Figure 7, the display panel 100a may include a display area DAa and a non-display area NDAa. The first area 110A1a of the base layer 110a may overlap with the display area DAa, and the second area 110A2a of the base layer 110a may overlap with the non-display area NDAa. That is, the first area 110A1a of the base layer 110a may be a base surface for providing components configured in the display area DAa, and the second area 110A2a of the base layer 110a may be a base surface for providing components configured in the non-display area NDAa.

[0118] A plurality of pixels PX may be disposed in the display area DAa. For example, a plurality of pixels PX may be disposed on the first area 110A1a. A plurality of wirings may be disposed on the base layer 110a and electrically connected to the pixels PX.

[0119] The upper surface U_110 of the base layer 110a (see Figure 5b ) and the bottom B_110 may be provided with a plurality of pads PD. An attachment area AA' to which a circuit film COF may be attached may be defined on the display panel 100a. The circuit film COF may be provided under the display panel 100a, and the circuit film COF may be attached to a plurality of pads PD exposed through an opening OPa defined in the base layer 110a.

[0120] The display panel 100 a may define an attachment area AA′ to which the circuit film COF is attached. Figure 7 The adhesion-enabled area AA' may overlap the display area DAa and the non-display area NDAa. That is, the opening OPa of the base layer 110a may overlap the first area 110A1a and the second area 110A2a of the base layer 110a.

[0121] Figures 8 to 13 FIG. 1 is a perspective view showing a part of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 8 to 13 When Figures 1 to 7 The same / similar structures as those described in the present invention are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0122] According to an embodiment of the present invention, a display panel manufacturing method may include: a step of preparing a base layer including a first sub-base layer, a barrier layer arranged on the first sub-base layer, a second sub-base layer arranged on the barrier layer, and a plurality of pads arranged in the barrier layer; a step of etching a portion of the first sub-base layer to form an opening to expose the plurality of pads; a step of preparing a circuit film including a prepared circuit film wiring inside; a step of irradiating the circuit film with a laser to form a circuit film wiring from the prepared circuit film wiring; a step of arranging the base layer and the circuit film on a workbench in such a manner that the plurality of pads and the circuit film wiring overlap and arranging a transfer substrate on the base layer; and a step of irradiating the transfer substrate with a first laser to form a conductive pattern on the plurality of pads and the circuit film wiring.

[0123] Below, through Figures 8 to 13 A method of forming the conductive pattern MF will be described. Figures 8 to 13 The illustration is centered on the adhesion area AA′ of the base layer 110 .

[0124] Reference Figure 8 The display panel manufacturing method according to the present embodiment may include the step of preparing a base layer 110. The base layer 110 may include polyimide (PI). The base layer 110 may include an upper surface U_110 and a lower surface B_110. The upper surface U_110 of the base layer 110 may be connected to the circuit layer 120 (refer to Figure 3 The lower surface B_110 of the base layer 110 may be a surface opposite to the upper surface U_110 of the base layer 110, and may be a surface of the display panel 100 (see Figure 3 ) below.

[0125] The base layer 110 provided in the present embodiment may include a plurality of pads PD inside. The plurality of pads PD may extend along the second direction DR2 inside the base layer 110. The base layer 110 may include a first region 110A1 and a second region 110A2 (see Figure 4 ). It may be that the first area 110A1 of the base layer 110 and the display panel 100 (see Figure 4 ) display area DA (refer to Figure 4 ) overlaps, the second area 110A2 of the base layer 110 overlaps with the non-display area NDA (refer to Figure 4 That is, a plurality of pixels PX may be arranged on the first region 110A1 of the base layer 110 (see Figure 4 ).exist Figure 8 Schematically, the attachment-enabled area AA′ overlapping with the first area 110A1 is shown.

[0126] Afterwards, refer to Fig. 9 According to the display panel manufacturing method of the present embodiment, the step of etching a portion of the base layer 110 to form an opening OP to expose the plurality of pads PD may be included. The opening OP may be formed by etching a portion of the base layer 110 from the bottom B_110 of the base layer 110 in the thickness direction of the base layer 110. That is, the opening OP may be defined in the thickness direction of the base layer 110 (e.g., the third direction DR3).

[0127] The opening OP of the base layer 110 may overlap with the first region 110A1 of the base layer 110. However, the position of the opening OP of the base layer 110 is an exemplary case and is not limited thereto. For example, the opening OP of the base layer 110 may overlap with the first region 110A1 and the second region 110A2 (see Figure 4 )overlapping.

[0128] Afterwards, refer to Fig.10 , the display panel manufacturing method according to the present embodiment may include the step of preparing a circuit film COF. The circuit film COF provided in the present embodiment may include a preliminary circuit film wiring CFL_I inside. The preliminary circuit film wiring CFL_I may extend along the second direction DR2 inside the circuit film COF. The circuit film COF may include polyimide (PI), and the preliminary circuit film wiring CFL_I may include a metal substance. For example, the preliminary circuit film wiring CFL_I may include copper (Cu) or silver (Ag).

[0129] Afterwards, refer to Fig.11 , the display panel manufacturing method according to the present embodiment may include the step of forming a circuit film wiring CFL from the prepared circuit film wiring CFL_I. The step of forming the circuit film wiring CFL may include the step of etching a portion of the circuit film COF to expose a portion of the prepared circuit film wiring CFL_I. For example, a laser may be irradiated to the circuit film COF to etch a portion of the circuit film COF to expose a portion of the prepared circuit film wiring CFL_I inside the circuit film COF. The circuit film wiring CFL may include a first portion P1 and a second portion P2. The first portion P1 of the circuit film wiring CFL may be exposed to the outside of the circuit film COF, and the second portion P2 of the circuit film wiring CFL may be included in the circuit film COF. For example, the first portion P1 of the circuit film wiring CFL may extend from the circuit film COF along the second direction DR2.

[0130] According to the present invention, as the base layer 110 (refer to Fig. 9 ) forms an opening OP (refer to Fig. 9 ), and forming a circuit film wiring CFL exposed to the outside of the circuit film COF, can reduce or remove the subsequent combination of the circuit film wiring CFL and the pad PD (refer to Fig. 9Therefore, even if the circuit film COF is formed on the display area DA (refer to Figure 4 ) overlapped area, the display device 1000 of the present invention can also be improved (refer to Figure 1 ) display quality.

[0131] Fig.12a A step of forming the conductive pattern MF is shown. Figure 12b and Fig.12c The steps of forming the conductive pattern MF are shown. Fig.12a Another embodiment of . That is, Figure 12b and Fig.12c Can be with Fig.12a The steps described in .

[0132] Reference Figures 12a to 12c According to the present embodiment, the display panel manufacturing method may include: configuring a base layer 110 and a circuit film COF on a workbench ST, configuring a transfer substrate TF on the base layer 110; and forming a conductive pattern MF.

[0133] The base layer 110 and the circuit film COF may be configured in such a manner that a plurality of pads PD and the circuit film wiring CFL of the base layer 110 overlap. That is, the base layer 110 and the circuit film COF may be configured in such a manner that a plurality of pads PD, a portion of the circuit film COF, and the circuit film wiring CFL overlap within the opening OP of the base layer 110. The transfer substrate TF configured on the base layer 110 may include a donor film DF and a transparent substrate TS. The transparent substrate TS may be configured on the donor film DF. The transparent substrate TS may support the donor film DF.

[0134] First, refer to Fig.12a The first laser LS1 may be irradiated to the transfer substrate TF to form a conductive pattern MF on the plurality of pads PD and the circuit film wiring CFL. The step of forming the conductive pattern MF may include irradiating the first laser LS1, changing the direction of the first laser LS1, and transferring a portion of the donor film DF.

[0135] The laser device LSD may irradiate the first laser LS1 in a direction parallel to the first direction DR1. For example, the laser device LSD may irradiate the first laser LS1 in a direction opposite to the first direction DR1.

[0136] Afterwards, the direction of the first laser LS1 can be changed to a third direction DR3 by a lens LL disposed on the transfer substrate TF. The third direction DR3 can be a direction intersecting the first direction DR1. For example, the third direction DR3 can be a direction toward the transparent substrate TS. In this specification, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be changed to another direction.

[0137] Afterwards, the first laser LS1 irradiated toward the transparent substrate TS can transmit the transparent substrate TS and transfer a portion of the donor film DF. The transferred portion of the donor film DF can be arranged on the plurality of pads PD and the circuit film wiring CFL to form a conductive pattern MF. The conductive pattern MF can combine the plurality of pads PD and the circuit film wiring CFL.

[0138] The step of forming the conductive pattern MF may further include the step of moving the laser device LSD and the lens LL in the first direction DR1 or the second direction DR2. The laser device LSD and the lens LL may be moved in the first direction DR1 or the second direction DR2 to change the position of the first laser LS1 irradiated to the transfer substrate TF. For example, the position of the first laser LS1 may be moved to transfer a portion of the donor film DF corresponding to one pad PD and one circuit film wiring CFL, and the first conductive pattern MF may be formed from the transferred portion of the donor film DF. Thereafter, the position of the first laser LS1 may be moved in a direction parallel to the first direction DR1 to transfer a portion of the donor film DF corresponding to the second pad PD and the second circuit film wiring CFL, and the second conductive pattern MF may be formed from the transferred portion of the donor film DF.

[0139] However, the process of changing the position of the first laser LS1 is not limited to the above method. For example, the step of forming the conductive pattern MF may further include the step of moving the work stage ST in the first direction DR1 or the second direction DR2. Alternatively, the work stage ST may be moved in the first direction DR1 or the second direction DR2 to change the position of the first laser LS1 irradiated to the transfer substrate TF.

[0140] Reference Figure 12b , the first laser LS1 may be irradiated to the transfer substrate TF to form a conductive pattern MF on the plurality of pads PD and the circuit film wiring CFL. The step of forming the conductive pattern MF may include the step of irradiating the first laser LS1, the step of changing the direction of the first laser LS1, and the step of transferring a portion of the donor film DF by continuously changing the direction of the first laser LS1 by the scanner SCR.

[0141] The laser device LSD may irradiate the first laser LS1 in a direction parallel to the first direction DR1. For example, the laser device LSD may irradiate the first laser LS1 in a direction opposite to the first direction DR1.

[0142] Afterwards, the direction of the first laser LS1 may be changed to a third direction DR3 by the scanner SCR disposed on the transfer substrate TF. The third direction DR3 may be a direction crossing the first direction DR1. For example, the third direction DR3 may be a direction toward the transparent substrate TS.

[0143] After that, the scanner SCR may continuously change the direction of the first laser LS1. For example, the scanner SCR may move the first laser LS1 in the first direction DR1 or the second direction DR2. Fig.12a ) or workbench ST (refer to Fig.12a ) is moved, the direction of the first laser LS1 can be moved by the scanner SCR, thereby reducing the time for transferring the donor film DF.

[0144] The first laser LS1 may be irradiated toward the transparent substrate TS while continuously changing its direction. The first laser LS1 may transmit through the transparent substrate TS and transfer a portion of the donor film DF. The transferred portion of the donor film DF may be arranged on a plurality of pads PD and the circuit film wiring CFL to form a conductive pattern MF. The conductive pattern MF may combine a plurality of pads PD and the circuit film wiring CFL.

[0145] Reference Fig.12c , a first laser (or line laser) LS1a may be irradiated onto the transfer substrate TF to form a conductive pattern MF on a plurality of pads PD and the circuit film wiring CFL. The step of forming the conductive pattern MF may include a step of disposing a mask MK on the transfer substrate TF, a step of irradiating the first laser LS1a along the mask MK by the laser device LSD, and a step of transferring a portion of the donor film DF by the first laser LS1a that transmits the mask MK.

[0146] A mask MK may be disposed on the transfer substrate TF. The mask MK may include a plurality of mask openings OP_M. Fig.12c Nine mask openings OP_M are exemplarily shown, but are not limited thereto. For example, the number of mask openings OP_M may correspond to the number of conductive patterns MF to be formed.

[0147] The laser device LSD may irradiate the first laser LS1a in a direction parallel to the third direction DR3. The third direction DR3 may be a direction toward the transparent substrate TS. For example, the laser device LSD may irradiate the first laser LS1a toward the third direction DR3 while moving in a direction parallel to the first direction DR1. The first laser LS1a may be a line laser.

[0148] The first laser LS1a transmitting the mask MK can transmit the transparent substrate TS of the transfer substrate TF. A portion of the donor film DF can be transferred by the first laser LS1a transmitting the transparent substrate TS. The transferred portion of the donor film DF can be arranged on a plurality of pads PD and the circuit film wiring CFL to form a conductive pattern MF. The conductive pattern MF can combine a plurality of pads PD and the circuit film wiring CFL. According to the present invention, as the donor film DF is transferred using the line laser LS1a and the mask MK, the time for transferring the donor film DF to form the conductive pattern MF can be reduced.

[0149] The conductive pattern MF of the present invention may be formed by transferring the donor film DF. In this case, the spacing between the conductive patterns MF may be formed to be short compared to the case where the conductive material is coated with ink. In addition, the conductive pattern MF formed by transferring the donor film DF may be in the form of a thin film. In this case, compared to the case where the conductive material is coated in a hemispherical form, damage to the base layer 110 caused by a subsequent laser process may be reduced or removed.

[0150] After forming the conductive pattern MF, refer to Fig.13 , the display panel manufacturing method according to an embodiment of the present invention may further include the step of irradiating a second laser LS2 to an area where the circuit film wiring CFL and the conductive pattern MF overlap. The second laser LS2 may be an infrared laser. The second laser LS2 may pass through the conductive pattern MF and combine the circuit film wiring CFL and the conductive pattern MF. For example, the second laser LS2 may combine the boundary of the circuit film wiring CFL and the conductive pattern MF. With the additional irradiation of the second laser LS2, the bonding force between the circuit film wiring CFL and the conductive pattern MF may be improved, and thus the bonding force between the circuit film wiring CFL and the pad PD may be improved.

[0151] The above description is made with reference to the preferred embodiments of the present invention, but it is understood by those skilled in the art or those with common knowledge in the art that various modifications and changes can be made to the present invention within the scope of the concept and technical field of the present invention as described in the attached claims. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A method for manufacturing a display panel, wherein: include: The step of preparing a base layer including a plurality of pads; A step of etching a portion of the base layer to form an opening to expose the plurality of pads; a step of preparing a circuit film including a preliminary circuit film wiring therein; irradiating the circuit film with laser light to form a circuit film wiring from the preliminary circuit film wiring; The steps of arranging the base layer and the circuit film on a workbench in such a manner that the plurality of pads and the circuit film wiring overlap each other and arranging a transfer substrate on the base layer; as well as The step of irradiating the transfer substrate with a first laser to form a conductive pattern on the plurality of pads and the circuit film wiring.

2. The method for manufacturing a display panel according to claim 1, wherein: The step of forming the circuit film wiring includes the step of etching a portion of the circuit film to expose a portion of the preliminary circuit film wiring.

3. The method for manufacturing a display panel according to claim 1, wherein: The transfer substrate includes a donor film and a transparent substrate disposed on the donor film.

4. The method for manufacturing a display panel according to claim 3, wherein: The step of forming the conductive pattern comprises: A step of irradiating the first laser light in a first direction by a laser device; The step of changing the direction of the first laser light to a direction toward the transparent substrate by a lens disposed on the transfer substrate; and The first laser irradiated toward the transparent substrate transfers a portion of the donor film.

5. The method for manufacturing a display panel according to claim 4, wherein: The step of forming the conductive pattern further includes: The step of moving the laser device and the lens in the first direction or a second direction intersecting the first direction.

6. The method for manufacturing a display panel according to claim 4, wherein: The step of forming the conductive pattern further comprises: The step of moving the workbench in the first direction or a second direction intersecting the first direction.

7. The method for manufacturing a display panel according to claim 3, wherein: The step of forming the conductive pattern comprises: A step of irradiating the first laser light in a first direction by a laser device; The step of changing the direction of the first laser to a direction toward the transparent substrate by a scanner disposed on the transfer substrate; and The scanner continuously changes the direction of the first laser to transfer a portion of the donor film.

8. The method for manufacturing a display panel according to claim 3, wherein: The step of forming the conductive pattern comprises: a step of disposing a mask on the transfer substrate; a step of irradiating the first laser light along the mask with a laser device; and a step of transferring a portion of the donor film by the first laser transmitted through the mask, The first laser is a line laser.

9. The method for manufacturing a display panel according to claim 3, wherein: The display panel manufacturing method further includes: a step of irradiating a second laser beam onto an area where the circuit film wiring and the conductive pattern overlap, The second laser passes through the conductive pattern to combine the circuit film wiring and the conductive pattern.

10. The method for manufacturing a display panel according to claim 9, wherein: The second laser is an infrared laser.

11. The method for manufacturing a display panel according to claim 1, wherein: The base layer includes a first region and a second region, a plurality of pixels are arranged in the first region, and the opening overlaps with the first region of the base layer.

12. The method for manufacturing a display panel according to claim 1, wherein: The steps of configuring the base layer and the circuit film and configuring the transfer substrate on the base layer include: The step of arranging the base layer and the circuit film so that the plurality of pads and the circuit film wiring overlap in the opening of the base layer.

13. The method for manufacturing a display panel according to claim 1, wherein: The steps of configuring the base layer and the circuit film and configuring the transfer substrate on the base layer include: The step of arranging the base layer and the circuit film so that the plurality of pads, a portion of the circuit film, and the circuit film wiring overlap in the opening of the base layer.

14. A display panel, wherein: include: A base layer defining the first region and the second region; A plurality of pixels are arranged on the first region of the base layer; A plurality of pads are arranged between the upper surface and the lower surface of the base layer; A circuit film is arranged on the plurality of pads and the bottom surface of the base layer; A circuit film wiring is arranged on the plurality of pads, and a portion of the circuit film wiring extends from the circuit film; as well as A conductive pattern is arranged on the circuit film wiring and the plurality of pads, An opening is defined in the base layer in a thickness direction of the base layer, and the plurality of pads, the circuit film wiring, and the conductive pattern are arranged in the opening.

15. The display panel according to claim 14, wherein: A portion of the circuit film is disposed in the opening.

16. The display panel according to claim 14, wherein: The base layer comprises: A first sub-base layer, including the bottom surface of the base layer and defining the opening; a barrier layer, disposed on the first sub-base layer; and A second sub-base layer is disposed on the barrier layer and includes the upper surface of the base layer. The plurality of pads are disposed in the barrier layer and exposed through the opening of the first sub-base layer.

17. The display panel according to claim 14, wherein: On a plane, a width of the circuit film wiring is equal to or smaller than a width of each of the plurality of pads.

18. The display panel according to claim 14, wherein: On a plane, the width of the conductive pattern is equal to or smaller than the width of the circuit film wiring.

19. The display panel according to claim 14, wherein: The opening portion overlaps with the first region.

20. The display panel according to claim 14, wherein: The opening overlaps with the first region and the second region.

21. The display panel according to claim 14, wherein: The conductive pattern combines the circuit film wiring and the plurality of pads.

22. The display panel according to claim 14, wherein: The conductive pattern is in the form of a thin film.

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