Nonvolatile storage-SRAM data transfer unit, heterogeneous integrated storage system and chip system

Abstract

The invention provides a non-volatile memory-SRAM (Static Random Access Memory) data transfer unit, a heterogeneous integrated storage system and a chip system. The non-volatile memory-SRAM data transfer unit comprises a non-volatile memory-SRAM (Static Random Access Memory) data transfer unit, the M * N nonvolatile storage units are arranged in a matrix form, and the multiplexing unit is positioned between the M * N nonvolatile storage units arranged in the matrix form and the SRAM storage unit; the M * N non-volatile storage units are used for multiplexing the SRAM storage unit through the multiplexing unit, and the M * N non-volatile storage units are used for multiplexing the SRAM storage unit through the multiplexing unit; wherein M and N are positive integers.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a non-volatile storage-SRAM data transfer unit, a heterogeneous integrated storage system and a chip system. Background Art

[0002] Compared with traditional transistor-based chip designs, non-volatile memory chips have shown advantages. For example, MRAM (Magnetic Random Access Memory) using spin devices has significant advantages in the field of non-volatile storage. Its core component, the magnetic tunnel junction (MTJ), has a persistent magnetization state, which can maintain data even under power-off conditions, significantly reducing standby power consumption. At the same time, due to the rapid conversion of electron spin states, MRAM can achieve faster read and write speeds than traditional storage media.

[0003] Another major advantage of spin devices is the simple chip manufacturing process. By utilizing the top metal layer, the back-end process is simplified and is compatible with complementary metal oxide semiconductor (CMOS) technology. In addition, spin chips have good erasable and radiation resistance, which meets the storage requirements of embedded non-volatile computing platforms at advanced process nodes in the big data era.

[0004] In the traditional von Neumann architecture, data transmission between the processor and the memory constitutes a "storage wall", resulting in an obvious performance bottleneck. In-Memory Computing (IMC) effectively alleviates this problem by embedding the computing logic inside the memory, greatly shortening the data access delay. More importantly, the energy loss during data transmission in the traditional von Neumann architecture is considerable. The IMC strategy achieves a significant improvement in energy efficiency by reducing unnecessary data movement. In-Memory Computing of non-volatile memory combines the capabilities of data storage and data computing, and uses the high bandwidth of the memory itself to perform computing tasks. It is no longer limited by the transmission rate of the external data bus, thereby significantly enhancing the overall performance of the system. The tight integration of computing and storage not only saves chip area, but also reduces the overall cost and design complexity of the system.

[0005] Although non-volatile storage has excellent performance in storage density, non-volatility, low power consumption and durable erasure, it faces certain limitations in the field of in-memory computing. The main challenge stems from its inherent device characteristics, namely low tunneling magnetoresistance ratio (TMR) and small magnetoresistance difference, which limits it to binary storage and lacks the ability to store multi-value states, making it difficult to implement multi-bit computing tasks. If non-volatile storage is to be used for accumulation operations, complex sampling and sensing techniques are required to interpret the accumulated results, which increases the difficulty of implementation and energy consumption. In addition, the read and write speeds of non-volatile storage are relatively slow, and each read operation involves multiple steps, which cannot meet the requirements of in-memory computing architectures for high-speed data transmission.

[0006] In contrast, SRAM (Static Random-Access Memory) stores data through voltage states, has extremely fast read and write speeds, is highly compatible with digital computing logic, and is suitable for in-memory computing architectures to achieve high-speed data processing.

[0007] In view of this, the hybrid storage architecture of non-volatile storage and SRAM has become an innovative direction in the field of in-memory computing. In this architecture, non-volatile storage takes advantage of its non-volatility and high-density storage to play the role of weight storage, which is particularly suitable for storing the weight parameters of neural networks, while SRAM takes on the tasks of data caching and calculation due to its high performance and easy cooperation with digital computing units. This hybrid architecture can not only achieve low standby power consumption, but also ensure high computing accuracy.

[0008] In summary, the in-memory computing architecture of non-volatile storage-SRAM hybrid storage combines the advantages of two storage technologies and can solve the problem of low energy efficiency caused by frequent data movement in traditional computing architecture. Summary of the invention

[0009] In view of this, the present application provides a data transfer circuit and an SRAM storage circuit for realizing a non-volatile storage-SRAM hybrid storage architecture.

[0010] In a first aspect, an embodiment of the present application provides a non-volatile storage-SRAM data transfer unit, the non-volatile storage-SRAM data transfer unit comprising: M*N non-volatile storage cells arranged in a matrix form, an SRAM storage cell, and a multiplexing unit between the M*N non-volatile storage cells arranged in a matrix form and the SRAM storage cell; the M*N non-volatile storage cells multiplex the SRAM storage cell through the multiplexing unit; wherein M and N are both positive integers.

[0011] Optionally, the SRAM storage unit is implemented using a MOS tube, and the first metal layer and the second metal layer of the MOS tube are used to implement the SRAM storage unit; the metal layer above the second metal layer is used to arrange a data bus.

[0012] Optionally, a protection ring is arranged around the non-volatile storage unit, the SRAM storage unit and the multiplexing unit, and the protection ring is connected to a high-level power network of the data transfer unit.

[0013] Optionally, the nonvolatile storage unit includes a magnetic tunnel junction and a MOS transistor, and the magnetic tunnel junction is located between upper metal layers of the MOS transistor.

[0014] Optionally, the magnetic tunnel junction is located between high-level metal layers of the MOS tube.

[0015] Optionally, the wiring space between the word lines, bit lines and source lines of the non-volatile memory cell is used to arrange customized bits.

[0016] Optionally, the multiplexing unit is used to select a column of the non-volatile storage cells to be connected to the SRAM storage cells.

[0017] Optionally, the non-volatile storage-SRAM data transfer unit is used in a computing or storage circuit.

[0018] In a second aspect, an embodiment of the present application provides a heterogeneous integrated storage system, wherein the heterogeneous integrated storage system is constructed by splicing the non-volatile storage-SRAM data transfer unit described in the first aspect as a basic unit.

[0019] In a third aspect, an embodiment of the present application provides a chip system, comprising the heterogeneous integrated storage system as described in the second aspect, wherein the chip system is used to complete the data transfer or in-memory calculation included in the chip system according to the heterogeneous integrated storage system, and the heterogeneous integrated storage system is arranged unilaterally or bilaterally in the chip system.

[0020] The non-volatile storage-SRAM data transfer unit provided in the embodiment of the present application completes a more complex layout design by making full use of the existing wiring space and the available metal layers. The SRAM part only uses two layers of metal, M1 and M2, and can continue to use the high-level metal above it for data bus deployment, further improving the chip area utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the architecture of a non-volatile storage-SRAM heterogeneous integrated system provided in an embodiment of the present application;

[0022] Figure 2 It is a schematic diagram of the structure of a non-volatile storage-SRAM heterogeneous integrated circuit provided in an embodiment of the present application;

[0023] Figure 3A is a top view schematic diagram of the physical structure of a non-volatile storage array provided in an embodiment of the present application;

[0024] Figure 3B is a side view schematic diagram of the physical structure of a non-volatile storage array provided in an embodiment of the present application;

[0025] Figure 4 It is a top view schematic diagram of the structure of a non-volatile storage-SRAM data transfer unit provided in an embodiment of the present application;

[0026] Figure 5A is a schematic diagram of a chip architecture provided in an embodiment of the present application;

[0027] Figure 5B It is a schematic diagram of another chip architecture provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The development of computing in memory (CIM) has not only overturned the traditional computing architecture, but also promoted the progress of processors, computing architecture and computing models. CIM solves the power consumption and speed problems caused by the separation of storage and computing in the von Neumann architecture, and realizes the design concept of integrated storage and computing. By shortening the distance between the computing unit and the memory, the CIM method enables the memory to have computing power, thus solving the problem of low energy efficiency caused by frequent data movement in the traditional computing architecture.

[0029] Therefore, exploring non-volatile storage, such as MRAM (Magnetic Random Access Memory) or RRAM (Resistive Random-Access Memory) and SRAM (Static Random-Access Memory) hybrid storage in-memory computing has become a feasible computing architecture. This hybrid storage aims to take advantage of the non-volatility and high-density storage of non-volatile storage to achieve effective storage of weights; at the same time, it uses the high performance of SRAM and its natural compatibility with digital computing units to complete data caching and computing processes. Through this combination, a method for implementing in-memory computing with low standby power consumption and high computing accuracy can be realized to provide a new computing system architecture.

[0030] The present application embodiment provides a heterogeneous integrated storage structure, see Figure 1 . Figure 1Schematic diagram of the architecture of the non-volatile storage-SRAM heterogeneous integrated system provided in the embodiment of the present application. Taking MRAM as an example, Figure 1 The MRAM-SRAM heterogeneous integrated system shown includes: SRAM array (SRAM ARRAY) 101, multiplexing unit (MUX) 102, MRAM array (MRAM ARRAY) 103. It should be noted that the non-volatile storage in the embodiment of the present application is described by taking MRAM as an example, but no specific limitation is made to the non-volatile storage.

[0031] The MRAM array 103 is used to store weight data, while the SRAM array 101 is used as an efficient cache mechanism to extract the weight data and convert it into a voltage signal for the digital operation circuit to perform operations. Figure 1 As shown, the MRAM-SRAM heterogeneous integrated system architecture provided in the embodiment of the present application may also include: Input (input) and Output (output) modules or Computing Module (computing module) modules. Figure 1 The embodiment shown includes Input and Output modules. Figure 1 The architecture shown can be used for storage circuits if Figure 1 The embodiment shown includes a computing module. Figure 1 The architecture shown can be used as a memory-computation circuit. Figure 1 The architecture shown can also be used as a storage plus computing circuit. Figure 1 The use of the architecture shown is not specifically limited. Considering that the size of the sub-array is kept within a small range, the voltage attenuation effect caused by it is significantly reduced, that is, the digital signal from the SRAM can be directly captured by the register group without going through a redundant readout circuit link, thereby simplifying the circuit design and reducing energy consumption and delay.

[0032] The design of the calculation circuit adopts mature digital logic technology. Its layout is close to SRAM, which can directly process the operation between input data and weight data, and realize real-time data processing. This calculation method close to the source of data not only reduces the data transmission distance and improves the calculation efficiency, but also reduces the attenuation of signals in long-distance transmission, ensuring the accuracy and stability of the calculation results.

[0033] In summary, by closely integrating computing modules with storage resources, especially the heterogeneous integration design of SRAM and MRAM, fast data access and efficient processing are achieved, which is conducive to building a high-performance, low-power computing platform suitable for the big data era.

[0034] In the field of storage technology, the design of traditional sense amplifiers, whether current mode or voltage mode, faces significant challenges. Such amplifiers are usually complex in structure, occupy a large chip area, and are susceptible to manufacturing process deviations, especially when the threshold voltage of the MOS tubes in the differential pair is mismatched, which may lead to unstable performance. In addition, the operation of the sense amplifier usually involves multiple stages, which prolongs the reading time and poses challenges to real-time performance and efficiency.

[0035] To address the above problems, the MRAM-SRAM hybrid circuit with a cross-coupling structure provides a streamlined and efficient alternative, especially for small storage arrays, see Figure 2 . Figure 2 Schematic diagram of the structure of the non-volatile memory-SRAM heterogeneous integrated circuit provided in the embodiment of the present application. Figure 2 As shown in Figure 1, this design can directly realize data migration without the need for additional complex amplifier structures. By cascading or splicing multiple such small arrays, large-scale storage arrays can be easily constructed while maintaining low power consumption and high read and write speeds.

[0036] The following pair Figure 2 The circuit structure shown in the figure is described in detail. Figure 2 The circuit structure shown includes a cross-coupled data transfer circuit and an SRAM data transfer array, wherein the cross-coupled data transfer circuit includes a cross-coupled transistor and a 1T-1M storage array. The cross-coupled transistor includes a first transistor M1, a second transistor M2, and two control transistors. The gate of the first transistor M1 is connected to the first bit line (BL[X]) of the storage circuit; the gate of the second transistor M2 is connected to the second bit line (BL[B]) of the storage circuit; the first electrode of the first transistor M1 is connected to the first electrode of a control transistor; the first electrode of the second transistor M2 is connected to the first electrode of another control transistor; the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are respectively connected to the ground; forming a cross-coupled transistor structure. The second electrodes of the two control transistors are respectively connected to the two source lines SL[X] and SLB of the storage circuit.

[0037] It should be noted that the first electrode of the transistor in the embodiment of the present application is one of the source (S) and the drain (D), and the second electrode of the transistor is the other corresponding electrode.

[0038] The following is a detailed description of the 1T (transistor) -1M (magnetic tunnel junction) memory array. The embodiment of the present application uses 1T (transistor) -1M (magnetic tunnel junction) as an example for schematic description, but the embodiment of the present application does not specifically limit the structure of the MRAM memory array. For example, the MRAM memory array can be 2T-2M (two transistors - two magnetic tunnel junctions). In the 1T-1M structure, one end of the magnetic tunnel junction MTJ is connected to the first pole of the transistor, the gate (G) of the transistor is connected to the word line (exemplarily, WL[0] or WL[1]), the other end of the magnetic tunnel junction MTJ is connected to the bit line (exemplarily, BL[X]), and the second pole of the transistor is connected to the source line (exemplarily, SL[X]).

[0039] Each MTJ can store a data bit (0 or 1), depending on its magnetization direction. When data needs to be read or written, the corresponding transistor is selected by controlling the voltage of the word line (WL). When the transistor is turned on, a path is formed between the bit line (BL) and the MTJ, allowing current to pass through the MTJ. In the read operation, the resistance state of the MTJ is detected by measuring the current or voltage change on the bit line (BL), thereby determining the stored data bit. In the write operation, the magnetization direction of the MTJ is changed by applying a specific current or voltage pulse to the bit line (BL) and / or word line (WL), thereby achieving data writing.

[0040] Figure 2 In the illustrated embodiment, during a read operation, the bit line (BL) and its complementary line (BLB) are first precharged, and then the enable signal (EN) is turned on, and the word line (WL) and the control signal (Ctr) of the magnetoresistive random access memory are activated at the same time, prompting the storage unit to start the discharge process. During this stage, the voltage on the bit line and its complementary line will gradually tend to a stable equilibrium state, reflecting the data information in the storage unit. Next, the word line (WL) of the SRAM is activated, and the enable signal (EN) is set to a high level, triggering the latching action of the SRAM storage unit, locking the read data state, and completing the reading and temporary storage of the data. It is worth noting that the entire reading process is designed to be extremely compact and can be completed in just 3 nanoseconds (ns), which makes it highly applicable and efficient in a variety of application scenarios of storage acceleration and in-memory computing acceleration cards.

[0041] The SRAM data transfer array is introduced as follows. Figure 2As shown, the 8TSRAM structure provided in the embodiment of the present application adds additional MOS transistors to the pull-up network and the pull-down network on the basis of the traditional 6-tube SRAM. This enables the strong feedback connection of the inverters connected end to end to be cut off during data transfer, thereby improving the stability and accuracy of data transfer. The read and write operations of the 8T SRAM are similar to those of the traditional 6-tube SRAM, but due to the addition of additional transistors, the read and write speeds may be slightly different. When reading data, the data is read from the storage cell (MRAM) through the access transistor; when writing data, the data is written to the storage cell (MRAM) through the access transistor. In addition, a pair of cross-coupled transistors are added to the MRAM storage array to assist in extracting data from the MRAM to the SRAM. When data needs to be extracted from the MRAM to the SRAM, the cross-coupled transistors are activated. By controlling the gate voltage of the cross-coupled transistor, the size of the channel current can be adjusted to achieve data amplification and transmission. Data is transmitted from the storage cell of the MRAM to the input port of the SRAM through the cross-coupled transistor, and then written to the storage cell of the SRAM.

[0042] The design of the non-volatile memory-SRAM hybrid circuit simplifies the reading process of the storage unit and reduces the area overhead, thereby improving the overall storage density. At the same time, since the use of the traditional sensitive amplifier is omitted, the stability and reliability of the circuit are improved, and the performance is more robust in the face of process deviations. The storage architecture has a faster reading speed, a smaller chip footprint, and a better energy efficiency ratio.

[0043] The following is a detailed description of the non-volatile storage array in the embodiment of the present application, see Figure 3A-3B . Figure 3A It is a top view schematic diagram of the physical structure of the non-volatile storage array provided in an embodiment of the present application.

[0044] Figure 3B FIG. 1 is a side view schematic diagram of the physical structure of the non-volatile storage array provided in the embodiment of the present application. Figure 3A and 3B As shown, the physical structure of the non-volatile memory array provided by the embodiment of the present application uses the compatibility of STT-MTJ (spin transfer torque magnetic tunnel junction) and CMOS process. In order to achieve heterogeneous integration, the entire manufacturing process is divided into two stages: the front-end process focuses on the construction of the underlying CMOS circuit, while the back-end process is dedicated to the processing of STT-MTJ to ensure seamless connection between the two. Figure 3BAs shown, the bottom CMOS circuit includes a silicon substrate, a gate, a source and a drain formed on the silicon substrate. The upper layer of the MOS tube includes metal layers (e.g., M1, M2, M3, M4, M5, M6) and through holes between the metal layers (e.g., V1, V2, V3, V4, V5, V6).

[0045] It should be noted that M1, M2, M3, M4, M5 and M6 are the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer and the sixth metal layer respectively; CT is a through hole between the first metal layer and the gate, source and drain of the CMOS. Figure 3B The MTJ is shown to be disposed between the sixth metal layer and the seventh metal layer. Figure 3B As shown, the source line (SL) is arranged on the second metal layer, the word line (WL) is arranged on the third metal layer, and the bit line (BL) is arranged on the seventh metal layer. Here, the bit line of T2-M2 is used as an example for schematic illustration but no specific limitation is made. Therefore, there is still a rich wiring area between the word line (WL), the bit line (BL) and the source line (SL), which can be used to provide a customized bit design for the STT-MRAM.

[0046] It should be noted that the line (WL), the bit line (BL) and the source line (SL) may also be arranged on other metal layers, and the embodiment of the present application does not impose any specific limitation on this.

[0047] Figure 3A It is a top view schematic diagram of the physical structure of a non-volatile memory array. Figure 3A AA is the active area of ​​the MOS tube, and Via is the metal through hole, that is, Figure 3B V1, V2, V3, V4, V5, V6 and CT.

[0048] Given the high current requirements of STT-MTJ write operations, access transistors are usually selected with a larger width-to-length ratio to ensure sufficient current supply. Therefore, the actual area of ​​the non-volatile storage bit is determined by the physical size of the MOS tube and the necessary wiring channels.

[0049] In the design of ultra-large-scale integrated circuits, MTJ components are often placed in higher metal layers, for example, between the sixth metal layer (M6) and the seventh metal layer (M7), making full use of the wiring capabilities of the high-level metal layers. Of course, the MTJ can also be set between other high-level metal layers, and the embodiments of the present application do not impose specific restrictions on this. This layout not only optimizes the transmission path of the signal, but also provides space for customized bit design of STT-MRAM. In the non-volatile storage memory architecture, the rich wiring area between the word line (WL), bit line (BL) and source line (SL) creates conditions for the deep integration of high-performance computing and storage.

[0050] It should be noted that the WL, SL and BL in the embodiments of the present application are not limited to specific metal layers, but can be flexibly positioned at different levels of the circuit according to design requirements.

[0051] The following is a detailed description of the non-volatile storage-SRAM data transfer unit, see Figure 4 . Figure 4 Schematic diagram of the structure of the non-volatile storage-SRAM data transfer unit provided in the embodiment of the present application. Figure 4 As shown, the non-volatile storage-SRAM data transfer unit includes: M*N non-volatile storage cells (MRAM ARRAY) arranged in a matrix form, a multiplexing unit (MUX) and an SRAM storage cell (SRAM ARRAY). Among them, MRAM is implemented by the embodiment shown in Figure 3, which will not be repeated here. The SRAM storage cell is implemented by a MOS tube, and the SRAM storage cell only occupies the lowest two layers of metal M1 and M2, while the higher-level metal layers can be used for the expansion deployment of the data bus. Through the selection function of the MUX (multiplexing unit), the MRAM storage cell can be connected to the SRAM storage cell to form a bridge for data flow.

[0052] Given the relatively large size of the SRAM memory cell, it can share space with multiple columns of non-volatile memory, resulting in efficient resource utilization. The number of SRAM blocks directly depends on the bit width of a single data read, ensuring that data throughput matches system requirements.

[0053] In terms of physical structure implementation, the non-volatile memory array can be seamlessly connected to the SRAM unit through the MUX selection function, forming a bridge for data flow. Thanks to the ample wiring space and available metal layers, complex wiring design can be implemented, which makes the density of the overall physical implementation architecture limited by the spacing between the MTJ and the underlying metal layer and the wiring spacing between each metal layer.

[0054] It should be noted that the SRAM part only occupies the lowest two metal layers M1 and M2, while higher-level metal layers are available for the expansion and deployment of the data bus, which effectively improves the overall utilization of the chip, further improves the chip area utilization, and achieves space optimization.

[0055] Figure 4 The sharing mode of M*N non-volatile memory array and single SRAM cell shown in the figure represents the basic unit for building heterogeneous integrated storage and computing arrays. By reusing this basic unit, a larger storage / computing fusion architecture can be built. In order to avoid latch-up effect, guardrings must be set around the non-volatile memory array, MUX and SRAM array, and the guardrings are connected to the high-level power network to ensure the stability and reliability of the circuit.

[0056] In actual deployment, specific process constraints must also be considered, such as adjusting the trace width to prevent long-term reliability issues caused by electromigration and metal stress, such as metal fatigue or breakdown, which are key points affecting the life of the circuit. Through fine engineering control, the performance and stability of the architecture can be guaranteed over a long period of time.

[0057] It should be noted that Figure 4 The minimum reusable data transfer unit shown is composed of an M*N non-volatile memory array and one SRAM, where M and N are both positive integers. The minimum reusable data transfer unit is spliced ​​to produce the entire heterogeneous integrated storage system.

[0058] It should also be noted that the upper metal layer of the SRAM can be used to arrange the data bus, but the embodiments of the present application do not impose specific restrictions on this. Even if the upper metal layer of the SRAM is not used to arrange the data bus deployment, it still needs to be protected.

[0059] In some embodiments, the heterogeneous integrated storage system provided in the embodiments of the present application can be used in a chip system, and the chip system is used to complete the data transfer or in-memory computing included in the chip system according to the above heterogeneous integrated storage system. Figure 5A-Figure 5B . Figure 5A is a schematic diagram of a chip architecture provided in an embodiment of the present application, such as Figure 5A As shown, the heterogeneous integrated storage system (bank) is arranged unilaterally in the chip system, that is, data, signal or resource transmission is mainly carried out in one direction, that is, from one bank to another bank, rather than complex interaction in two directions. Figure 5B is a schematic diagram of another chip architecture provided in an embodiment of the present application, such as Figure 5BAs shown, the heterogeneous integrated storage system (bank) is arranged bilaterally in the chip system, that is, the bank is distributed on both sides of the chip system, and data, signals or resources are more complexly interacted and transmitted in two directions.

[0060] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0061] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0062] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0063] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0064] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0065] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0066] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0067] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0068] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A non-volatile storage-SRAM data transfer unit, characterized in that: The nonvolatile storage-SRAM data transfer unit comprises: M*N nonvolatile storage cells arranged in a matrix, an SRAM storage cell, and a multiplexing unit between the M*N nonvolatile storage cells arranged in a matrix and the SRAM storage cell; The M*N non-volatile storage units multiplex the SRAM storage unit through the multiplexing unit; Wherein, M and N are both positive integers.

2. The nonvolatile storage-SRAM data transfer unit according to claim 1, characterized in that: The SRAM storage unit is implemented by using a MOS tube, and the first metal layer and the second metal layer of the MOS tube are used to implement the SRAM storage unit; The metal layer above the second metal layer is used for arranging a data bus.

3. The non-volatile storage-SRAM data transfer unit according to claim 1, characterized in that: A protection ring is arranged around the nonvolatile storage unit, the SRAM storage unit and the multiplexing unit, and the protection ring is connected to the high-level power supply network of the data transfer unit.

4. The nonvolatile storage-SRAM data transfer unit according to claim 1, characterized in that: The nonvolatile storage unit comprises a magnetic tunnel junction and a MOS tube, wherein the magnetic tunnel junction is located between upper metal layers of the MOS tube.

5. The non-volatile storage-SRAM data transfer unit according to claim 4, characterized in that: The magnetic tunnel junction is located between high-level metal layers of the MOS tube.

6. The nonvolatile storage-SRAM data transfer unit according to claim 4, characterized in that: The wiring spaces between the word lines, bit lines and source lines of the nonvolatile memory cell are used to arrange customized bits.

7. The nonvolatile storage-SRAM data transfer unit according to claim 1, characterized in that: The multiplexing unit is used to select a certain column of the non-volatile storage cells to be connected to the SRAM storage cells.

8. The nonvolatile storage-SRAM data transfer unit according to claim 1, characterized in that: The nonvolatile storage-SRAM data transfer unit is used in a circuit for storage or calculation or storage plus calculation.

9. A heterogeneous integrated storage system, characterized in that: The heterogeneous integrated storage system is constructed by splicing the non-volatile storage-SRAM data transfer unit described in any one of claims 1 to 8 as a basic unit.

10. A chip system, characterized in that: It includes the heterogeneous integrated storage system as described in claim 9, wherein the chip system is used to complete the data transfer or in-memory calculation included in the chip system according to the heterogeneous integrated storage system, and the heterogeneous integrated storage system is arranged unilaterally or bilaterally in the chip system.

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