High-speed VCSEL chip and manufacturing method thereof

Abstract

The invention provides a high-speed VCSEL chip and a manufacturing method, and belongs to the technical field of semiconductors, the high-speed VCSEL chip comprises a GaAs substrate, and the GaAs substrate is sequentially provided with an n-DBR, a quantum well active region, a p-DBR, a p-In < 0.49 > Ga < 0.51 > P inner cavity contact layer and a u-DBR; according to the invention, the number of pairs of series connection of the p-DBR is reduced, and the series resistance of the chip is reduced, so that the resistance of the chip is still kept at a reasonable level when the chip with a small oxidation aperture is manufactured, and the reliability and the high-temperature performance of the chip are better; the band gap width of the p-In0. 49Ga0. 51P inner cavity contact layer is 1.88 eV which is much larger than 1.42 V of GaAs, and the negative effect of light absorption in the 850 nm wave band is removed. A u-DBR table top is reserved at a light outlet, so that a large threshold gain difference exists between a fundamental mode and a high-order mode. In addition, the thick p-In0. 49Ga0. 51P inner cavity contact layer still has certain light field intensity, so that the loss of a high-order mode is further increased, the chip can stably work in a fundamental mode, and the modulation bandwidth is greatly increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-speed VCSEL chip and a manufacturing method thereof. Background Art

[0002] Vertical cavity surface emitting laser (VCSEL) has many advantages such as low threshold, high speed, small wavelength temperature drift coefficient, high coupling efficiency and low production cost. It is widely used in optical communication, three-dimensional sensing and lidar. With the rapid development of data centers and AI artificial intelligence, the terminal's demand for higher bandwidth of communication chips is becoming more and more urgent. As an important part of the industry, the current mainstream 25G and 50G VCSELs have gradually failed to meet terminal needs, and the development of 100G and 200G VCSELs is imminent. VCSEL chips are generally multi-transverse modes, and stable single-mode devices are difficult to achieve. However, single-mode stable operation is very helpful for improving the bandwidth of the device. In addition, while increasing the bandwidth of VCSEL, it is inevitable to reduce the oxidation aperture of VCSEL to increase its relaxation oscillation frequency, which leads to an increase in the series resistance of the device. This will bring a series of negative effects, such as:

[0003] 1. The CR cutoff frequency of the device decreases, limiting the overall bandwidth of the device.

[0004] 2. The heating of the device becomes more serious, and the power and bandwidth are more likely to saturate and decay at high temperatures.

[0005] 3. When the device is operating normally, the junction temperature becomes higher and the reliability of the device decreases. Summary of the invention

[0006] The present invention aims to solve the above technical problems and provides a high-speed VCSEL chip and a manufacturing method thereof.

[0007] In order to solve the above technical problems, the technical solution provided by the present invention is:

[0008] A high-speed VCSEL chip comprises a GaAs substrate, on which an n-DBR, a quantum well active region, a p-DBR, a p-In 0.49 Ga 0.51 P cavity contact layer and u-DBR;

[0009] Removal of u-DBR and p-In by etching 0.49 Ga 0.51 The P cavity contact layer retains the u-DBR in the light outlet area during the etching process to form a circular table. 0.49 Ga 0.51 Metal is deposited on the P cavity contact layer to form a p-type contact electrode, and a circular mesa structured optical port region u-DBR is retained during the etching process;

[0010] Oxidized mesa etching, from p-In 0.49 Ga 0.51 The P cavity contact layer to the n-DBR is wet oxidized to form current limiting oxide holes;

[0011] The n-electrode region is defined by photolithography, and the GaAs substrate is deeply etched to prepare the n-region metal contact electrode on the GaAs substrate.

[0012] Preferably, the u-DBR retained in the light outlet region has a mesa diameter of 3-5 μm.

[0013] Preferably, the distance between the terrace of the u-DBR and the inner diameter of the p-type contact electrode is 2-4 μm.

[0014] Preferably, the p-In 0.49 Ga 0.51 The overall optical thickness of the P cavity contact layer is 2-5λ.

[0015] Preferably, in p-In 0.49 Ga 0.51 The metal deposited on the P cavity contact layer to form the p-type contact electrode is TiPtAu, and its typical thickness is 30nm, 50nm, and 200nm respectively.

[0016] Preferably, the p-In is removed by etching 0.49 Ga 0.51 The thickness of the P cavity contact layer is less than half of the thickness of this layer.

[0017] A method for manufacturing a high-speed VCSEL chip comprises the following steps:

[0018] Step 1: On the GaAs substrate, epitaxially grow n-DBR, quantum well active region, oxide layer, p-DBR, p-In 0.49 Ga 0.51 P cavity contact layer and u-DBR;

[0019] Step 2: Etch and remove u-DBR and p-In through photoresist mask 0.49 Ga 0.51 P cavity contact layer, the light-emitting hole area retains part of the u-DBR table for mode control function;

[0020] Step 3: Using electron beam evaporation on p-In 0.49 Ga 0.51 A p-type contact electrode is prepared on the P inner cavity contact layer;

[0021] Step 4: Use PECVD to grow a thickness of SiNx;

[0022] Step 5: using photoresist as a mask, etching out the oxidation mesa and then performing wet oxidation to form oxidation holes;

[0023] Step 6: After oxidation is completed, the growth thickness is The SiNx passivation layer is processed by BCB process and PECVD process photolithography and etching process;

[0024] Step 7: Photolithography and deep etching of the front N-electrode region, the etching depth exceeds the n-DBR and reaches the GaAs substrate, and the n-region metal contact electrode is prepared on the GaAs substrate;

[0025] Step 8: Thinning and preparation of back metal;

[0026] Step 9: After laser cutting, a single or array VCSEL die is obtained.

[0027] Preferably, the thickness after thinning in step 8 is typically 150um or 200um.

[0028] After adopting the above structure and method, the present invention has the following advantages:

[0029] The present invention reduces the number of series pairs of p-DBRs and reduces the series resistance of the chip, so that when a chip with a small oxidation aperture is manufactured, its resistance is still maintained at a reasonable level, and the chip reliability and high temperature performance are better; 0.49 Ga 0.51 The band gap width of the P cavity contact layer is 1.88eV, which is much larger than the 1.42V of GaAs, eliminating the negative effect of light absorption in the 850nm band; the u-DBR table retained at the light outlet makes the threshold gain difference between the fundamental mode and the high-order mode. In addition, the thicker p-In 0.49 Ga 0.51 There is still a certain light field intensity at the P cavity contact layer, which further increases the loss of high-order modes, allowing the chip to work stably in the fundamental mode and greatly increasing the modulation bandwidth.

[0030] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a flow chart of the present invention;

[0033] Figure 2 It is a preparation schematic diagram of the present invention.

[0034] As shown in the figure: 21, n-DBR; 22, quantum well active region; 23, p-DBR; 24, p-In 0.49 Ga 0.51 P cavity contact layer; 25, u-DBR; 26, p-type contact electrode; 27, oxidation trench; 28, n-region metal contact electrode. DETAILED DESCRIPTION

[0035] Specific embodiments of the present invention will now be mentioned in detail. Although the present invention is described in conjunction with these specific embodiments, it should be appreciated that it is not intended to limit the present invention to these specific embodiments. On the contrary, these embodiments are intended to cover substitutions, changes or equivalent embodiments that may be included in the spirit and scope of the invention defined by the claims. In the following description, a large number of specific details are set forth in order to provide a comprehensive understanding of the present invention. The present invention can be implemented without some or all of these specific details. In other cases, in order not to make the present invention unnecessarily obscure, well-known process operations are not described in detail.

[0036] When used in conjunction with "including," "methods comprising," or similar language in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0037] The present invention is further described in detail below in conjunction with the full text.

[0038] Combined with Figure 1 and Figure 2 A high-speed VCSEL chip comprises a GaAs substrate, on which an n-DBR 21, a quantum well active region 22, a p-DBR 23, and a p-In 0.49 Ga 0.51 P cavity contact layer 24 and u-DBR 25;

[0039] Remove u-DBR25 and p-In by etching 0.49 Ga 0.51 The p-inner cavity contact layer 24 retains the light outlet region u-DBR25 during the etching process to form a circular table. 0.49 Ga 0.51 Metal is deposited on the P cavity contact layer 24 to form a p-type contact electrode 26, and a circular mesa structured optical port region u-DBR 25 is retained during the etching process;

[0040] Oxidized mesa etching, from p-In 0.49 Ga 0.51 P cavity contact layer 24 to n-DBR 21 is dry etched to form oxidation trench 27, and wet oxidation is used to form oxidation holes;

[0041] The n-electrode region is defined by photolithography, and the GaAs substrate is deeply etched to prepare an n-region metal contact electrode 28 on the GaAs substrate.

[0042] The u-DBR25 retained in the light outlet area has a table diameter of 3-5μm.

[0043] The distance between the terrace of the u-DBR 25 and the inner diameter of the p-type contact electrode 26 is 2-4 μm.

[0044] The p-In 0.49 Ga 0.51 The overall optical thickness of the P cavity contact layer 24 is 2-5λ.

[0045] In p-In 0.49 Ga 0.51 The metal deposited on the P cavity contact layer 24 to form the p-type contact electrode 26 is TiPtAu, and its typical thickness is 30 nm, 50 nm, and 200 nm, respectively.

[0046] Preferably, the p-In is removed by etching 0.49 Ga 0.51 The thickness of the P cavity contact layer 24 is less than half of the thickness of this layer.

[0047] A method for manufacturing a high-speed VCSEL chip comprises the following steps:

[0048] Step 1: On the GaAs substrate, epitaxially grow n-DBR 21, quantum well active region 22, oxide layer, p-DBR 23, p-In 0.49 Ga 0.51 P cavity contact layer 24 and u-DBR 25;

[0049] Step 2: Etch and remove u-DBR25 and p-In through the photoresist mask 0.49 Ga 0.51P cavity contact layer 24, the light-emitting hole area retains part of the u-DBR25 table for mode control function;

[0050] Step 3: Using electron beam evaporation on p-In 0.49 Ga 0.51 A p-type contact electrode 26 is prepared on the p-cavity contact layer 24;

[0051] Step 4: Use PECVD to grow a thickness of SiNx;

[0052] Step 5: using a photoresist as a mask, etching out an oxidation mesa and then performing wet oxidation to form a current limiting oxidation hole;

[0053] Step 6: After oxidation is completed, the growth thickness is The SiNx passivation layer is processed by BCB process and PECVD process photolithography and etching process;

[0054] Specifically, the BCB process is used; the PECVD growth thickness is about SiNx protective layer; contact hole Via lithography and RIE etching, remove part of SiNx on the contact electrode, so that part of the metal is exposed; after the seed layer is deposited, the photolithography process is carried out, and then Au with a thickness of 3.5um is electroplated. After the resist is removed, wet etching is used to remove part of the metal, and then it is rinsed clean; Street lithography and SiNx etching are used for dicing.

[0055] Step 7: Photolithography and deep etching of the front N-electrode region, the etching depth exceeds the n-DBR 21 and reaches the GaAs substrate, and the n-region metal contact electrode 28 is prepared on the GaAs substrate;

[0056] Step 8: Thinning and preparation of back metal;

[0057] Specifically, the front N electrode is prepared by photolithography and N electrode evaporation; the PECVD growth thickness is about SiNx protective layer; photolithography, etching to remove the electrode and passivation layer on the scribe line; thinning the back side to an overall thickness of about 150um, and then preparing the back side N-type electrode and thermal annealing.

[0058] Step 9: After laser cutting, a single or array VCSEL die is obtained.

[0059] Embodiment 1:

[0060] This embodiment takes 850nm data communication VCSEL as an example, and the specific process steps are as follows:

[0061] (1) Using the MOCVD growth method, n-DBR, quantum well active layer, oxide layer, p-DBR, p-In 0.49 Ga 0.51 P cavity contact layer, u-DBR and other epitaxial layers;

[0062] p-In 0.49 Ga 0.51 The number of u-DBR pairs on P is 6;

[0063] (2) After the epitaxial wafer is cleaned, the p-type metal ring deposition area is produced by photolithography;

[0064] (3) Through the photoresist mask, the u-DBR and part of the p-In deposition area of ​​the p-type metal ring are etched away 0.49 Ga 0.51 P layer. Figure 2 As shown, the center u-DBR table diameter is controlled at 3 μm;

[0065] (4) After photolithography, a p-side TiPtAu contact electrode is fabricated in the p-type metal deposition area by electron beam evaporation, where Ti Pt Au After metal deposition, the photoresist is removed by stripping. The inner side of the TiPtAu electrode ring is 2μm away from the u-DBR table. A slightly smaller distance is better, depending on the process level.

[0066] (5) PECVD growth thickness is about SiNx;

[0067] (6) using photoresist as a mask, etching out the oxidation mesa and then performing wet oxidation;

[0068] (7) After the oxidation is completed, the growth thickness is SiNx passivation layer;

[0069] (8) BCB process;

[0070] (9) PECVD growth thickness is about SiNx protective layer;

[0071] (10) Contact hole Via photolithography and RIE etching to remove part of SiNx on the contact electrode, so that part of the metal is exposed;

[0072] (11) After the seed layer is deposited, a photolithography process is performed, and then Au with a thickness of about 3.5 μm is electroplated. After the resist is removed, some metal is removed by wet etching, and then rinsed clean;

[0073] (12) Street lithography and SiNx etching;

[0074] (12) Photolithography of the front N-electrode region and deep etching of the PN region, the etching depth exceeds the n-DBR and reaches the N-side substrate;

[0075] (13) Front N-electrode photolithography and N-electrode evaporation preparation;

[0076] (14)PECVD growth thickness is about SiNx protective layer;

[0077] (15) Photolithography, etching to remove the electrodes and the passivation layer on the scribe line;

[0078] (16) The typical thickness after back thinning is 150 μm, followed by preparation and thermal annealing of the back N-type electrode;

[0079] (17) After laser cutting, a single or array VCSEL die is obtained.

[0080] Embodiment 2:

[0081] This embodiment takes 850nm data communication VCSEL as an example, and the specific process steps are as follows:

[0082] (1) Using the MOCVD growth method, n-DBR, quantum well active layer, oxide layer, p-DBR, p-In 0.49 Ga 0.51 P cavity contact layer, u-DBR and other epitaxial layers;

[0083] p-In 0.49 Ga 0.51 The number of u-DBR pairs on P is 10;

[0084] (2) After the epitaxial wafer is cleaned, the p-type metal ring deposition area is produced by photolithography;

[0085] (3) Through the photoresist mask, the u-DBR and part of the p-In deposition area of ​​the p-type metal ring are etched away 0.49 Ga 0.51 P layer. Figure 2 As shown, the center u-DBR table diameter is controlled at 3 μm;

[0086] (4) After photolithography, a p-side TiPtAu contact electrode is fabricated in the p-type metal deposition area by electron beam evaporation, where Ti Pt Au After metal deposition, the photoresist is removed by stripping. The inner side of the TiPtAu electrode ring is 2.5μm away from the u-DBR table. A slightly smaller distance is better, depending on the process level.

[0087] (5) PECVD growth thickness SiNx;

[0088] (6) using photoresist as a mask, etching out the oxidation mesa and then performing wet oxidation;

[0089] (7) After the oxidation is completed, the growth thickness is SiNx passivation layer;

[0090] (8) BCB process;

[0091] (9) PECVD growth thickness SiNx protective layer;

[0092] (10) Contact hole Via photolithography and RIE etching to remove part of SiNx on the contact electrode, so that part of the metal is exposed;

[0093] (11) After the seed layer is deposited, a photolithography process is performed, and then Au with a thickness of about 3.5 μm is electroplated. After the resist is removed, some metal is removed by wet etching, and then rinsed clean;

[0094] (12) Street lithography and SiNx etching;

[0095] (12) Photolithography of the front N-electrode region and deep etching of the PN region, the etching depth exceeds the n-DBR and reaches the N-side substrate;

[0096] (13) Front N-electrode photolithography and N-electrode evaporation preparation;

[0097] (14)PECVD growth thickness is about SiNx protective layer;

[0098] (15) Photolithography, etching to remove the electrodes and the passivation layer on the scribe line;

[0099] (16) The typical thickness after back thinning is 200 μm, followed by preparation and thermal annealing of the back N-type electrode;

[0100] (17) After laser cutting, a single or array VCSEL die is obtained.

[0101] Comparative Example:

[0102] 850nm datacom VCSELs are made in a conventional way.

[0103] The first embodiment, the second embodiment and the comparative example were tested, and during the test, the parameters of temperature, current, slope efficiency and series resistance were detected and recorded.

[0104] The recorded time is shown in Table 1 below: (taking OA 6.5um as an example)

[0105]

[0106]

[0107] 1. The logarithm of p-DBR is reduced, and the series resistance of the chip is reduced, so that when making a small oxidation aperture chip, its resistance is still maintained at a reasonable level, and the chip reliability and high temperature performance are better;

[0108] 2.p-In 0.49 Ga 0.51 The band gap width of the P cavity contact layer is 1.88eV, which is much larger than the 1.42V of GaAs, eliminating the negative effect of light absorption in the 850nm band;

[0109] 3. The u-DBR table retained at the light outlet makes the threshold gain difference between the fundamental mode and the high-order mode larger. In addition, the thicker p-In 0.49 Ga 0.51 There is still a certain light field intensity at the P cavity contact layer, which further increases the loss of high-order modes, allowing the chip to work stably in the fundamental mode and greatly increasing the modulation bandwidth.

[0110] The present invention and its embodiments are described above, and such description is not restrictive. What is shown in the full text is only one of the embodiments of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it, without departing from the purpose of the invention, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the present invention.

Claims

1. A high-speed VCSEL chip, characterized in that: The invention comprises a GaAs substrate, on which an n-DBR (21), a quantum well active region (22), a p-DBR (23), a p-In 0.49 Ga 0.51 P cavity contact layer (24) and u-DBR (25); The u-DBR (25) and p-In are removed by etching. 0.49 Ga 0.51 The p-inner cavity contact layer (24) retains the light outlet region u-DBR (25) during the etching process to form a circular table. 0.49 Ga 0.51 A metal is deposited on the P cavity contact layer (24) to form a p-type contact electrode (26), and a circular mesa structured optical port region u-DBR (25) is retained during the etching process; Oxidized mesa etching, from p-In 0.49 Ga 0.51 A P cavity contact layer (24) to the n-DBR (21) is wet oxidized to form a current limiting oxide hole (27); The n-electrode region is defined by photolithography, and the GaAs substrate is deeply etched to prepare an n-region metal contact electrode (28) on the GaAs substrate.

2. A high-speed VCSEL chip according to claim 1, characterized in that: The u-DBR (25) retained in the light outlet region has a terrace diameter of 3-5 μm.

3. A high-speed VCSEL chip according to claim 1, characterized in that: The distance between the terrace of the u-DBR (25) and the inner diameter of the p-type contact electrode (26) is 2-4 μm.

4. A high-speed VCSEL chip according to claim 1, characterized in that: The p-In 0.49 Ga 0.51 The overall optical thickness of the P cavity contact layer (24) is 2-5λ.

5. The high-speed VCSEL chip according to claim 1, characterized in that: In p-In 0.49 Ga 0.51 The metal deposited on the P cavity contact layer (24) to form the p-type contact electrode (26) is TiPtAu, and its typical thickness is 30nm, 50nm, and 200nm respectively.

6. A high-speed VCSEL chip according to claim 1, characterized in that: Removal of p-In by etching 0.49 Ga 0.51 The thickness of the P inner cavity contact layer (24) is less than half of the thickness of this layer.

7. A method for manufacturing a high-speed VCSEL chip, characterized in that: The following steps are involved: Step 1: On a GaAs substrate, epitaxially grow n-DBR (21), quantum well active region (22), oxide layer, p-DBR (23), p-In 0.49 Ga 0.51 P cavity contact layer (24) and u-DBR (25); Step 2: Remove u-DBR (25) and p-In by etching through a photoresist mask 0.49 Ga 0.51 The P cavity contact layer (24) retains part of the u-DBR (25) terrace in the light-emitting hole region for mode control function; Step 3: Using electron beam evaporation on p-In 0.49 Ga 0.51 A p-type contact electrode (26) is prepared on the p-cavity contact layer (24); Step 4: Use PECVD to grow a thickness of SiNx; Step 5: using a photoresist as a mask, etching out an oxidized mesa and then performing wet oxidation to form an oxidized trench (27); Step 6: After oxidation is completed, the growth thickness is The SiNx passivation layer is processed by BCB process and PECVD process photolithography and etching process; Step 7: Photolithography and deep etching of the front N-electrode region, the etching depth exceeds the n-DBR (21) and reaches the GaAs substrate, and an n-region metal contact electrode (28) is prepared on the GaAs substrate; Step 8: Thinning and preparation of back metal; Step 9: After laser cutting, a single or array VCSEL die is obtained.

8. The method for manufacturing a high-speed VCSEL chip according to claim 7, characterized in that: The thickness after thinning in step 8 is typically 150um or 200um after thinning the back side.

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