Gray mapping for variable to fixed distribution matching

Abstract

Certain aspects of the present disclosure provide a method for wireless communication by a transmitter. The method generally includes obtaining a first block of information bits from a buffer; generating a first sequence of probability amplitude shaping (PAS) symbols from the first block of information bits using a demapper function and an arithmetic decoder function; transmitting the first PAS symbol sequence to a receiver; combining a first subset of the first block of information bits identified by an arithmetic encoder function and a mapper function with a second block of information bits from the buffer; generating a second PAS symbol sequence from the combined first subset of the first block of information bits and the second block of information bits using the demapper function and the arithmetic decoder function; and transmitting the second PAS symbol sequence to the receiver.

Description

Background Art Technical Field

[0001] Aspects of the present disclosure relate to wireless communications and, more particularly, to techniques for wireless transmissions.

[0002] Related technologies

[0003] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, broadcasts or other similar types of services. These wireless communication systems may employ multiple-access technologies capable of supporting communication with multiple users by sharing available wireless communication system resources with the multiple users.

[0004] Although wireless communication systems have made tremendous technical progress over the years, challenges still exist. For example, complex and dynamic environments can still attenuate or block signals between wireless transmitters and wireless receivers. Therefore, there is a continuous desire to improve the technical performance of wireless communication systems, including, for example: improving the speed and data carrying capacity of communications, improving the efficiency of using shared communication media, reducing the power used by transmitters and receivers when performing communications, improving the reliability of wireless communications, avoiding redundant transmission and / or reception and related processing, improving the coverage area of ​​wireless communications, increasing the number and types of devices that can access wireless communication systems, increasing the ability of different types of devices to communicate with each other, increasing the number and types of wireless communication media available for use, etc. Therefore, there is a need to further improve wireless communication systems to overcome the above-mentioned technical challenges and other challenges. Summary of the invention

[0005] One aspect provides a method for wireless communication at a transmitter. The method generally includes: obtaining a first information bit block from a buffer; generating a first probability amplitude shaping (PAS) symbol sequence from the first information bit block using a demapper function and an arithmetic decoder function; sending the first PAS symbol sequence to a receiver; combining a first subset of the first information bit block identified by the arithmetic encoder function and the mapper function with a second information bit block from the buffer; generating a second PAS symbol sequence from the combined first subset of the first information bit block and the second information bit block using the demapper function and the arithmetic decoder function; and sending the second PAS symbol sequence to the receiver.

[0006] One aspect provides a method for wireless communication at a receiver. The method generally includes: receiving a first probability amplitude shaping (PAS) symbol sequence generated based on a first information bit block from a transmitter; identifying a first subset of the first information bit block using an arithmetic encoder function and a mapper function; storing a second subset of the first information bit block in a buffer using an arithmetic encoder function and a mapper function, wherein the second subset includes a remaining set of the first information bit block after discarding the first subset; receiving a second PAS symbol sequence generated by combining the first subset of the first information bit block with a second information bit block; and updating the buffer based on the combined first subset and the subset of the second information bit block identified using the arithmetic encoder function and the mapper function.

[0007] Other aspects provide: an apparatus operable to, configured to, or otherwise adapted to perform the foregoing method and those described elsewhere herein; a non-transitory computer-readable medium comprising instructions that, when executed by a processor of the apparatus, cause the apparatus to perform the foregoing method and those described elsewhere herein; a computer program product embodied on a computer-readable storage medium, the computer-readable storage medium comprising code for performing the foregoing method and those described elsewhere herein; and an apparatus comprising components for performing the foregoing method and those described elsewhere herein. By way of example, an apparatus may include a processing system, a device having a processing system, or a processing system cooperating through one or more networks.

[0008] For purposes of illustration, the following description and drawings set forth certain features. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings depict certain features of the aspects described herein and should not be considered to limit the scope of the disclosure.

[0010] Figure 1 An example wireless communication network is depicted.

[0011] Figure 2 An example disaggregated base station architecture is depicted.

[0012] Figure 3 Aspects of an example base station and example user equipment are depicted.

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D Various example aspects of data structures for a wireless communication network are described.

[0014] Figure 5 Example implementations of transmitters and receivers are depicted.

[0015] Fig. 6A and Figure 6B Examples of an amplitude shaper and an amplitude deshaper are depicted, respectively.

[0016] Fig. 7A and Figure 7B An example of another amplitude shaper and another amplitude deshaper is depicted, respectively.

[0017] Figure 8 Depicted is an example output of the amplitude deshaper.

[0018] Fig. 9A and Fig. 9B Examples of amplitude shapers and amplitude deshapers according to aspects of the present disclosure are depicted.

[0019] Fig.10 Depicted are example outputs of an amplitude deshaper in accordance with aspects of the present disclosure.

[0020] Fig.11 Depicted are examples of coding schemes for variable to fixed distribution matching in accordance with aspects of the present disclosure.

[0021] Fig.12 Depicted are example implementations of a transmitter and a receiver with a coding scheme for variable to fixed distribution matching in accordance with aspects of the present disclosure.

[0022] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D Depicted are examples of iterative transmit processing utilizing a transmitter and a receiver with a coding scheme for variable to fixed distribution matching in accordance with aspects of the present disclosure.

[0023] Fig.14 A method for wireless communication is described.

[0024] Fig.15 A method for wireless communication is described.

[0025] Fig.16 Aspects of an example communications device are depicted.

[0026] Fig.17 Aspects of an example communications device are depicted. DETAILED DESCRIPTION

[0027] Aspects of the present disclosure provide apparatus, methods, processing systems, and computer-readable media for wireless transmission. Specifically, the techniques presented herein include encoding techniques for transmission schemes involving variable to fixed distribution matching, such as Gray mapping.

[0028] Communication can be performed over a channel if the transmission rate on the channel meets the capacity based on the transmission power and the signal-to-noise ratio (SNR). Shannon capacity refers to a theorem that defines the maximum amount of information that can be sent over a channel (e.g., a wireless channel). Commonly used coded modulation (CM) techniques (such as amplitude shift keying (ASK) and quadrature amplitude modulation (QAM)) have a signal constellation characterized by equidistant signal points and uniform signaling (e.g., a non-Gaussian distribution of information), which means that each signal point is sent with the same probability. Unfortunately, uniform signaling can optimistically achieve an achievable information rate (AIR) that differs from the capacity of an AWGN channel by 1.53 dB (0.255 bits per dimension (bits / 1-D)) (sometimes referred to as a "shaping gap").

[0029] In order to close the shaping gap and to increase spectral efficiency, signal shaping techniques can be applied to generate a non-uniform distribution of information. For example, in geometric shaping, the constellation points are arranged in a non-equidistant manner in the complex plane to simulate the capacity of the distribution. On the other hand, probability shaping starts with a constellation with equidistant signal points (e.g., ASK or QAM), but assigns different probabilities to different constellation points.

[0030] Examples of probabilistic shaping include mesh shaping and shell mapping. Probabilistic amplitude shaping (PAS) is another technique that employs probabilistic shaping that has achieved high throughput (e.g., over 10 GB / sec) for commercial use in optical core networks. Probabilistic shaping provides low complexity and flexible integration with existing coding schemes. PAS typically provides low complexity integration of amplitude shaping into existing binary forward error correction (FEC) systems as well as large shaping gain and inherent rate adaptation functionality.

[0031] In some cases, a PAS-based transmitter may perform additional processing to increase spectral efficiency. For example, in a variable-to-fixed distribution matching scheme, a PAS-based transmitter may perform processing to identify the number of information bits that may be successfully received at the receiver (by emulating the receiver-side processing at the transmitter) in order to avoid sending additional bits that may be discarded at the receiver. In this way, the variable-to-fixed scheme may limit the amount of signaling overhead.

[0032] Various aspects of the present disclosure propose enhancements to PAS-based transmission schemes by introducing Gray mapping in the PAS architecture. As will be described in more detail below, utilizing Gray mapping in the PAS architecture can help increase the number of information bits that may be successfully received at the receiver, which can result in a reduction in the number of transmissions.

[0033] Introduction to Wireless Communication Networks

[0034] The techniques and methods described herein can be used in various wireless communication networks. Although various aspects may be described herein using terms commonly associated with 3G, 4G and / or 5G wireless technologies, various aspects of the present disclosure may also be applicable to other communication systems and standards not explicitly mentioned herein.

[0035] Figure 1 An example of a wireless communication network 100 is depicted in which various aspects described herein may be implemented.

[0036] In general, the wireless communication network 100 includes various network entities (alternatively, network elements or network nodes). A network entity is typically a communication device and / or a communication function performed by a communication device. For example, various functions of a network and various devices associated with and interacting with the network can be considered network entities.

[0037] In the depicted example, the wireless communication network 100 includes a base station (BS) 102, a user equipment (UE) 104, and one or more core networks such as an evolved packet core (EPC) 160 and a 5G core (5GC) network 190, which interoperate to provide communication services over various communication links, including wired and wireless links.

[0038] Figure 1 Various example UEs 104 are depicted, which may more generally include: a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop, a personal digital assistant (PDA), a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player, a camera, a game console, a tablet computer, a smart device, a wearable device, a vehicle, an electric meter, a gas pump, a large or small kitchen appliance, a healthcare device, an implant, a sensor / actuator, a display, an Internet of Things (IoT) device, an Always-On (AON) device, an edge processing device, or other similar devices. UE 104 may also be more generally referred to as a mobile device, a wireless device, a wireless communication device, a station, a mobile station, a subscriber station, a mobile subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a remote device, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, and others.

[0039] BS 102 communicates wirelessly with UE 104 via communication link 120. Communication link 120 between BS 102 and UE 104 may include uplink (UL) (also referred to as a reverse link) transmissions from UE 104 to BS 102 and / or downlink (DL) (also referred to as a forward link) transmissions from BS 102 to UE 104. In various aspects, communication link 120 may utilize multiple-input multiple-output (MIMO) antenna technology, including spatial multiplexing, beamforming, and / or transmit diversity.

[0040] BS 102 may generally include: Node B, enhanced Node B (eNB), next generation enhanced Node B (ng-eNB), next generation Node B (gNB or gNodeB), access point, base transceiver station, radio base station, radio transceiver, transceiver function, transmission and reception point, etc. Each of BS 102 may provide communication coverage for a corresponding geographic coverage area 110, which may sometimes be referred to as a cell, and may overlap in some cases (e.g., a small cell 102' may have a coverage area 110' that overlaps with the coverage area 110 of a macro cell). For example, a BS may provide communication coverage for a macro cell (covering a relatively large geographic area), a pico cell (covering a relatively small geographic area, such as a stadium), a femto cell (relatively smaller geographic area (e.g., a residence)), and / or other types of cells.

[0041] Although BS102 is depicted as a single communication device in various aspects, BS102 can be implemented in various configurations. For example, one or more components of the base station may be decomposed, including a central unit (CU), one or more distributed units (DU), one or more radio units (RU), a radio unit (RU), a near real-time (near RT) RAN intelligent controller (RIC), or a non-real-time (non-RT) RIC, to name a few examples. In another example, various aspects of the base station may be virtualized. More generally, a base station (e.g., BS102) may include components located at a single physical location or components located at various physical locations. In an example in which the base station includes components located at various physical locations, the various components may each perform a function so that the various components together implement functions similar to those of a base station located at a single physical location. In some aspects, a base station including components located at various physical locations may be referred to as a decomposed radio access network architecture (such as an open RAN (O-RAN) or virtualized RAN (VRAN) architecture). Figure 2 An example decomposed base station architecture is depicted and described.

[0042] Different BSs 102 within the wireless communication network 100 may also be configured to support different radio access technologies, such as 3G, 4G, and 5G. For example, a BS 102 configured for 4G LTE (collectively referred to as the Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN)) may interface with the EPC 160 via a first backhaul link 132 (e.g., an S1 interface). A BS 102 configured for 5G (e.g., 5G NR or Next Generation RAN (NG-RAN)) may interface with the 5GC 190 via a second backhaul link 184. The BSs 102 may communicate with each other directly or indirectly (e.g., via the EPC 160 or the 5GC 190) over a third backhaul link 134 (e.g., an X2 interface), which may be wired or wireless.

[0043] The wireless communication network 100 may subdivide the electromagnetic spectrum into various categories, frequency bands, channels, or other characteristics. In some aspects, the subdivision is provided based on wavelength and frequency, where frequency may also be referred to as a carrier, subcarrier, channel, tone, or subband. For example, 3GPP currently defines frequency range 1 (FR1) as including 600 MHz-6 GHz, which is often (interchangeably) referred to as "below 6 GHz". Similarly, 3GPP currently defines frequency range 2 (FR2) as including 26 GHz-41 GHz, which is sometimes (interchangeably) referred to as "millimeter wave" ("mmW" or "mmWave"). A base station (e.g., a mmWave base station such as BS180) configured to communicate using mmWave / near mmWave radio bands may utilize beamforming (e.g., 182) with a UE (e.g., 104) to improve path loss and range.

[0044] The communication link 120 between the BS 102 and, for example, the UE 104 may be through one or more carriers, which may have different bandwidths (e.g., 5 MHz, 10 MHz, 15 MHz, 20 MHz, 100 MHz, 400 MHz, and other MHz) and may be aggregated in various aspects. The carriers may or may not be adjacent to each other. The allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated for DL ​​compared to UL).

[0045] Communications using higher frequency bands may have higher path loss and shorter range than communications at lower frequencies. Figure 1180) can utilize beamforming 182 with UE 104 to improve path loss and range. For example, BS 180 and UE 104 may each include multiple antennas, such as antenna elements, antenna panels and / or antenna arrays, to facilitate beamforming. In some cases, BS 180 may send beamformed signals to UE 104 in one or more transmit directions 182'. UE 104 may receive beamformed signals from base station 180 in one or more receive directions 182". UE 104 may also send beamformed signals to base station 180 in one or more transmit directions 182". BS 180 may also receive beamformed signals from UE 104 in one or more receive directions 182'. Base station 180 and UE 104 may then perform beam training to determine the best receive direction and transmit direction for each of BS 180 and UE 104. It is worth noting that the transmit direction and receive direction of BS 180 may be the same or different. Similarly, the transmit direction and receive direction of UE 104 may be the same or different.

[0046] Wireless communication network 100 also includes Wi-Fi AP 150 that communicates with Wi-Fi station (STA) 152 via communication link 154 in, for example, the 2.4 GHz and / or 5 GHz unlicensed spectrum.

[0047] Certain UEs 104 may communicate with each other using a device-to-device (D2D) communication link 158. The D2D communication link 158 may use one or more sidelink channels, such as a physical sidelink broadcast channel (PSBCH), a physical sidelink discovery channel (PSDCH), a physical sidelink shared channel (PSSCH), and a physical sidelink control channel (PSCCH).

[0048] The EPC 160 may include various functional components, including, in the depicted example: a mobility management entity (MME) 162, other MMEs 164, a serving gateway 166, a multimedia broadcast multicast service (MBMS) gateway 168, a broadcast multicast service center (BM-SC) 170, and a packet data network (PDN) gateway 172. The MME 162 may communicate with a home subscriber server (HSS) 174. The MME 162 is a control node that handles signaling between the UE 104 and the EPC 160. In general, the MME 162 provides bearer and connection management.

[0049] Generally speaking, user Internet Protocol (IP) packets are delivered through the Serving Gateway 166, which itself is connected to the PDN Gateway 172. The PDN Gateway 172 provides UE IP address allocation and other functions. The PDN Gateway 172 and the BM-SC 170 are connected to the IP Services 176, which may include, for example, the Internet, an Intranet, an IP Multimedia Subsystem (IMS), a Packet Switched (PS) streaming media service, and / or other IP services.

[0050] The BM-SC 170 may provide functionality for MBMS user service configuration and delivery. The BM-SC 170 may serve as an entry point for content provider MBMS delivery, may be used to authorize and initiate MBMS bearer services within a public land mobile network (PLMN), and may be used to schedule MBMS delivery. The MBMS Gateway 168 may be used to distribute MBMS services to BSs 102 belonging to a multicast broadcast single frequency network (MBSFN) area that broadcasts a particular service, and may be responsible for session management (start / stop) and for collecting eMBMS-related charging information.

[0051] 5GC 190 may include various functional components, including: access and mobility management function (AMF) 192, other AMFs 193, session management function (SMF) 194, and user plane function (UPF) 195. AMF 192 may communicate with unified data management (UDM) 196.

[0052] AMF 192 is a control node that handles signaling between UE 104 and 5GC 190. AMF 192 provides, for example, Quality of Service (QoS) flow and session management.

[0053] Internet Protocol (IP) packets are delivered through UPF 195, which is connected to IP Services 197 and provides IP address allocation for UEs and other functions for 5GC 190. IP Services 197 may include, for example, the Internet, Intranet, IMS, PS streaming services, and / or other IP services.

[0054] In various aspects, a network entity or network node may be implemented as a converged base station, a decomposed base station, an integrated access and backhaul (IAB) node, a relay node, a sidelink node, to name a few examples.

[0055] Figure 2An example disaggregated base station 200 architecture is depicted. The disaggregated base station 200 architecture may include one or more central units (CUs) 210 that may communicate directly with a core network 220 via a backhaul link, or indirectly with the core network 220 through one or more disaggregated base station units, such as a near real-time (near-RT) RAN intelligent controller (RIC) 225 via an E2 link, or a non-real-time (non-RT) RIC 215 associated with a service management and orchestration (SMO) framework 205, or both. The CU 210 may communicate with one or more distributed units (DUs) 230 via respective midhaul links, such as an F1 interface. The DU 230 may communicate with one or more radio units (RUs) 240 via respective fronthaul links. The RU 240 may communicate with respective UEs 104 via one or more radio frequency (RF) access links. In some implementations, a UE 104 may be served simultaneously by multiple RUs 240.

[0056] Each of the units (e.g., CU 210, DU 230, RU 240, and near-RT RIC 225, non-RT RIC 215, and SMO framework 205) may include or be coupled to one or more interfaces configured to receive or send signals, data, or information (collectively referred to as signals) via a wired or wireless transmission medium. Each of the units or an associated processor or controller that provides instructions to the communication interface of these units may be configured to communicate with one or more of the other units via a transmission medium. For example, these units may include a wired interface configured to receive or send signals to one or more of the other units via a wired transmission medium. Additionally, these units may include a wireless interface that may include a receiver, a transmitter, or a transceiver (such as a radio frequency (RF) transceiver) that is configured to receive or send signals, or both, to one or more of the other units via a wireless transmission medium.

[0057] In some aspects, CU 210 may host one or more higher layer control functions. Such control functions may include radio resource control (RRC), packet data convergence protocol (PDCP), service data adaptation protocol (SDAP), etc. Each control function may be implemented using an interface that is configured to communicate signals with other control functions hosted by CU 210. CU 210 may be configured to handle user plane functionality (e.g., central unit-user plane (CU-UP)), control plane functionality (e.g., central unit-control plane (CU-CP)), or a combination thereof. In some specific implementations, CU 210 may be logically split into one or more CU-UP units and one or more CU-CP units. When implemented in an O-RAN configuration, the CU-UP unit may communicate bidirectionally with the CU-CP unit via an interface (such as an E1 interface). As needed, CU 210 may be implemented to communicate with DU 230 for network control and signaling.

[0058] DU 230 may correspond to a logical unit that includes one or more base station functions for controlling the operation of one or more RUs 240. In some aspects, DU 230 may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, etc.) at least in part according to a functional split such as defined by the Third Generation Partnership Project (3GPP). In some aspects, DU 230 may further host one or more low PHY layers. Each layer (or module) may be implemented using an interface that is configured to communicate signals with other layers (and modules) hosted by DU 230 or with control functions hosted by CU 210.

[0059] The lower layer functionality may be implemented by one or more RUs 240. In some deployments, the RU 240 controlled by the DU 230 may correspond to a logical node that hosts RF processing functions or low PHY layer functions (such as performing fast Fourier transform (FFT), inverse FFT (iFFT), digital beamforming, physical random access channel (PRACH) extraction and filtering, etc.), or both, based at least in part on functional splitting (such as lower layer functional splitting). In such an architecture, the RU 240 may be implemented to handle over-the-air (OTA) communications with one or more UEs 104. In some implementations, real-time and non-real-time aspects of control plane and user plane communications with the RU 240 may be controlled by the corresponding DU 230. In some scenarios, this configuration may enable the implementation of the DU 230 and the CU 210 in a cloud-based RAN architecture (such as a vRAN architecture).

[0060] The SMO framework 205 may be configured to support RAN deployment and provisioning of non-virtualized network elements and virtualized network elements. For non-virtualized network elements, the SMO framework 205 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements, which may be managed via an operation and maintenance interface (such as an O1 interface). For virtualized network elements, the SMO framework 205 may be configured to interact with a cloud computing platform (such as an open cloud (O-Cloud) 290) to perform network element lifecycle management (such as instantiating virtualized network elements) via a cloud computing platform interface (such as an O2 interface). Such virtualized network elements may include, but are not limited to, CU 210, DU 230, RU 240, and near-RT RIC 225. In some specific implementations, the SMO framework 205 may communicate with hardware aspects of the 4G RAN (such as an open eNB (O-eNB) 211) via the O1 interface. Additionally, in some specific implementations, the SMO framework 205 may communicate directly with one or more RUs 240 via the O1 interface. The SMO framework 205 may also include a non-RT RIC 215 configured to support the functionality of the SMO framework 205 .

[0061] The non-RT RIC 215 may be configured to include logic functions that enable non-real-time control and optimization of RAN elements and resources, artificial intelligence / machine learning (AI / ML) workflows including model training and updating, or policy-based guidance of applications / features in the near-RT RIC 225. The non-RT RIC 215 may be coupled to or in communication with the near-RT RIC 225 (such as via an A1 interface). The near-RT RIC 225 may be configured to include logic functions that enable near-real-time control and optimization of RAN elements and resources via data collection and actions through an interface (such as via an E2 interface) that connects one or more CUs 210, one or more DUs 230, or both, and the O-eNB with the near-RT RIC 225.

[0062] In some implementations, in order to generate an AI / ML model to be deployed in the near-RT RIC 225, the non-RT RIC 215 may receive parameters or external enrichment information from an external server. Such information may be utilized by the near-RT RIC 225 and may be received from a non-network data source or from a network function at the SMO framework 205 or the non-RT RIC 215. In some examples, the non-RT RIC 215 or the near-RT RIC 225 may be configured to tune RAN behavior or performance. For example, the non-RT RIC 215 may monitor long-term trends and patterns of performance and employ AI / ML models to perform corrective actions through the SMO framework 205 (such as via reconfiguration of O1) or via the creation of RAN management policies (such as A1 policies).

[0063] Figure 3 Aspects of an example BS 102 and UE 104 are depicted.

[0064] In general, BS 102 includes various processors (e.g., 320, 330, 338, and 340), antennas 334a-334t (collectively 334), transceivers 332a-332t (collectively 332) including modulators and demodulators, and other aspects that enable wireless transmission of data (e.g., data source 312) and wireless reception of data (e.g., data sink 339). For example, BS 102 can transmit and receive data between BS 102 and UE 104. BS 102 includes a controller / processor 340 that can be configured to implement various functions described herein related to wireless communication.

[0065] In general, the UE 104 includes various processors (e.g., 358, 364, 366, and 380), antennas 352a-352r (collectively 352), transceivers 354a-354r (collectively 354) including modulators and demodulators, and other aspects that enable wireless transmission of data (e.g., data source 362) and wireless reception of data (e.g., data sink 360). The UE 104 includes a controller / processor 380 that can be configured to implement various functions described herein related to wireless communications.

[0066] Regarding example downlink transmissions, BS 102 includes a transmit processor 320 that can receive data from a data source 312 and control information from a controller / processor 340. The control information can be for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical HARQ indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. In some examples, the data can be for a physical downlink shared channel (PDSCH).

[0067] The transmit processor 320 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 320 may also generate reference symbols (such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS)).

[0068] The transmit (Tx) multiple-input multiple-output (MIMO) processor 330 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 332a-332t. Each modulator in the transceiver 332a-332t may process a corresponding output symbol stream to obtain an output sample stream. Each modulator may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the modulators in the transceivers 332a-332t may be transmitted via antennas 334a-334t, respectively.

[0069] To receive downlink transmissions, UE 104 includes antennas 352a-352r that can receive downlink signals from BS 102 and can provide received signals to demodulators (DEMODs) in transceivers 354a-354r, respectively. Each demodulator in transceivers 354a-354r can condition (e.g., filter, amplify, downconvert, and digitize) a corresponding received signal to obtain input samples. Each demodulator can further process the input samples to obtain received symbols.

[0070] A MIMO detector 356 may obtain received symbols from all demodulators in transceivers 354a-354r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 358 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 104 to a data sink 360, and provide decoded control information to a controller / processor 380.

[0071] With respect to example uplink transmissions, the UE 104 also includes a transmit processor 364 that may receive and process data from a data source 362 (e.g., for a PUSCH) and control information from a controller / processor 380 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 364 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 364 may be pre-decoded by a TxMIMO processor 366, where applicable, further processed by a modulator in the transceivers 354a-354r (e.g., for SC-FDM), and transmitted to the BS 102.

[0072] At BS 102, uplink signals from UE 104 may be received by antennas 334 a-334 t, processed by demodulators in transceivers 332 a-332 t, detected by MIMO detector 336 if applicable, and further processed by receive processor 338 to obtain decoded data and control information transmitted by UE 104. Receive processor 338 may provide decoded data to data sink 339 and decoded control information to controller / processor 340.

[0073] Memories 342 and 382 may store data and program codes for BS 102 and UE 104, respectively.

[0074] The scheduler 344 may schedule UEs for data transmission on the downlink and / or uplink.

[0075] In various aspects, BS 102 may be described as sending and receiving various types of data associated with the methods described herein. In these contexts, "sending" may refer to various mechanisms for outputting data, such as outputting data from a data source 312, a scheduler 344, a memory 342, a transmit processor 320, a controller / processor 340, a Tx MIMO processor 330, a transceiver 332a-332t, an antenna 334a-334t, and / or other aspects described herein. Similarly, "receiving" may refer to various mechanisms for obtaining data, such as obtaining data from antennas 334a-334t, transceivers 332a-332t, an Rx MIMO detector 336, a controller / processor 340, a receive processor 338, a scheduler 344, a memory 342, and other aspects described herein.

[0076] In various aspects, the UE 104 may also be described as sending and receiving various types of data associated with the methods described herein. In these contexts, "sending" may refer to various mechanisms for outputting data, such as outputting data from a data source 362, a memory 382, ​​a transmit processor 364, a controller / processor 380, a Tx MIMO processor 366, a transceiver 354a-354t, an antenna 352a-352t, and / or other aspects described herein. Similarly, "receiving" may refer to various mechanisms for obtaining data, such as obtaining data from an antenna 352a-352t, a transceiver 354a-354t, an Rx MIMO detector 356, a controller / processor 380, a receive processor 358, a memory 382, ​​and other aspects described herein.

[0077] In some aspects, the processor may be configured to perform various operations (such as those associated with the methods described herein) and send (output) data to or receive (obtain) data from another interface configured to send or receive data, respectively.

[0078] Figure 4A , Figure 4B , Figure 4C and Figure 4D Describes a method for use in a wireless communication network such as Figure 1 Various aspects of the data structure of the wireless communication network 100).

[0079] Specifically, Figure 4A is a diagram 400 illustrating an example of a first subframe within a 5G (e.g., 5G NR) frame structure, Figure 4B is a diagram 430 illustrating an example of a DL channel within a 5G subframe, Figure 4C is a diagram 450 illustrating an example of a second subframe within a 5G frame structure, and Figure 4D FIG480 is a diagram illustrating an example of UL channels within a 5G subframe.

[0080] Wireless communication networks can utilize Orthogonal Frequency Division Multiplexing (OFDM) with a Cyclic Prefix (CP) on both the uplink and downlink. Such systems can also support half-duplex operation using Time Division Duplex (TDD). OFDM and Single Carrier Frequency Division Multiplexing (SC-FDM) can be used to maximize the system bandwidth (e.g., Figure 4B and Figure 4D ) is divided into multiple orthogonal subcarriers. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM.

[0081] The wireless communication frame structure may be frequency division duplex (FDD), where for a particular set of subcarriers, and subframes within the subcarrier set are dedicated to DL or UL. The wireless communication frame structure may also be time division duplex (TDD), where for a particular set of subcarriers, and subframes within the subcarrier set are dedicated to both DL and UL.

[0082] exist Figure 4A and Figure 4C In the wireless communication frame structure, TDD is used, where D is DL, U is UL, and X is used flexibly between DL / UL. The UE can be configured with the slot format (dynamically configured by DL control information (DCI) or semi-statically / statically configured by radio resource control (RRC) signaling) through the received slot format indicator (SFI). In the depicted example, the 10ms frame is divided into 10 1ms subframes of equal size. Each subframe may include one or more slots. In some examples, each slot may include 7 or 14 symbols, depending on the slot configuration. The subframe may also include microslots, which generally have fewer symbols than the entire slot. Other wireless communication technologies may have different frame structures and / or different channels.

[0083] In general, the number of slots within a subframe is based on the slot configuration and parameter set. For slot configuration 0, different parameter sets (μ) 0 to 5 allow for 1, 2, 4, 8, 16, and 32 slots per subframe, respectively. For slot configuration 1, different parameter sets 0 to 2 allow for 2, 4, and 8 slots per subframe, respectively. Thus, for slot configuration 0 and parameter set μ, there are 14 symbols / slot and 2μ slots / subframe. The subcarrier spacing and symbol length / duration are a function of the parameter set. The subcarrier spacing can be equal to 2 μ × 15kHz, where μ is parameter set 0 to 5. Thus, parameter set μ=0 has a subcarrier spacing of 15kHz, and parameter set μ=5 has a subcarrier spacing of 480kHz. The symbol length / duration is inversely related to the subcarrier spacing. Figure 4A , Figure 4B , Figure 4C and Figure 4D An example is provided for slot configuration 0 with 14 symbols per slot and parameter set μ=2 with 4 slots per subframe. The slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 μs.

[0084] like Figure 4A , Figure 4B , Figure 4C and Figure 4DAs depicted in , a resource grid can be used to represent a frame structure. Each time slot includes a resource block (RB) (also called a physical RB (PRB)) extending over 12 consecutive subcarriers. The resource grid is divided into a plurality of resource elements (REs). The number of bits carried by each RE depends on the modulation scheme.

[0085] like Figure 4A As illustrated, some of the REs carry data for UEs (eg, Figure 1 and Figure 3 The RS may include a demodulation RS (DMRS) and a channel state information reference signal (CSI-RS) for channel estimation at the UE. The RS may also include a beam measurement RS (BRS), a beam refinement RS (BRRS), and a phase tracking RS (PT-RS).

[0086] Figure 4B Examples of various DL channels within a subframe of a frame are illustrated.The Physical Downlink Control Channel (PDCCH) carries DCI within one or more Control Channel Elements (CCEs), each CCE comprising nine RE Groups (REGs), each REG comprising four consecutive REs in an OFDM symbol.

[0087] The primary synchronization signal (PSS) may be in symbol 2 of a particular subframe of a frame. The PSS is transmitted by a UE (e.g., Figure 1 and Figure 3 104) is used to determine subframe / symbol timing and physical layer identification.

[0088] A Secondary Synchronization Signal (SSS) may be within symbol 4 of a particular subframe of a frame. The SSS is used by the UE to determine the physical layer cell identity group number and radio frame timing.

[0089] Based on the physical layer identifier and the physical layer cell identifier group number, the UE can determine the physical cell identifier (PCI). Based on the PCI, the UE can determine the location of the aforementioned DMRS. The physical broadcast channel (PBCH) carrying the master information block (MIB) can be logically grouped with the PSS and SSS to form a synchronization signal (SS) / PBCH block. The MIB provides the system frame number (SFN) and the number of RBs in the system bandwidth. The physical downlink shared channel (PDSCH) carries user data, broadcast system information such as system information blocks (SIBs) that are not sent via the PBCH, and paging messages.

[0090] As in Figure 4CAs illustrated in , some REs carry DMRS for channel estimation at the base station (indicated as R for a specific configuration, but other DMRS configurations are possible). The UE may send DMRS for PUCCH and DMRS for PUSCH. The PUSCH DMRS may be sent, for example, in the first one or two symbols of the PUSCH. The PUCCH DMRS may be sent in different configurations depending on whether a short PUCCH or a long PUCCH is sent and depending on the specific PUCCH format used. UE 104 may also send a sounding reference signal (SRS). The SRS may be sent, for example, in the last symbol of a subframe. The SRS may have a comb structure, and the UE may send the SRS on one of the teeth of the comb. The SRS may be used by the base station for channel quality estimation to achieve frequency-dependent scheduling of the UL.

[0091] Figure 4D Examples of various UL channels within a subframe of a frame are illustrated. The PUCCH may be located at a position as indicated in one configuration. The PUCCH carries uplink control information (UCI), such as scheduling requests, channel quality indicator (CQI), precoding matrix indicator (PMI), rank indicator (RI), and HARQ ACK / NACK feedback. The PUSCH carries data and may additionally be used to carry a buffer status report (BSR), a power headroom report (PHR), and / or UCI.

[0092] Example Probabilistic Amplitude Shaping Architecture

[0093] Figure 5 A communication system employing probability amplitude shaping is illustrated. Probability amplitude shaping (PAS) utilizes reverse concatenation, whereby shaping precedes FEC decoding.

[0094] The communication system 500 includes a wireless transmitter 501 and a wireless receiver 503. For example, an information source 502 may generate k information bits that are received by an amplitude shaper 504. The amplitude shaper 504 may generate a sequence of symbols (e.g., n symbols fixed to a fixed scheme or variable to a fixed scheme). symbols). The symbol sequence (n symbols or Symbols) may be received by amplitude to bit component 506 and then received by FEC encoder 508 to produce a set of bits. In some examples, some of these bits are shaped and other bits are evenly distributed. After encoding, these bits are mapped to, for example, quadrature amplitude modulation (QAM) symbols by QAM mapping component 510. Signal 511 (e.g., symbol) is then sent to wireless receiver 503 via a wireless medium (e.g., via channel 512).

[0095] At the wireless receiver 503, the signal 511 is received by a bit-by-bit log-likelihood ratio (LLR) demapper component 514 to demap the symbols of the signal 511. The demapped symbols are received by an FEC decoder 516 and then by a bits-to-amplitude component 518 to decode the bits. The decoded bits are provided to an amplitude deshaper 520 to (e.g., evenly) distribute the received bits, which can then be transmitted to their destination.

[0096] The amplitude shaper 504 may also be referred to as a distribution matcher or a specific implementation of a distribution matcher. In some aspects, the distribution matcher includes a decompressor (e.g., a decoder) to convert an information bit sequence (u) into a symbol set. The information bit sequence (u) may be uniformly distributed. In an example, in 5G NR, the information bit sequence may be uniformly distributed. The decompressor may generate a symbol sequence based on a target probability mass function (PMF) (such as a Maxwell-Boltzmann distribution) and a symbol block length (n). The symbol sequence may be sent to a receiver for processing to determine the information sent.

[0097] The distribution matcher may also include a compressor (eg, an encoder) to convert the symbol set into a compressed information bit sequence In a fixed-to-fixed scheme, the distribution matcher may include a comparator to compare the information bit sequence (u) with the compressed information bit sequence Comparison is made to determine how many information bits have not been converted into a symbol set. In some examples, the distribution matcher can provide the output of the comparator to the receiver so that the receiver can determine how to process the symbol set. For example, based on a compressor at the receiver, the receiver can compress the symbol set to generate information bits based on the target PMF, which can result in additional bits. The receiver can use the output of the comparator (e.g., discard signaling) to determine how many bits to discard.

[0098] Alternatively, the distribution matcher can adopt a variable to fixed scheme, in which the decompressor is configured with a "backoff" limit. The backoff limit can limit the amount of information bits that the decompressor can convert into a symbol set so that no extra bits are sent to the receiver for discarding. In addition, the variable to fixed scheme can limit the amount of overhead (e.g., compared to the fixed to fixed scheme) because no comparator is required, and therefore the distribution matcher can forgo sending discard signaling with information about the number of bits to be discarded at the receiver. In such examples, when the variable to fixed scheme is adopted, the rate loss compared to the target entropy can be improved compared to when the fixed to fixed scheme is adopted.

[0099] Example amplitude shaper and amplitude deshaper that can be changed into a fixed scheme

[0100] Fig. 6AAn example of an amplitude shaper 602 that may be used in an independent and identically distributed (IID) variable to fixed distribution matching scheme is illustrated.

[0101] As shown, the amplitude shaper 602 can be implemented using an arithmetic decoder 610. The arithmetic decoder 610 can be configured to take a block of k information bits and generate a sequence of shaped symbols. The arithmetic decoder can be configured to select a symbol from a symbol alphabet (e.g., including numeric values, such as integers) The above reaches a fixed entropy H p The target distribution p. Parameters and η may be predetermined, and:

[0102]

[0103] The arithmetic decoder can be implemented using the following mapping function:

[0104]

[0105] Length is Each symbol sequence can be related to the interval Associated so that Pr({s}) = b s -a s And all such intervals are disjoint. For a value u∈[0,1), if and only if u∈[a s , b s )hour, For example, with integer representation x=∑ i x i 2 i The k information bits (x K-1 , ..., x1, x0) can be encoded as Figure 8 Example symbol sequences, corresponding intervals, and binary representations are shown in .

[0106] like Figure 6B As shown, the amplitude deshaper 604 may be implemented using an arithmetic encoder 620, which may perform the reverse order of the processing of the amplitude shaper 602. For example, the arithmetic encoder 620 may employ The sequence of symbols determines the number of information bits.

[0107] The arithmetic encoder can use the mapping To achieve this. For a length of For every symbol sequence s, whenever When it holds, the entire set of K integers [x′:x′+K)={x′, x′+1, ..., x′+K-1} can be mapped Encoded as s, where x′ is an integer representation of a block of k information bits, where the integer K is:

[0108] or

[0109]

[0110] The symbol sequence s, if received correctly, corresponds to It depends on the mapping The arithmetic encoder can be used To determine the quantity as the number of common prefixes of all binary representations of integers in [x′:x′+K). These common prefixes can be used to carry the k-bit Bit. Figure 8 It is shown in Examples of common prefixes.

[0111] Fig. 7A An example amplitude shaper 702 is illustrated, which includes two modules: an arithmetic decoder 710 and an arithmetic encoder 720. The arithmetic decoder 710 may follow IId variable to fixed distribution matching, similar to the arithmetic decoder 610 shown in FIG6. For example, the fine-tuning arithmetic decoder 710 may take k information bits as input and generate A sequence of integer symbols.

[0112] The sequence of integer symbols may also be input to the arithmetic encoder 720. The arithmetic encoder 720 may follow IId variable to fixed distribution matching, similar to the arithmetic encoder 620 shown in FIG6, and may be used to efficiently compute the binary representation of all integers in [x′: x′+K). common prefix.

[0113] In some aspects, the bits that belong to the original k information bits but are not the common prefix The bit is held in the amplitude shaper 710 and combined with the additional information bits are combined for the next transmission.

[0114] like Figure 7B As shown, the amplitude deshaper 704 can be implemented using the same arithmetic encoder 720 as the amplitude shaper 702. Therefore, The sequence of shaped symbols may also be input to the fine-tuned arithmetic encoder 720 to recover The remaining common prefixes are not common prefixes. Bits may be discarded at the amplitude deshaper 704 .

[0115] use Fig. 7A and Figure 7B A potential problem with the amplitude shaper and amplitude deshaper shown in is that for some symbol sequences there may be no common prefix In such cases, the amplitude deshaper may not be able to uniquely determine a single bit among the k information bits.

[0116] An example of this is in Figure 8 , which shows the common prefixes for the binary representation of integers in [x′: x′+K), assuming the following parameter set: p(1) = 0.6, p(3) = 0.4, H p =0.673, η=1,

[0117] The first row of the table is the header, where each column of the header defines the variables in the following rows. For example, the first column of the table shows a length of The second column shows the symbol sequence s. FIG. 6A to FIG. 6B The third column shows the disjoint intervals described in FIG. 6A to FIG. 6B The set of K integers (also called K binary numbers) with the standard binary representation described in , where the particular integer in the set depends on the base symbol sequence s, and the fourth column shows the corresponding common prefixes.

[0118] For example, if the symbol sequence s=111, the arithmetic encoder can generate a set of K binary numbers, which can be found in the third column of the second row. All K integers generated based on the symbol sequence s=111 share the same two most significant bits, shown as two leading zeros in bold. The arithmetic encoder can determine The common prefix is ​​two leading zeros 00, and

[0119] In the illustrated example, the arithmetic encoder can determine at least some common prefixes of the other symbol sequences except the symbol sequence s=131. The symbol sequence s=131 is an example sequence for which the arithmetic encoder cannot determine a common prefix, as shown in the fourth row of table 800. Because there is no shared leading bit among the K binary numbers, there is no common prefix Such sequences may pose a challenge to arithmetic coders because it is not possible to utilize (eg, execute) information bits from such sequences.

[0120] Example Gray Decoding for Variable to Fixed Distribution Matching

[0121] However, aspects of the present disclosure can help avoid scenarios where there is no common prefix by introducing Gray mapping for variable to fixed distribution matching in the PAS architecture. As will be described in more detail below, utilizing Gray mapping can help ensure that there are at least some common locations that do not differ, thereby increasing the number of information bits that may be successfully received at the receiver and reducing the total number of transmissions required to convey k information bits. Details on determining locations with differences can be found below in Fig. 9B turn up.

[0122] Fig. 9A An example amplitude shaper 902 is illustrated, which includes a Gray demapper 910 followed by an arithmetic decoder 920. Similarly, Fig. 9B An example amplitude deshaper 904 is illustrated, which includes a Gray mapper 940 after the arithmetic encoder 930.

[0123] Fig. 9A The amplitude reshaper of may take as input a k-bit information sequence having an integer representation v. The Gray demapper may form an integer x, where x = Ψ -1 (y). The arithmetic decoder can form a length of The symbol sequence The symbol sequence s is the output of the amplitude shaper.

[0124] For integer y∈[0:2 k ), the binary representation can be (y K-1 , ..., y1, y0).

[0125] Inverse Gray Map Ψ -1 :[0:2 k )→[0:2 k ) can be obtained by setting x = Ψ -1 (y), where an integer x has a binary representation (x K-1 , ..., x1, x0). For each position index i∈{0, 1, ..., k-1), in In the case of the upper summation, x i =y i +y i+1 +…+y k-1 It may be true. -1 The definition of Ψ can be obtained by applying Ψ point by point -1 And expand to [0:2 k ).

[0126] For simplicity, in the following discussion, an integer x is considered to be a binary representation (x K-1 , ..., x1, x0), while the integer y is treated as a binary representation (y K-1, ..., y1, y0). In other words, the Gray mapping Ψ and the inverse Gray mapping Ψ -1 can be directly applied to binary representations. For example, following the above definition, (y K-1 , ..., y1, y0) = Ψ((x K-1 , ..., x1, x0)), while (x K-1 , ..., x1, x0) = Ψ -1 ((y K-1 , ..., y1, y0)).

[0127] In the example, using Figure 8 The introduced parameter, integer y=21 is the input to the amplitude reshaper 902. The binary representation of integer y is the information sequence (0, 1, 0, 1, 0, 1). Gray demapper 910 forms x=Ψ -1 (y)=25, where x is a binary representation of the Gray demapped information bit sequence as (0, 1, 1, 0, 0, 1), and the number (eg, length or size) of information bits k is 6. In this example, the arithmetic decoder 920 forms a symbol sequence for transmission like Fig. 9B As shown, the amplitude deshaper 904 may include an arithmetic encoder 930 and a Gray mapper 940. The symbol sequence s (eg, the output of the amplitude shaper 902) may be an input to the amplitude deshaper 904. The arithmetic encoder 930 may take the symbol sequence s as input and determine based on the symbol sequence s

[0128] Gray mapper 940 may determine the set of all difference positions of the set Ψ([x′:x′+K)) This set is the set of all Gray-coded K numbers.

[0129] For any set of integers A position index i∈{0, 1, ..., k-1} can be considered as a differential position in S if and only if there are u and v in S such that, under the binary representation of u and v, u i ≠v i In other words, if the binary representations of any two integers in S have different bits at a given position index, then that position index is a difference position in S.

[0130] Gray mapper 940 can select any y∈Ψ([x′:x′+K)) and output all bits y i ,in The cardinality of , which represents the number of bits that are sent indifferently. The positions are used to carry k information bits. information bits.

[0131] In the example, using Figure 8 The introduced parameters, symbol sequence s = (1, 3, 1) is the input to the amplitude deshaper 904. The arithmetic encoder 930 can generate Where the set of integers is [24:24+9)={24, 25, 26, 27, 28, 29, 30, 31, 32}. Gray mapper 940 can first generate an integer set Ψ([24:24+9)), which is {20, 21, 23, 22, 18, 19, 17, 16, 48}. For each y∈Ψ([24:24+9)), its binary representation (y5, y4, y3, y2, y1, y0) satisfies y4=1 and y3=0, so that the other position indexes are difference positions. Then, Gray mapper 940 can determine the set of all difference positions is {0, 1, 2, 5}. Similarly, the index set without different positions can be determined as {0, 1, 2, 3, 4, 5}\{0, 1, 2, 5}={3, 4}, and The 2 bits represented by the index {3, 4} are (1, 0), with the least significant bit as the rightmost bit. The sequence (1, 0) may be the output of the amplitude deshaper 904 .

[0132] Fig.10 Table 1000 of illustrates how Gray mapping can produce more common prefixes (non-differential positions) than the conventional PAS method. The parameters assumed for Table 1000 are as follows: a symbol alphabet with probability distributions p(1)=0.6 and p(0)=0.4 Symbol sequence length Entropy H p = 0.673 and the information sequence length k = 6. As described above, these non-differential positions are used to carry information bits for transmission, so Gray mapping can improve spectrum efficiency.

[0133] As shown, for the symbol sequence s=113, the number of indifferent common positions can increase from 1 to 2. As shown, for the symbol sequence s=131, the number of indifferent common positions can increase from 0 to 2.

[0134] Fig.111 illustrates how the Gray mapping function can produce a non-differentiated position {3, 4}. As shown, before Gray mapping, the binary representation set 1100 lacks any bit positions with all the same values ​​(e.g., no common prefix). However, after Gray mapping, the binary representation set 1110 has two bit positions {3, 4} that have common values ​​(0 and 1, respectively), making the position {3, 4} an indifferent common position.

[0135] Can be used in variable to fixed distribution matching schemes Fig.10 Table 1000 is used to identify the number of information bits that may be successfully received at the receiver (by simulating receiver-side processing at the transmitter) in order to avoid sending additional bits that may be discarded at the receiver.

[0136] For example, as will be described in more detail below, table 1000 may allow an amplitude shaper on the transmitter side and an amplitude deshaper on the receiver side to know which bits have non-differential positions (non-differential bits, which represent transmitted information bits) and which bits are differential bits based on the shaped symbol sequence. This information allows the transmitter to know how to update the transmit (Tx) buffer (and what bits need to be retransmitted) and when the transmit buffer can be cleared (after all bits are transmitted as non-differential bit positions). This information allows the receiver to know when the entire block of information bits has been successfully received so that the block can be delivered from the receive (Rx) buffer and those bits can be discarded from the Rx buffer.

[0137] Fig.12 An example amplitude shaper 1202 is illustrated that is configured to perform variable to fixed distribution matching enhanced with Gray mapping to efficiently transmit information bits to a receiver with an amplitude deshaper 1204 .

[0138] As shown, the amplitude shaper 1202 may include a transmit (Tx) buffer 1205 , a Gray demapper 1210 , an arithmetic decoder 1220 , an arithmetic encoder 1230 , and a Gray mapper 1240 .

[0139] The Tx buffer 1205 may be a buffer that receives and stores blocks of information bits for transmission (each block is of size k). The Tx buffer stores the current block and all unprocessed blocks. The Tx buffer 1205 may deliver blocks of k information bits (e.g., Gray-decoded information bits that may be referred to herein as "normal information bits") to the Gray demapper 1210. The blocks of k information bits correspond to an integer y. The Gray demapper 1210 may perform an inverse Gray mapping of y to generate k information bits corresponding to an integer x, which may be used by the arithmetic decoder 1220 to generate a sequence of integer symbols for transmission. As described above with reference to Fig.10As described in Table 1000, each shaped symbol sequence may have a corresponding number of non-differential bit positions It represents the information bits conveyed by this particular sequence of shaped symbols.

[0140] As shown, the arithmetic encoder 1230 and the Gray mapper 1240 may use the first shaping symbol sequence S to determine (eg, based on Fig.10 Table 1000) has a set of different locations Gray mapping sequence. This information can be used to effectively provide information about the current block that needs to be retransmitted. Feedback information of the bit.

[0141] The output from the Gray mapper 1240 may be provided to the Tx buffer 1205 as feedback for the current block. Thus, the Tx buffer 1205 may maintain the current block. All corresponding bits, and discard the index set corresponding to the current block with no difference position In other words, after sending, the current block is Corresponding The bits may be determined to be unsuccessfully delivered and may be retained in the Tx buffer 1205 for use in the next transmission.

[0142] Without changing the order (for example, making The corresponding least significant bit is reserved as the rightmost bit), and the Tx buffer 1205 converts the feedback The corresponding current block The first bit of the next block bit combination (for example, the first bits are appended to the current block bits) to form a new current block of k information bits. This new current block of k information bits can be a new input to Gray demapper 1210. In some examples, such as Fig. 13C As shown, if there are not enough bits remaining in the Tx buffer 1205 to form a new current block of k information bits, zero padding may be used.

[0143] As shown, the amplitude deshaper 1204 may include an arithmetic encoder 1230, a Gray mapper 1240, and an Rx buffer 1250. In some examples, the arithmetic encoder 1230 is the same as or similar to the arithmetic encoder 930, and the Gray mapper 1240 is the same as the Rx buffer 1250. Fig. 9B Gray mapper 940 is shown to be the same or similar.

[0144] The amplitude deshaper 1204 may receive (via a wireless channel) a shaped symbol sequence generated by the arithmetic decoder 1220. The arithmetic encoder 1230 and the Gray mapper 1240 may take the shaped symbol sequence as input to determine (e.g., based on Fig.11 Table 1100) has a difference position set The Gray mapping sequence of , as discussed above.

[0145] The Rx buffer 1250 may be initialized by reading a first block of k values ​​from the Gray mapper 1240. The Rx buffer 1250 may record the indices of all undetermined values ​​in the Rx buffer 1250 (eg, corresponding to the difference positions).

[0146] Upon receiving the new block B from the Gray mapper 1240, the Rx buffer 1250 may first define the integer m as the minimum of k and the number of undetermined values ​​(e.g., the same cardinality as the difference positions) in the Rx buffer 1250. For example, the new block B may be the same as the first subset of the first information bit block and the second information bit block combined, as discussed above.

[0147] Then, Rx buffer 1250 can read the first m elements from new block B and replace the first m undetermined values ​​in Rx buffer 1250 with these m values ​​from block B without changing the order. For example, the least significant bit of the first m elements is assigned to the least significant bit of the undetermined value.

[0148] Rx buffer 1250 may then append the remaining km elements from block B to the end of Rx buffer 1250. Rx buffer 1250 may then determine for the first k elements in Rx buffer 1250 whether all of these elements have determined values, and deliver these k elements and then discard them. Rx buffer 1250 may update the index corresponding to the undetermined value in Rx buffer 1250.

[0149] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D Describes the use of Gray mapping combined with Fig.12 An example of iterative transmission processing for a transmitter and a receiver in the amplitude shaper and amplitude deshaper shown in FIG. Fig.10 The same parameters as those assumed in Table 1000: a symbol alphabet with probability distributions p(1)=0.6 and p(0)=0.4 Symbol sequence length Entropy Hp = 0.673 and information sequence length k = 6. These figures show the order of processing steps performed at the amplitude shaper (e.g., steps 1-5) and processing steps performed at the amplitude deshaper (e.g., steps 6-7), but the operations performed at different entities may be performed simultaneously.

[0150] Fig.13A The process of processing the initial transmission by the amplitude reshaper 1202 and the amplitude deshaper 1204 is illustrated. As shown, two information bit blocks (1, 0, 0, 0, 1, 1) and (1, 0, 1, 1, 0, 1) are available for transmission. These information bit blocks can be concatenated and stored in the Tx buffer, such as (1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1).

[0151] like Fig.13A As shown, for the first transmission at the amplitude shaper, a first block of k information bits (1, 0, 0, 0, 1, 1) may be provided to a Gray demapper 1210, which performs an inverse Gray mapping to produce information bits (1, 1, 1, 1, 0, 1). An arithmetic decoder 1220 may take the block of bits as input and generate a first shaped symbol sequence (3, 3, 3) for transmission.

[0152] After being processed by the arithmetic encoder 1230, the Gray mapper 1240 (e.g., using Fig.10 The table 1000 of FIG. 1000 determines the set of difference positions as {0, 1} and feeds the set back to the Tx buffer. As shown in Table 1000, this means that (1, 0, 0, 0, ?, ?) is a "gray mapping" sequence. Based on this, the Tx buffer can be updated to (1, 1, 1, 0, 1, 1, 0, 1). This is because the first 4 elements in the original Tx buffer (1, 0, 0, 0, 1, 1, 1, 0, 1, 1) are sent indifferently and discarded because they correspond to the (non-difference position) information bits conveyed in the shaping symbol (3, 3, 3).

[0153] At the amplitude deshaper 1204, a symbol sequence (3, 3, 3) is received. After being processed by the arithmetic encoder, the Gray mapper determines the set of difference positions to be {0, 1}, because the "Gray mapping" sequence is (1, 0, 0, 0, ?, ?). Based on this, the Rx buffer can be initialized to (1, 0, 0, 0, ?, ?), and the Rx buffer can hold {0, 1] as the set of difference positions.

[0154] like Fig. 13BAs shown, after the first transmission, the Tx buffer stores (1, 1, 1, 0, 1, 1, 0, 1), and the first 2 bits of the stored information bit sequence (e.g., (1, 1)) are the bits with differences in the first information bit block (4 bits of the first block have been delivered).

[0155] For the second transmission at the amplitude shaper, the Gray demapper takes the first k bits from the Tx buffer containing (1, 1, 1, 0, 1, 1, 0, 1) and forms Ψ -1 (1, 1, 1, 0, 1, 1) = (1, 0, 1, 1, 0, 1) The arithmetic decoder 1220 may take the block of bits as input and generate a second shaped symbol sequence (3, 1, 1) for transmission.

[0156] After being processed by the arithmetic encoder 1230, the Gray mapper 1240 (e.g., using Fig.10 The set of difference positions is determined as {0, 1, 2, 3} and fed back to the Tx buffer. As shown in Table 1000, this means that (1, 1, ?, ?, ?, ?) is a "gray mapping" sequence. Based on this, the Tx buffer can be updated to (1, 0, 1, 1, 0, 1). The first 2 elements in the original Tx buffer (1, 1, 1, 0, 1, 1, 0, 1) are sent without difference and are discarded (because the entire first original block has been sent).

[0157] At the amplitude deshaper 1204, a symbol sequence (3, 1, 1) is received. After processing by the arithmetic encoder, the Gray mapper determines the set of difference positions to be {0, 1, 2, 3}, since the "Gray mapped" sequence is (1, 1, ?, ?, ?, ?). Based on this, the Rx buffer can be updated to (?, ?, ?, ?), since the first 6 bits are determined and can be delivered (and discarded from the Rx buffer).

[0158] like Fig. 13C As shown, after the second transmission, the Tx buffer stores (1, 0, 1, 1, 0, 1), i.e., the original second information bit block, because all bits of the original first information bit block have been delivered.

[0159] For the third transmission at the amplitude shaper, the Gray demapper takes the first k bits from the Tx buffer containing (1, 0, 1, 1, 0, 1) and forms Ψ -1 (1, 0, 1, 1, 0, 1) = (1, 1, 0, 1, 1, 0). The arithmetic decoder 1220 may take the block of bits as input and generate a third shaped symbol sequence (3, 3, 1) for transmission.

[0160] After being processed by the arithmetic encoder 1230, the Gray mapper 1240 (e.g., using Fig.10 The table 1000 of FIG. 1000 determines the set of difference positions as {0, 1, 3} and feeds the set back to the Tx buffer. As shown in Table 1000, this means that (1, 0, ?, 1, ?, ?) is a "gray mapping" sequence. Based on this, the Tx buffer can be updated to (1, 0, 1, 0, 0, 0) with 3 zero padding bits. This is because the elements indexed as {2, 4, 5} in the original Tx buffer (1, 0, 1, 1, 0, 1) are discarded.

[0161] At the amplitude deshaper 1204, a symbol sequence (3, 3, 1) is received. After being processed by the arithmetic encoder, the Gray mapper determines the set of difference positions as {0, 1, 3}, because the "Gray mapping" sequence is (1, 0, ?, 1, ?, ?). Based on this, the Rx buffer can be updated to (1, 0, ?, 1, ?, ?). This is because the amplitude deshaper replaces the 4 undetermined values ​​in the original Rx buffer (?, ?, ?, ?) with the first 4 elements from the "Gray mapping" sequence (1, 0, ?, 1, ?, ?), and appends the remaining 2 elements (?, ?) of the "Gray mapping" sequence to the end of the Rx buffer, so that the Rx buffer becomes (1, 0, ?, 1, ?, ?).

[0162] like Fig.13D As shown, after the third transmission, the Tx buffer stores (1, 0, 1, 0, 0, 0), and 3 bits of the second information bit block have been delivered.

[0163] For the fourth transmission at the amplitude shaper, the Gray demapper takes the first k bits from the Tx buffer containing (1, 0, 1, 0, 0, 0) and forms Ψ -1 (1, 0, 1, 0, 0, 0) = (1, 1, 0, 0, 0, 0) The arithmetic decoder 1220 may take this block of bits as input and generate a fourth shaped symbol sequence (3, 1, 3) for transmission.

[0164] After being processed by the arithmetic encoder 1230, the Gray mapper 1240 (e.g., using Fig.10 The set of difference positions is determined as {0, 1, 2} by the table 1000 of FIG. 1000 , and the set is fed back to the Tx buffer. As shown in the table 1000 , this means that (1, 0, 1, ?, ?, ?) is a "gray mapping" sequence. Based on this, the Tx buffer can be updated to 0 (cleared / reset) because the two original blocks have been sent.

[0165] At the amplitude deshaper 1204, a symbol sequence (3, 1, 3) is received. After being processed by the arithmetic encoder, the Gray mapper determines the set of difference positions to be {0, 1, 2}, because the "Gray mapping" sequence is (1, 0, 1, ?, ?, ?). Based on this, the amplitude deshaper can replace the 3 undetermined values ​​in the original Rx buffer (1, 0, ?, 1, ?, ?) with the first 3 elements from the "Gray mapping" sequence (1, 0, 1, ?, ?, ?). The amplitude deshaper can also append the remaining 3 elements of the "Gray mapping" sequence (?, ?, ?) to the end of the Rx buffer, so that the value stored in the Rx buffer becomes.

[0166] Since the first 6 elements of the Rx buffer are all determined, they are delivered and then discarded. Since this is the second raw information bit block from the Tx buffer, this corresponds to the end of information transmission.

[0167] Example Operation of the Transmitter

[0168] Fig.14 An example of a method 1400 for wireless communication by a transmitter is shown. In some aspects, the transmitter is a UE, such as Figure 1 and Figure 3 UE 104. In some aspects, the transmitter is a network entity such as Figure 1 and Figure 3 BS102 or such Figure 2 The decomposed base station in question.

[0169] Method 1400 begins at step 1405 by obtaining a first information bit block from a buffer. In some cases, the operation of this step refers to the operation of Fig.16 The described circuit for obtaining and / or the code for obtaining, or can be executed by the circuit and / or the code.

[0170] Method 1400 then proceeds to step 1410, generating a first probability amplitude shaping (PAS) symbol sequence from the first information bit block using a demapper function and an arithmetic decoder function. In some cases, the operation of this step is referred to as reference Fig.16 The described circuit for generating and / or code for generating, or can be executed by the circuit and / or the code.

[0171] Method 1400 then proceeds to step 1415, where the first PAS symbol sequence is sent to the receiver. In some cases, the operation of this step is referred to as in reference to Fig.16 The described circuits for transmitting and / or codes for transmitting, or executable by the circuits and / or the codes.

[0172] Method 1400 then proceeds to step 1420, combining the first subset of the first information bit block identified by the arithmetic encoder function and the mapper function with the second information bit block from the buffer. In some cases, the operation of this step refers to the operation of Fig.16 The described circuits for combining and / or codes for combining may be executed by the circuits and / or the codes.

[0173] Method 1400 then proceeds to step 1425, generating a second PAS symbol sequence from the combined first subset of the first information bit block and the second information bit block using a demapper function and an arithmetic decoder function. In some cases, the operation of this step refers to as described in reference Fig.16 The described circuits for transmitting and / or codes for transmitting, or executable by the circuits and / or the codes.

[0174] Method 1400 then proceeds to step 1430, where a second PAS symbol sequence is sent to the receiver. In some cases, the operation of this step is referred to as in reference to Fig.16 The described circuits for transmitting and / or codes for transmitting, or executable by the circuits and / or the codes.

[0175] In one aspect, method 1400 or any aspect related thereto may be performed by an apparatus such as Fig.16 The method 1400 is performed by a communication device 1600 that includes various components operable, configured, or adapted to perform the method 1400. The communication device 1600 is described in more detail below.

[0176] Please note that Fig.14 This is merely one example of a method, and other methods including fewer, additional, or alternative steps may also be consistent with the present disclosure.

[0177] Example Operation of Receiver

[0178] Fig.15 An example of a method 1500 for wireless communication by a receiver is shown. In some aspects, the receiver is a UE, such as Figure 1 and Figure 3 UE 104. In some aspects, the receiver is a network entity such as Figure 1 and Figure 3 BS102 or such Figure 2 The decomposed base station in question.

[0179] Method 1500 begins at step 1505 by receiving a first probability amplitude shaping (PAS) symbol sequence generated based on a first information bit block from a transmitter. In some cases, the operation of this step refers to the same as in reference to Fig.17The described circuits for receiving and / or codes for receiving may be or may be executed by the circuits and / or codes.

[0180] Method 1500 then proceeds to step 1510, using the arithmetic encoder function and the mapper function to identify a first subset of the first information bit block. In some cases, the operation of this step refers to the operation of Fig.17 The described circuit for identifying and / or code for identifying may be executed by the circuit and / or the code.

[0181] Method 1500 then proceeds to step 1515, storing a second subset of the first information bit block in a buffer using the arithmetic encoder function and the mapper function, wherein the second subset includes a remaining set of the first information bit block after discarding the first subset. In some cases, the operation of this step refers to as described in reference to Fig.17 The described circuit for storing and / or code for storing, or can be executed by the circuit and / or the code.

[0182] Method 1500 begins at step 1520 by receiving a second PAS symbol sequence generated by combining a first subset of a first information bit block with a second information bit block. In some cases, the operation of this step refers to the operation of Fig.17 The described circuits for receiving and / or codes for receiving may be or may be executed by the circuits and / or codes.

[0183] Method 1500 begins at step 1525 by updating a buffer based on a first subset of a combination of a block of second information bits and a subset of a block of second information bits identified using an arithmetic encoder function and a mapper function. In some cases, the operation of this step refers to the operation of Fig.17 The described circuit for updating and / or code for updating may be executed by the circuit and / or the code.

[0184] In one aspect, method 1500 or any aspect related thereto may be performed by an apparatus such as Fig.17 The method 1500 is performed by a communication device 1700 that includes various components operable, configured, or adapted to perform the method 1500. The communication device 1700 is described in more detail below.

[0185] Please note that Fig.15 This is merely one example of a method, and other methods including fewer, additional, or alternative steps may also be consistent with the present disclosure.

[0186] Example Transmitter Device

[0187] Fig.16Depicted are aspects of an example communication device 1600. In some examples, the communication device 1600 is a user equipment, such as described above with respect to Figure 1 and Figure 3 UE 104 is described. In some aspects, the communication device 1600 is a network entity such as Figure 1 and Figure 3 BS 102 or such Figure 2 The decomposed base station in question.

[0188] The communication device 1600 includes a processing system 1605 coupled to a transceiver 1665 (e.g., a transmitter and / or a receiver). In some aspects (e.g., when the communication device 1600 is a network entity), the processing system 1605 can be coupled to a network interface 1675 that is configured to communicate with the communication device 1600 via a communication link (such as, for example, as described herein with respect to Figure 2 The processing system 1605 may be configured to perform processing functions of the communication device 1600, including processing signals received and / or to be transmitted by the communication device 1600.

[0189] The processing system 1605 includes one or more processors 1610. In various aspects, such as with respect to Figure 3 As depicted, the one or more processors 1610 may represent one or more of the receive processor 358, the transmit processor 364, the TX MIMO processor 366, and / or the controller / processor 380. In various aspects, as described with respect to Figure 3 As described, the one or more processors 1610 may represent one or more of the receive processor 338, the transmit processor 320, the TX MIMO processor 330, and / or the controller / processor 340. The one or more processors 1610 are coupled to the computer-readable medium / memory 1635 via the bus 1660. In some aspects, the computer-readable medium / memory 1635 is configured to store instructions (e.g., computer-executable code) that, when executed by the one or more processors 1610, cause the one or more processors 1610 to perform operations related to the processing of the data transmission. Fig.14 The described method 1400 or any aspect related thereto. Note that references to a processor performing a function of the communication device 1600 may include one or more processors 1610 performing that function of the communication device 1600 .

[0190] In the depicted example, computer readable medium / memory 1635 stores code (e.g., executable instructions) such as code for obtaining 1640, code for generating 1645, code for combining 1650, and code for transmitting 1655. Processing of code for obtaining 1640, code for generating 1645, code for combining 1650, and code for transmitting 1655 may enable communication device 1600 to perform operations related to Fig.14 The described method 1400 or any aspect related thereto.

[0191] The one or more processors 1610 include circuits configured to implement (e.g., execute) code stored in the computer-readable medium / memory 1635, including circuits such as circuits for obtaining 1615, circuits for generating 1620, circuits for combining 1625, and circuits for transmitting 1630. Processing using the circuits for obtaining 1615, generating 1620, combining 1625, and transmitting 1630 may enable the communication device 1600 to perform operations related to Fig.14 The described method 1400 or any aspect related thereto.

[0192] The various components of the communication device 1600 may provide for performing Fig.14 The components of the described method 1400 or any aspect related thereto. For example, the components for sending, transmitting, or outputting for sending may include Figure 3 The transceiver 354 and / or antenna 352 of the UE 104 are shown. Figure 3 The transceiver 332 and / or antenna 334 of BS 102, and / or Fig.16 The transceiver 1665 and antenna 1670 of the communication device 1600 in FIG. 1 may include Figure 3 The transceiver 354 and / or antenna 352 of the UE 104 are shown. Figure 3 The transceiver 332 and / or antenna 334 of BS 102, and / or Fig.16 The transceiver 1665 and antenna 1670 of the communication device 1600 in FIG.

[0193] Example Receiver Device

[0194] Fig.17 Depicted are aspects of an example communications device 1700. In some examples, communications device 1700 is user equipment, such as described above with respect to Figure 1 and Figure 3 UE 104 is described. In some aspects, communication device 1700 is a network entity such as Figure 1 and Figure 3BS 102 or such Figure 2 The decomposed base station in question.

[0195] The communication device 1700 includes a processing system 1705 coupled to a transceiver 1755 (e.g., a transmitter and / or a receiver). In some aspects (e.g., when the communication device 1700 is a network entity), the processing system 1705 can be coupled to a network interface 1765 that is configured to communicate with the communication device 1700 via a communication link (such as, for example, as described herein with respect to Figure 2 The processing system 1705 may be configured to perform processing functions of the communication device 1700, including processing signals received and / or to be transmitted by the communication device 1700.

[0196] The processing system 1705 includes one or more processors 1710. In various aspects, such as with respect to Figure 3 As depicted, the one or more processors 1710 may represent one or more of the receive processor 358, the transmit processor 364, the TX MIMO processor 366, and / or the controller / processor 380. In various aspects, as described with respect to Figure 3 As described, the one or more processors 1710 may represent one or more of the receive processor 338, the transmit processor 320, the TX MIMO processor 330, and / or the controller / processor 340. The one or more processors 1710 are coupled to the computer-readable medium / memory 1730 via the bus 1750. In some aspects, the computer-readable medium / memory 1730 is configured to store instructions (e.g., computer-executable code) that, when executed by the one or more processors 1710, cause the one or more processors 1710 to perform operations related to the processing of the data transmission. Fig.15 The described method 1500 or any aspect related thereto. Note that references to a processor performing a function of the communication device 1700 may include one or more processors 1710 performing that function of the communication device 1700 .

[0197] In the depicted example, computer readable medium / memory 1735 stores code (e.g., executable instructions) such as code for receiving 1740, code for identifying 1745, code for storing 1750, and code for updating 1755. Processing of code for receiving 1740, code for identifying 1745, code for storing 1750, and code for updating 1755 may enable communication device 1700 to perform operations related to Fig.15 The described method 1500 or any aspect related thereto.

[0198] The one or more processors 1710 include circuits configured to implement (e.g., execute) code stored in the computer-readable medium / memory 1730, including circuits such as circuits for receiving 1715, circuits for identifying 1720, circuits for storing 1725, and circuits for updating 1730. Processing using the circuits for receiving 1715, the circuits for identifying 1720, the circuits for storing 1725, and the circuits for updating 1730 may enable the communication device 1700 to perform operations related to Fig.15 The described method 1500 or any aspect related thereto.

[0199] The various components of the communication device 1700 may be provided for performing Fig.15 The components of the described method 1500 or any aspect thereof. For example, the components for sending, transmitting, or outputting for sending may include Figure 3 The transceiver 354 and / or antenna 352 of the UE 104 are shown. Figure 3 The transceiver 332 and / or antenna 334 of BS 102, and / or Fig.17 The transceiver 1755 and antenna 1760 of the communication device 1700 in FIG. 1 may include Figure 3 The transceiver 354 and / or antenna 352 of the UE 104 are shown. Figure 3 The transceiver 332 and / or antenna 334 of BS 102, and / or Fig.17 The transceiver 1755 and antenna 1760 of the communication device 1700.

[0200] Sample Clauses

[0201] Specific implementation examples are described in the following numbered clauses:

[0202] Item 1: A method for wireless communication at a transmitter, comprising: obtaining a first block of information bits from a buffer; generating a first probability amplitude shaping (PAS) symbol sequence from the first block of information bits using a demapper function and an arithmetic decoder function; sending the first PAS symbol sequence to a receiver; combining a first subset of the first block of information bits identified by the arithmetic encoder function and the mapper function with a second block of information bits from the buffer; generating a second PAS symbol sequence from the combined first subset of the first block of information bits and the second block of information bits using the demapper function and the arithmetic decoder function; and sending the second PAS symbol sequence to the receiver.

[0203] Clause 2: The method of clause 1, wherein: the demapper function comprises a Gray demapper function that maps a set of normal information bits to a set of Gray demapped bits; and the mapper function comprises a Gray mapper function that maps a set of Gray demapped bits to a set of Gray mapped bits.

[0204] Clause 3: A method according to clause 2, wherein the first block of information bits represents a first integer, and generating the first PAS symbol sequence includes: forming a second integer from the first integer using the Gray demapper function; and forming the first PAS symbol sequence from the second integer using the arithmetic decoder.

[0205] Clause 4: The method according to Clause 3 also includes identifying a first subset of the first information bit block by the following steps: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder; and identifying a second subset of the first information bit block, the second subset corresponding to a plurality of bit positions having common values ​​of all binary representations of integers in the set of integers.

[0206] Clause 5: The method of clause 4, wherein the first subset corresponds to difference bit positions lacking a common value of all binary representations of the integer.

[0207] Clause 6: The method according to any one of clauses 1 to 5 further includes: combining a subset of the second information bit block identified by the arithmetic encoder function and the mapper function with a third information bit block; generating a third PAS symbol sequence from the first information bit block using the demapper function and the arithmetic decoder function; and sending the third PAS symbol sequence to the receiver.

[0208] Clause 7: A method for wireless communication at a receiver, comprising: receiving a first probability amplitude shaping (PAS) symbol sequence generated based on a first information bit block from a transmitter; identifying a first subset of the first information bit block using an arithmetic encoder function and a mapper function; storing a second subset of the first information bit block in a buffer using the arithmetic encoder function and the mapper function, wherein the second subset includes a remaining set of the first information bit block after discarding the first subset; receiving a second PAS symbol sequence generated by combining the first subset of the first information bit block with a second information bit block; and updating the buffer based on the combined first subset and the subset of the second information bit block identified using the arithmetic encoder function and the mapper function.

[0209] Clause 8: The method according to clause 7 further includes: using the arithmetic encoder function and the mapper function to determine a number of bits successfully received in the buffer; delivering the number of bits to another function of the receiver; and discarding the number of bits from the buffer.

[0210] Clause 9: A method according to any one of clauses 7 to 8, wherein: the mapper function comprises a Gray mapper function.

[0211] Clause 10: The method of clause 9, wherein: the first block of information bits represents a first integer; and the first PAS symbol sequence is generated based on a second integer formed from the first integer using a Gray demapper function.

[0212] Clause 11: The method according to clause 10 also includes identifying a first bit subset of the first information bit block by the following steps: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder; and identifying multiple bit positions having common values ​​of all binary representations of integers in the set of integers.

[0213] Clause 12: The method of clause 11, wherein the first subset corresponds to difference positions lacking a value common to all binary representations of the integer.

[0214] Clause 13: An apparatus comprising: a memory including executable instructions; and a processor configured to execute the executable instructions and cause the apparatus to perform the method according to any one of clauses 1 to 12.

[0215] Clause 14: An apparatus comprising: means for performing the method according to any one of clauses 1 to 12.

[0216] Clause 15: A non-transitory computer readable medium comprising: executable instructions that, when executed by a processor of an apparatus, cause the apparatus to perform the method of any one of clauses 1 to 12.

[0217] Clause 16: A computer program product embodied on a computer readable storage medium, comprising: code for performing the method according to any one of clauses 1 to 12.

[0218] Additional considerations

[0219] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein do not limit the scope, applicability or aspects set forth in the claims. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Various examples may omit, replace or add various processes or components as appropriate. For example, the described methods may be performed in a different order from the described order, and various actions may be added, omitted or combined. In addition, the features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structures and functionality other than the various aspects of the present disclosure set forth herein or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0220] The various illustrative logic blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Although a general purpose processor may be a microprocessor, in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, a system on a chip (SoC), or any other such configuration.

[0221] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0222] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, and the like. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Additionally, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0223] The method disclosed herein includes one or more actions for implementing the method. The method actions can be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions can be modified without departing from the scope of the claims. In addition, the various operations of the method described above can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors.

[0224] The following claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims. Within the claims, unless explicitly stated, reference to an element in the singular form is not intended to mean "one and only one", but "one or more". Unless otherwise specified, the term "some" refers to one or more. Any claim element is not interpreted according to the provisions of 35 USC § 112 (f) unless the element is explicitly stated using the phrase "parts for...". All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will be known later to a person of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, regardless of whether such disclosure is explicitly stated in the claims, anything disclosed herein is not intended to be disclosed to the public.

Claims

1. A method for wireless communication at a transmitter, comprising: Obtain a first information bit block from a buffer; generating a first probability amplitude shaping (PAS) symbol sequence from the first block of information bits using a demapper function and an arithmetic decoder function; sending the first PAS symbol sequence to a receiver; combining a first subset of the first block of information bits identified by the arithmetic encoder function and the mapper function with a second block of information bits from the buffer; generating a second PAS symbol sequence from the combined first subset of the first block of information bits and the second block of information bits using the demapper function and the arithmetic decoder function; as well as The second PAS symbol sequence is sent to the receiver.

2. The method according to claim 1, wherein: The demapper function comprises a Gray demapper function that maps a set of normal information bits to a set of Gray demapped bits; and The mapper function includes a Gray mapper function that maps a Gray demapped bit set to a Gray mapped bit set.

3. The method of claim 2, wherein the first block of information bits represents a first integer, and generating the first PAS symbol sequence comprises: forming a second integer from the first integer using the Gray demapper function; as well as The first PAS symbol sequence is formed from the second integer using the arithmetic decoder function.

4. The method according to claim 3, further comprising identifying a first bit subset of the first information bit block by: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder function; and A second subset of the first block of information bits is identified, the second subset corresponding to a plurality of bit positions having values ​​that are common to all binary representations of integers in the set of integers.

5. The method of claim 4, wherein the first subset corresponds to difference bit positions lacking a common value of all binary representations of the integer.

6. The method according to claim 1, further comprising: combining a subset of the second block of information bits identified by the arithmetic encoder function and the mapper function with a third block of information bits; generating a third PAS symbol sequence from the first block of information bits using the demapper function and the arithmetic decoder function; as well as The third PAS symbol sequence is sent to the receiver.

7. A method of wireless communication at a receiver, comprising: receiving, from a transmitter, a first probability amplitude shaping (PAS) symbol sequence generated based on a first information bit block; identifying a first subset of said first block of information bits using an arithmetic encoder function and a mapper function; storing a second subset of the first block of information bits in a buffer using the arithmetic encoder function and the mapper function, wherein the second subset comprises a remaining set of the first block of information bits after discarding the first subset; receiving a second PAS symbol sequence generated by combining the first subset of the first block of information bits with a second block of information bits; as well as The buffer is updated based on a first subset of combinations and a subset of second blocks of information bits identified using the arithmetic encoder function and the mapper function.

8. The method according to claim 7, further comprising: determining a number of bits successfully received into the buffer using the arithmetic encoder function and the mapper function; delivering the plurality of bits to another function of the receiver; and The plurality of bits are discarded from the buffer.

9. The method according to claim 7, wherein: The mapper function comprises a Gray mapper function.

10. The method according to claim 9, wherein: The first block of information bits represents a first integer; and The first PAS symbol sequence is generated based on a second integer formed from the first integer using a Gray demapper function.

11. The method according to claim 10, further comprising identifying a first bit subset of the first information bit block by: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder function; and A plurality of bit positions having values ​​common to all binary representations of integers in the set of integers are identified.

12. The method of claim 11, wherein the first subset of bits corresponds to difference positions lacking a common value for all binary representations of the integer.

13. An apparatus for wireless communication by a transmitter, comprising: Memory; as well as at least one processor coupled to the memory, wherein the memory includes instructions executable by the at least one processor to cause the transmitter to: Obtain a first information bit block from a buffer; generating a first probability amplitude shaping (PAS) symbol sequence from the first block of information bits using a demapper function and an arithmetic decoder function; sending the first PAS symbol sequence to a receiver; combining a first subset of the first block of information bits identified by the arithmetic encoder function and the mapper function with a second block of information bits from the buffer; generating a second PAS symbol sequence from the combined first subset of the first block of information bits and the second block of information bits using the demapper function and the arithmetic decoder function; and The second PAS symbol sequence is sent to the receiver.

14. The device according to claim 13, wherein: The demapper function comprises a Gray demapper function that maps a set of normal information bits to a set of Gray demapped bits; and The mapper function includes a Gray mapper function that maps a Gray demapped bit set to a Gray mapped bit set.

15. The apparatus of claim 14, wherein the first block of information bits represents a first integer, and generating the first PAS symbol sequence comprises: forming a second integer from the first integer using the Gray demapper function; as well as The first PAS symbol sequence is formed from the second integer using the arithmetic decoder function.

16. The apparatus of claim 15, wherein the memory further comprises instructions executable by the at least one processor to cause the transmitter to identify a first bit subset of the first information bit block by: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder function; and A second subset of the first block of information bits is identified, the second subset corresponding to a plurality of bit positions having values ​​that are common to all binary representations of integers in the set of integers.

17. The apparatus of claim 16, wherein the first subset of bits corresponds to difference bit positions lacking a common value of all binary representations of the integer.

18. The apparatus of claim 13, wherein the memory comprises instructions executable by the one or more processors to cause the transmitter to: combining a subset of the second block of information bits identified by the arithmetic encoder function and the mapper function with a third block of information bits; generating a third PAS symbol sequence from the first information bit block using the demapper function and the arithmetic decoder function; and The third PAS symbol sequence is sent to the receiver.

19. An apparatus for wireless communication by a receiver, comprising: Memory; as well as at least one processor coupled to the memory, wherein the memory includes instructions executable by the at least one processor to cause the receiver to: receiving, from a transmitter, a first probability amplitude shaping (PAS) symbol sequence generated based on a first information bit block; identifying a first subset of said first block of information bits using an arithmetic encoder function and a mapper function; storing a second subset of the first block of information bits in a buffer using the arithmetic encoder function and the mapper function, wherein the second subset comprises a remaining set of the first block of information bits after discarding the first subset; receiving a second PAS symbol sequence generated by combining the first subset of the first block of information bits with a second block of information bits; and The buffer is updated based on a first subset of combinations and a subset of second blocks of information bits identified using the arithmetic encoder function and the mapper function.

20. The apparatus of claim 19, wherein the memory further comprises instructions executable by the one or more processors to cause the receiver to: determining a number of bits successfully received into the buffer using the arithmetic encoder function and the mapper function; delivering the plurality of bits to another function of the receiver; and The plurality of bits are discarded from the buffer.

21. The apparatus of claim 19, wherein: The mapper function comprises a Gray mapper function.

22. The apparatus of claim 21, wherein: The first block of information bits represents a first integer; and The first PAS symbol sequence is generated based on a second integer formed from the first integer using a Gray demapper function.

23. The apparatus of claim 22, wherein the memory includes instructions executable by the at least one processor to cause the receiver to identify a first bit subset of the first block of information bits by: generating a set of integers from the first PAS symbol sequence using the arithmetic encoder function; and A plurality of bit positions having values ​​common to all binary representations of integers in the set of integers are identified.

24. The apparatus of claim 23, wherein the first subset corresponds to difference positions lacking a common value of all binary representations of the integer.

Images