Hardware-assisted page table management system and method, medium, program product and terminal

Abstract

The invention provides a hardware auxiliary page table management system and method, a medium, a program product and a terminal. Efficient address translation is achieved through cooperative work of a memory management unit and a memory unit. Comprising the key steps of conversion backup buffer hit detection, guest page table lookup, page traversal cache lookup and the like. After receiving the access instruction, the memory management unit executes detection through a conversion backup buffer hit detection module; and if not, a guest page table search module obtains a corresponding host physical address. And the system executes search in the page traversal cache module, accesses a second-level cache of the memory unit when necessary, and stores a search result into a cache line in a preset format. Transparent conversion of the client page table address in the cache is achieved in a hardware assisting mode, and a complete shadow page table item life cycle management scheme is provided.

Description

Technical Field

[0001] The present application relates to the field of computing processor architecture, and in particular to a hardware-assisted page table management system, method, medium, program product and terminal. Background Art

[0002] In modern virtualized environments, virtual machines (VMs) provide users with a secure sandbox environment by multiplexing on multiple hardware resources. As the cornerstone of cloud computing, virtualization technology achieves the separation of hardware and software and allows multiple operating systems and applications to run simultaneously on a single machine. This isolation significantly optimizes resource utilization, reduces costs, enhances system security, and enables large-scale services. However, virtualization is accompanied by a large amount of address translation overhead, which mainly comes from the sequential access of multi-level radix page tables. In the modern x86-64 architecture, the four-level page table divides the 48-bit virtual address into four segments and converts it to a physical address through sequential memory access. Although this method reduces the storage space of the page table, in a non-virtualized environment, a TLB (Translation Lookaside Buffer) miss may require up to four sequential memory accesses. In a virtualized environment, the page table is organized in a multi-level tree structure. The virtual address (gVA) of the guest operating system needs to be converted into a guest physical address (gPA) through the guest page table (gPT), and then the address is used as the virtual address (hVA) of the host operating system, and then converted into a host physical address (hPA) through the nested page table (nPT) to access the final data.

[0003] To solve these problems, the industry has widely adopted hardware-assisted virtualization technology, such as Intel's Extended Page Table (EPT) and AMD's Nested Page Table (NPT), which use hardware functions to cache address translation and reduce the complexity of nested page lookups. In addition, shadow page tables are maintained by the virtual machine monitor (VMM) or hypervisor to provide a direct mapping from virtual addresses to physical addresses for each virtual machine. Although shadow page tables reduce the need for page table lookups, virtual machine exits are required every time the client operating system updates the page table, resulting in significant performance overhead. Victima is an emerging technology that improves translation efficiency by utilizing underutilized L2 cache resources, using L2 cache lines to store evicted TLB entries, and providing additional low-latency, high-capacity fallback components to support the last-level TLB and reduce page table walk (PTW) overhead.

[0004] Although existing technical solutions have solved the address translation problem in virtualized environments to a certain extent, they each have their limitations. Although TLB and shadow page table technologies shorten the address translation time, their efficiency is limited under high load or large memory workloads. Shadow page tables impose a considerable burden on performance, especially due to frequent virtual machine exits. Although Victima uses L2 cache to improve TLB cache capacity, high cache utilization and potential performance saturation limit its practical application advantages. In addition, although hardware-assisted address translation reduces software pressure, the high latency of TLB misses and page table traversal remains a challenge under the increasing memory demand. The limitations of these technologies show that more innovative solutions are still needed to optimize address translation in virtualized environments to further improve efficiency and performance. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a hardware-assisted page table management system, method, medium, program product and terminal, which are used to solve the problem that the efficiency of address conversion is still limited under high load and large memory workload in the existing page table management technology, thereby affecting system performance and responsiveness.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a hardware-assisted page table management system, the system includes an MMU unit and a memory unit, the system includes: the MMU unit includes: a TLB hit detection module, a guest page table lookup module and a page traversal cache module; the memory unit includes: a first-level cache, a second-level cache; the interaction method of the system includes the following steps: the MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction, if the TLB does not hit, the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction; the MMU unit A page table lookup operation is performed in the page traversal cache module according to the host physical address; if the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request; the memory unit performs a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, the client page table entry obtained by the lookup is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module; the page traversal cache module sends the shadow page table entry to the guest page table lookup module, so that the guest page table lookup module performs a corresponding access operation based on the shadow page table entry.

[0007] In some embodiments of the first aspect of the present application, the cache line in the preset format includes: a tag, a status bit, multiple customer page table entries and a first shadow flag bit; each customer page table entry includes: a second shadow flag bit and a page number; wherein the first shadow flag bit includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a customer page table entry that is replaced by a shadow page table entry; the second flag is used to indicate that the current cache line does not contain a customer page table entry that is replaced by a shadow page table entry; the second shadow flag bit includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current customer page table entry has been replaced by a shadow page table entry; and the fourth flag is used to indicate that the current customer page table entry has not been replaced by a shadow page table entry.

[0008] In some embodiments of the first aspect of the present application, the process of storing the found customer page table entry in a cache line of a preset format includes: the secondary cache determines the second shadow flag in the current customer page table entry; if the second shadow flag is the fourth flag, the current customer page table entry is converted into a corresponding shadow page table entry through the nested page table addresser in the memory unit, and the second shadow flag is set to the third flag; the replaced customer page table entry is stored in the current cache line, and the first shadow flag of the current cache line is set to the first flag.

[0009] In some embodiments of the first aspect of the present application, the interaction method of the system includes one or more of the following steps: if the first-level cache misses and the second-level cache hits, and the second shadow flag bit of the customer page table item of the hit request is the fourth flag, then the customer page table item of the hit request is sent to the first-level data cache of the memory unit; if the first-level cache misses and the second-level cache hits, and the second shadow flag bit of the customer page table item of the hit request is the third flag, then other layers of cache structure or DRAM memory are requested to provide cache lines that do not contain shadow page table entries, and the cache lines that do not contain shadow page table entries are sent to the first-level data cache of the memory unit; if the first-level cache misses and the second-level cache misses, the MMU unit and the memory unit perform customer page table item consistency maintenance operations.

[0010] In some embodiments of the first aspect of the present application, the guest page table lookup module includes: a guest page table traverser and a first register; the first register includes a valid bit and a host physical address bit, wherein an initial state of the valid bit is an invalid state.

[0011] In some embodiments of the first aspect of the present application, the process in which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction includes: the first register is communicatively connected to the second register; the first register obtains the guest physical address from the second register based on the access instruction; the second register searches for the corresponding host physical address in the host page table traverser based on the guest physical address, and sends the host physical address back to the first register; the MMU unit stores the host physical address in the first register, and sets the valid bit in the first register to a valid state.

[0012] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a hardware-assisted page table management method, which is applied to a computer processor, and the method includes: receiving an access instruction; performing a hit detection operation based on the access instruction, if the TLB does not hit, based on the access instruction, obtaining a host physical address corresponding to the access instruction, storing the host physical address, and performing a valid bit setting operation; performing a page table lookup operation according to the host physical address; if the lookup fails, performing a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, storing the client page table entry obtained in the lookup in a cache line of a preset format, and storing the cache line of the preset format in the secondary cache; based on the shadow page table entry, performing a corresponding access operation.

[0013] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the hardware-assisted page table management method when executed by a processor.

[0014] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements the hardware-assisted page table management method.

[0015] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the hardware-assisted page table management method.

[0016] As described above, the hardware-assisted page table management system, method, medium, program product and terminal of the present application have the following beneficial effects: 1) transparent conversion of client page table addresses in the cache is realized by hardware assistance, effectively reducing the address conversion overhead; 2) innovatively designing the life cycle management scheme of shadow page table entries to ensure the stability and reliability of system operation; 3) adopting a unique client operating system page table maintenance processing scheme to achieve software-level transparency and reduce system complexity. Experimental results show that compared with the prior art, the present invention has significant performance improvements, 17% higher than nested paging and 8.5% higher than Victima, making the performance of the virtualized environment reach 89% of the native performance, greatly improving the overall performance of the virtualized system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A structural diagram of an embodiment of a hardware-assisted page table management system of the present application is shown.

[0018] Figure 2 A flowchart of the interaction process in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0019] Figure 3 A schematic diagram of the structure of the SgCR3 register and the gCR3 register in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0020] Figure 4 A schematic diagram of the structure of cache lines in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0021] Figure 5 A flowchart of address translation in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0022] Figure 6 A flow chart showing different hit situations in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0023] Figure 7 A schematic diagram showing the effects of multiple load conditions in an embodiment of the hardware-assisted page table management system of the present application is shown.

[0024] Figure 8 A flowchart of an embodiment of the hardware-assisted page table management method of the present application is shown.

[0025] Fig. 9 A structural schematic diagram of an embodiment of a hardware-assisted page table management terminal of the present application is shown. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0028] <1> Page Table Management: Page Table Management refers to the process of creating, updating and maintaining page tables. Page tables are used by the operating system to manage the mapping between virtual memory and physical memory.

[0029] <2> MMU unit: The memory management unit (MMU) is a computer hardware component that is responsible for converting virtual addresses into physical addresses and implementing memory protection and address space management.

[0030] <3> Memory Cell: Memory Cell is the basic component of computer memory, responsible for persistent data storage. Its internal structure includes multiple levels of cache, such as L1 cache, L2 cache and L3 cache, and supports the mapping of guest page table entries (gpt entry) and host page table entries (npt entry) in virtualization. The crossbar bus (XBAR) provides parallel communication capabilities to improve the data transmission efficiency between the processor and the memory, while the dynamic random access memory (DRAM) as the core of the main memory needs to be refreshed regularly to maintain data validity.

[0031] <4> Guest Page Table Walker: The Guest Page Table Walker is used to access and search the page table inside the virtual machine and is often used in a virtualization environment.

[0032] <5> Host Page Table Walker: The Host Page Table Walker is a component that accesses the internal page tables of the host operating system and manages the mapping of the host virtual address space.

[0033] <6> Page Walk Cache Module: The Page Walk Cache Module is a cache mechanism that stores recently used page table entries to speed up the page table traversal process.

[0034] <7> SgCR3 Register: The SgCR3 Register stores the guest page table base address, which is used to point to the page table of the guest physical address space.

[0035] <8> gCR3 register: The gCR3 register (gCR3 Register) records the page table base address associated with the current virtual machine context and is used for address translation.

[0036] <9> Page table lookup operation: Page table lookup operation is the process of obtaining the physical address corresponding to the virtual address by looking up the page table.

[0037] <10> Cache Line: Cache Line is the basic unit of data storage in the CPU cache, usually composed of multiple bytes, which determines the minimum granularity of obtaining data from the main memory.

[0038] <11> DRAM: Dynamic random access memory (DRAM) is a type of semiconductor memory widely used in computers and electronic devices. It stores data in a dynamic manner and needs to be constantly refreshed to retain information.

[0039] <12> Guest physical address: Guest physical address refers to the physical memory address that the virtual machine can directly access, which is converted through the host machine's memory management.

[0040] <13> Host Physical Address: The Host Physical Address is the actual host machine physical memory address, through which the guest virtual machine's physical address is mapped.

[0041] <14> Shadow Guest Page Table Entry: A Shadow Guest Page Table Entry is a page table entry maintained on the host machine, which is used to quickly convert guest virtual addresses to host physical addresses to avoid accessing the guest page table.

[0042] <15> TLB: Translation Lookaside Buffer (TLB) is a cache mechanism used to store the mapping of recently accessed virtual addresses to physical addresses to speed up address translation.

[0043] <16> Guest Page Table: The Guest Page Table (gPT) is a page table maintained inside the virtual machine, which is used to manage the mapping of virtual addresses in the guest operating system to their physical addresses.

[0044] <17> Nested Translation Lookaside Buffer: The Nested Translation Lookaside Buffer is used to improve the efficiency of address translation in a nested virtualization environment and store virtual machine address mappings.

[0045] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The structural diagram of a hardware-assisted page table management system in an embodiment of the present invention is shown, and the system includes an MMU unit and a memory unit, wherein the MMU unit includes: a TLB hit detection module, a guest page table lookup module and a page traversal cache module; the memory unit includes: a first-level cache and a second-level cache. The present invention replaces the guest physical address gPA of the client page table in the cache with the host physical address hPA, thereby greatly reducing the need for nested address translation, while maintaining the software transparency of the client operating system. The client page table entry containing the hPA after replacement is called a shadow guest page table entry (Shadow Guest Page TableEntry).

[0046] The interaction of the hardware-assisted page table management system in this embodiment is as follows Figure 2 As shown, it mainly includes the following steps:

[0047] Step S21: the MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction, and if the TLB does not hit, the guest page table lookup module obtains a host physical address corresponding to the access instruction based on the access instruction.

[0048] In one embodiment of the present invention, after obtaining the host physical address corresponding to the access instruction, the following steps are further performed: storing the host physical address in a guest page table lookup module, and performing a valid bit setting operation on the guest page table lookup module.

[0049] In one embodiment of the present invention, the process of the guest page table lookup module acquiring the host physical address corresponding to the access instruction based on the access instruction includes: the guest page table lookup module requests the host page table lookup module to make the host page table lookup module convert the guest physical address gPA into the host physical address hPA based on the access instruction. The host page table addresser includes a host page table traverser and a second register.

[0050] In one embodiment of the present invention, the guest page table lookup module includes: a guest page table walker and a first register; the first register includes a valid bit and a host physical address bit, wherein the initial state of the valid bit is an invalid state.

[0051] In one embodiment of the present invention, the first register is the SgCR3 register, and the second register is the gCR3 register. Figure 3 The structural diagram of the SgCR3 register and the gCR3 register in this embodiment is shown. Among them, bits 65-52 of the gCR3 register are reserved bits, and bits 51-13 are gPA of the first-level client page table; bits 65-53 of the SgCR3 register are reserved bits, 53-52 are valid bits, and bits 51-13 are hPA of the first-level client page table. Among them, the reserved bits in the register are unused register bits, which are reserved for future expansion or compatibility. The SgCR3 register sets the 1 in the reserved bit as a valid bit to indicate whether the hPA currently stored in the SgCR3 is valid.

[0052] In this embodiment, the SgCR3 register is used to directly provide the first-level hPA of the guest page table to the guest page table walker (GPTW), thereby reducing additional conversion or search steps, thereby reducing latency. Among them, the client page table walker is a structure for finding and parsing guest page tables in a virtual environment. The traditional GPTW is used to map gvA to gPA, and the process includes a search function, a hierarchy, and an address conversion. GPTW accesses the guest page table step by step, starting from the first-level page table until the target page table entry is found. The guest page table usually adopts a multi-level structure, such as a second-level or third-level page table, and obtains the physical address by reading the content of each layer. In this embodiment, when the client operating system initiates a memory access request, GPTW uses the host physical address (Host Physical Address, hPA) stored in the SgCR3 register for direct access.

[0053] In this embodiment, the operating system and the virtualization monitoring program are not allowed to modify the SgCR3 register directly to ensure the stability and security of the system. The initial state of the valid bit is set to an invalid state to indicate that the current SgCR3 register has not yet established a valid hPA mapping. The SgCR3 register and the gCR3 register are maintained consistent through an automatic access and synchronization mechanism. Specifically, when SgCR3 is in an invalid state, the gPA is automatically retrieved from the gCR3 register, and the MMU unit is requested to convert the gPA to the hPA, and the generated hPA is stored in the SgCR3 and the valid bit is set to establish a mapping from gPA to hPA.

[0054] Furthermore, when the gCR3 register is modified, the valid bit of SgCR3 is cleared, so that the address translation is performed again on the next access, ensuring that any updates are reflected and avoiding potential data inconsistencies. Maintaining consistency between the SgCR3 register and the gCR3 register is critical to system stability and data integrity. If the two are out of sync, memory access errors may occur, affecting the overall system performance. In addition, through dynamic mapping and intelligent invalidation mechanisms, the design of SgCR3 effectively adapts to different memory requirements, improves access efficiency, and reduces expected delays.

[0055] In one embodiment of the present invention, the process in which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction includes: the first register is communicatively connected to the second register; the first register obtains the guest physical address from the second register based on the access instruction; the second register searches for the corresponding host physical address in the host page table traverser based on the guest physical address, and sends the host physical address back to the first register; the MMU unit stores the host physical address in the first register, and sets the valid bit in the first register to a valid state.

[0056] Step S22: the MMU unit performs a page table lookup operation in the page traversal cache module according to the host physical address; if the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request.

[0057] In one embodiment of the present invention, the MMU is used for address translation and memory management, and converts virtual addresses into physical addresses so that the processor can access the memory. In this embodiment, the host physical address is input into the MMU, and the MMU searches for the corresponding page table entry in the page traversal cache module. Among them, the page traversal cache is a cache mechanism for storing the most recently used page table information, which is intended to speed up the page table lookup operation, and the page table is used to map the virtual address to the physical address. By performing the page table lookup operation, the MMU can quickly confirm the physical page corresponding to the host physical address. However, if the MMU fails to find a matching page table entry in the cache, it is necessary to perform further address translation operations in the main memory unit. Subsequently, the MMU sends the host physical address to the memory unit to initiate an address translation request, requesting the memory management system or other hardware units (such as the main memory) to perform a deeper address translation to determine the actual physical address.

[0058] Step S23: the memory unit performs a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, the client page table entry obtained is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module.

[0059] In one embodiment of the present invention, the cache line of the preset format includes: a tag, a status bit, multiple client page table entries and a first shadow flag bit; each client page table entry includes: a second shadow flag bit and a page number; wherein the first shadow flag bit includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a client page table entry that is replaced by a shadow page table entry; the second flag is used to indicate that the current cache line does not contain a client page table entry that is replaced by a shadow page table entry; the second shadow flag bit includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current client page table entry has been replaced by a shadow page table entry; and the fourth flag is used to indicate that the current client page table entry has not been replaced by a shadow page table entry.

[0060] Figure 4 A schematic diagram of the cache line structure of an embodiment of the present invention is shown, which includes a 64-byte cache line of 8 8-byte client page table entries. The present invention creatively selects a bit from the unused bits of each client page table entry as a shadow flag bit, which is used to indicate whether the client page table entry is a shadow client page table entry or an original client page table entry. Exemplarily, in the initial state, the value of the shadow flag bit is 0, indicating that the client page table entry is in the original state. When the cache converts the original client page table entry into a shadow client page table entry, the shadow flag is set to 1. At this time, the current cache line cannot be directly read by the guest operating system and cannot be written back to the memory, thereby ensuring the memory security and effectiveness of the virtual machine.

[0061] It is worth mentioning that this innovation effectively reduces storage requirements by utilizing unused bits of client page table entries as shadow flags, without the need for additional storage overhead, thereby improving memory utilization efficiency. Secondly, the use of shadow flags can quickly identify the status of client page table entries and optimize the address translation process. This efficient status indication reduces search time and improves the overall performance of the system. In addition, when the original client page table entry is converted to a shadow client page table entry, a strategy that does not allow direct reading or writing back to memory is adopted to enhance the security of the virtual machine. This design prevents the guest operating system from directly accessing sensitive data and ensures memory protection. Life

[0062] In one embodiment of the present invention, efficient cycle management is provided for the shadow client page table entry. Although the speed of page table traversal can be accelerated by converting the original client page table entry into the shadow client page table entry, the original client page table entry still needs to be retained so that the client operating system can manage it. In addition, in order to prevent the modification and replacement of the only copy in the cache system, a protection mechanism is set when establishing the shadow client page table entry, thereby ensuring that the original client page table entry can be safely stored and remain valid when the page table entry conversion is performed.

[0063] Specifically, when the shadow flag of a data block in the L2 cache is updated from 0 to 1, it means that the data block will only contain original guest page table entries, and one of the entries is about to be converted to a shadow guest page table entry. In this process, the L2 cache will first write the data block back to the L3 cache to ensure that all original guest page table entries are safely stored in the L3 cache, thereby avoiding the loss of the original virtual address (gPA) in the guest page table (gPT). When the L2 cache moves a data block containing a shadow guest page table to the L3 cache due to replacement, the system will first check whether there is a corresponding shadow data block in the L3 cache. If so, the L3 cache will write this data block to the main memory, which will be responsible for storing these original guest page table entries. When the L3 cache needs to evict a data block containing a shadow guest page table entry, this data block will be directly discarded. If this shadow guest page table entry needs to be accessed again in the future, the system will re-convert it from the corresponding original guest page table entry. These mechanisms together ensure efficient management of page tables and data integrity. In simple terms, they manage virtual memory efficiently, ensuring that critical data is not lost and can be accessed and updated quickly.

[0064] In one embodiment of the present invention, the process of storing the found customer page table entry in a cache line of a preset format includes: the secondary cache determines the second shadow flag in the current customer page table entry; if the second shadow flag is the fourth flag, the current customer page table entry is converted into a corresponding shadow page table entry through the nested page table addresser in the memory unit, and the second shadow flag is set to the third flag; the replaced customer page table entry is stored in the current cache line, and the first shadow flag of the current cache line is set to the first flag.

[0065] Figure 5 The address translation process diagram in one embodiment of the present invention is shown. As shown in step 1 and step 2, when both L1TLB and L2 TLB miss, GPTW is activated to perform the page table traversal operation in step 3. The process of the page table traversal operation includes: executing step 4, obtaining the hPA of the global four-level page table (Global Level 4PageTable, gL4) from the SgCR3 register. As described in the above embodiment, the initial state of the valid bit in the SgCR3 register is an invalid state. When accessed for the first time, as shown in step 5, the SgCR3 register obtains the gPA of gL4 from the gCR3 register, and executes the request in step 6 to convert the host page table addresser into hPA, and stores the converted hPA in the SgCR3 register, and marks the valid bit in the SgCR3 register as valid.

[0066] Further, as shown in step 7, the GPTW queries the Page Walk Cache (PWC) for the shadow guest page table entry. If the shadow guest page table entry is not found in the PWC, the L2 cache is accessed. In step 8, if the guest page table entry is found in the L2 cache or the corresponding entry is retrieved from the lower level cache, the L2 cache will check whether the shadow flag of the requested guest page table entry is set to 1. If not set, the L2 cache will issue a request to the Host Page Table Walker (HPTW) (step 9) to convert the guest page table entry into a shadow guest page table entry and set the shadow flag to 1. Finally, the shadow guest page table entry is cached in the L2 cache and PWC, and finally returned to the GPTW so that the guest page table walker can directly access the next level guest page table using the physical address (hPA) in the shadow guest page table entry, thereby avoiding requesting the Nested Translation Lookaside Buffer (NTLB) or performing a nested page translation (PTW). Among them, the Nested Translation Lookaside Buffer (NTLB) is a memory management mechanism designed to support virtualization technology and optimize memory access by improving the efficiency of address translation in a virtual environment. NTLB is mainly used for memory access between the hypervisor and the virtual machine (VM), allowing multi-layer mapping between the virtual address of the virtual machine and the physical address of the host.

[0067] Step S24: the page traversal cache module sends the shadow page table entry to the guest page table lookup module, so that the guest page table lookup module performs a corresponding access operation based on the shadow page table entry.

[0068] In one embodiment of the present invention, the interaction method of the system includes one or more of the following steps: if the first-level cache misses and the second-level cache hits, and the second shadow flag bit of the customer page table item of the hit request is the fourth flag, then the customer page table item of the hit request is sent to the first-level data cache of the memory unit; if the first-level cache misses and the second-level cache hits, and the second shadow flag bit of the customer page table item of the hit request is the third flag, then other layers of cache structure or DRAM memory are requested to provide cache lines that do not contain shadow page table entries, and the cache lines that do not contain shadow page table entries are sent to the first-level data cache of the memory unit; if the first-level cache misses and the second-level cache misses, the MMU unit and the memory unit perform customer page table item consistency maintenance operations.

[0069] Figure 6It is shown that in this embodiment, when the client operating system reads the client page, if the requested client page table entry cannot be found in the L1 data cache, the request is further sent to the L2 cache, and corresponding different operations are performed based on the hit status of the L2 cache and the setting of the shadow flag.

[0070] Specifically, this embodiment includes three scenarios. For scenario one, if the L2 cache hits the requested customer page table entry, and the shadow flag (Shadows) in the cache block is not set, that is, the third flag mentioned above, it means that the requested customer page table entry is found in the current L2 cache, and no customer page table entry in the cache data block (cache line) is converted to a shadow customer page table entry. At this time, since the shadow flag is not set, the customer page table entry is still the original valid item and can be directly used for physical address conversion. The L2 cache directly forwards the currently hit cache data block to the L1 data cache (L1Data Cache) to meet the access request of the client operating system.

[0071] For scenario 2, if the L2 cache hits the requested customer page table entry and the shadow flag (Shadows) in the cache block is set, it means that the block containing the requested customer page table entry contains one or more shadow customer page table entries. In order to prevent the client operating system from reading the shadow customer page table entry, the L2 cache cannot directly return the block to the L1 data cache (L1 Data Cache). Direct return may cause the client operating system to obtain invalid or inconsistent data, causing security and stability issues. Therefore, the L2 cache needs to request blocks with unset shadow flags from other caches or from DRAM through the bus. To ensure that the returned data is valid and does not contain shadow customer page table entries. Once the requested valid block is successfully received, the L2 cache will directly send the data to the L1 Data Cache without updating the L2 cache to avoid overwriting any existing shadow customer page table entries.

[0072] For scenario three, if the requested customer page table entry is not found in the L2 cache, the L2 cache will follow the standard cache miss handler and request the target block. When the client operating system writes to the customer page table, the system will initiate a consistency request to ensure that the L1 data cache (L1 Data Cache) holds an exclusive or modified copy of the target customer page table entry block. This operation will invalidate all copies of the relevant blocks in the L2 and L3 caches. In addition, the relevant customer page table entries must also be invalidated in the page traversal cache module (PWC). To maintain the consistency of the PWC, a PWC cleanup operation is performed during the translation lookaside buffer (TLB) refresh to ensure that after the customer page table is modified, the old shadow customer page table entries are promptly invalidated in the PWC, L2, and L3 caches, thereby eliminating the risk of data inconsistency.

[0073] To evaluate the performance and energy efficiency of the present invention, experiments were conducted under multiple load conditions and compared with existing methods. The experimental results show that in this experiment, the method corresponding to the present invention is named Ninja. Figure 7 The horizontal axis in the graph represents a variety of common computing tasks and algorithms, and the vertical axis represents the speedup ratio (Speedup). The higher the value, the more significant the performance improvement. The horizontal axis represents a variety of algorithms, among which Betweenness Centrality (BC) is used to evaluate the importance of node connections in the network; Breadth-First Search (BFS) is a graph search algorithm that traverses adjacent nodes layer by layer from the starting node; Connected Components (CC) represents the largest subgraph of all reachable parts of the graph that are not connected to other parts; Deep Learning Recommendation Model (DLRM) is a deep learning algorithm for personalized recommendation; Graph Coloring (GC) is an algorithm for coloring nodes in the graph to ensure that adjacent nodes have different colors; Genomics Benchmark (k-mercounting in GenomicsBench) is a benchmark workload for evaluating the performance of computing systems; PageRank (PR) is an algorithm that determines the importance of web pages based on link structure; Random Access (RND) is the process of randomly selecting paths in a graph to walk; Shortest Path (Shortest Path, SP), used to calculate the shortest path from the source node to other nodes; Triangle Counting (TC), used to analyze the structural characteristics of the graph by calculating the number of triangles in the graph; Monte Carlo Macro-Sectional Search Performance Analysis Tool (XSBench, XS) Monte Carlo method is a numerical method based on random sampling, which is widely used in computational simulation and optimization problems in various fields. Macro-section search refers to the process of finding the optimal solution in a large-scale search space; Geometric Mean (GMEAN), a statistical method used to measure the comprehensive performance of different test results.

[0074] Figure 7The performance of Victima, the present invention, and Native (non-virtualized environment performance, as a reference) in terms of execution time acceleration is demonstrated, and the present invention is significantly better than the existing solutions in terms of performance. On average, the performance of the present invention is improved by 17% compared to Nested paging and 8.5% compared to Victima. In addition, under the optimization of the present invention, the average performance in the virtualized environment is improved from the original 76% to 89% of the native performance level.

[0075] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first shadow flag and the second shadow flag are only used to distinguish different shadow flags, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0076] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0077] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0078] Figure 8 is a flow chart of the hardware-assisted page table management method provided in the embodiment of the present application. Figure 8 As shown, the method is applied to a computer processor, and the method comprises the following steps:

[0079] Step S81: receiving an access instruction; performing a hit detection operation based on the access instruction, if the TLB does not hit, obtaining a host physical address corresponding to the access instruction based on the access instruction, storing the host physical address, and performing a valid bit setting operation.

[0080] Step S82: perform a page table lookup operation according to the host physical address; if the lookup fails, perform a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, store the client page table entry obtained in the lookup into a cache line of a preset format, and store the cache line of the preset format into the secondary cache.

[0081] Step S83: Based on the shadow page table entry, perform a corresponding access operation.

[0082] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0083] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0084] Fig. 9 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Fig. 9 As shown, the electronic terminal includes: at least one processor 901, a memory 902, at least one network interface 903 and a user interface 905. The various components in the device are coupled together through a bus system 904. It can be understood that the bus system 904 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig. 9 In the specification, various buses are labeled as bus systems.

[0085] The user interface 905 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0086] It is understood that the memory 902 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0087] The memory 902 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 900. Examples of these data include: any executable program used to operate on the electronic terminal 900, such as an operating system 9021 and an application 9022; the operating system 9021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 9022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The hardware-assisted page table management method provided by the embodiment of the present invention can be included in the application 9022.

[0088] The method disclosed in the above embodiment of the present invention can be applied to the processor 901, or implemented by the processor 901. The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 901 or the instruction in the form of software. The above processor 901 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 901 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 901 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0089] In an exemplary embodiment, the electronic terminal 900 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0090] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes the hardware-assisted page table management method of any embodiment shown in the above embodiments.

[0091] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code runs on a computer, the computer executes the hardware-assisted page table management method of any one of the embodiments shown above.

[0092] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0093] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0094] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0095] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0096] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0099] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0100] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0101] In summary, the present application provides a hardware-assisted page table management system, method, medium, program product and terminal, and provides a page table cache management method in a virtualization system, which realizes efficient address conversion through the collaborative work of MMU units and memory units. The method includes key steps such as TLB hit detection, guest page table search, and page traversal cache search. After the MMU unit receives the access instruction, it performs detection through the TLB hit detection module; if it does not hit, the guest page table search module obtains the corresponding host physical address. The system performs a search in the page traversal cache module, accesses the secondary cache of the memory unit when necessary, and stores the search results in a cache line of a preset format. The present invention realizes transparent conversion of client page table addresses in the cache through hardware assistance, and provides a complete shadow page table entry life cycle management solution. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0102] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A hardware-assisted page table management system, characterized in that: The system comprises an MMU unit and a memory unit, and the system comprises: The MMU unit includes: a TLB hit detection module, a guest page table lookup module and a page traversal cache module; The memory unit includes: a first-level cache and a second-level cache; The interaction method of the system includes the following steps: The MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction, and if the TLB does not hit, the guest page table lookup module obtains a host physical address corresponding to the access instruction based on the access instruction; The MMU unit performs a page table lookup operation in the page traversal cache module according to the host physical address; if the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request; The memory unit performs a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, the client page table entry obtained by the lookup is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module; The page traversal cache module sends the shadow page table entry to the guest page table lookup module, so that the guest page table lookup module performs a corresponding access operation based on the shadow page table entry.

2. The hardware-assisted page table management system according to claim 1, characterized in that: The cache line of the preset format includes: a tag, a status bit, a plurality of client page table entries and a first shadow flag bit; each client page table entry includes: a second shadow flag bit and a page number; The first shadow flag bit includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a client page table entry that is replaced by a shadow page table entry; the second flag is used to indicate that the current cache line does not contain a client page table entry that is replaced by a shadow page table entry; The second shadow flag includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current client page table entry has been replaced by a shadow page table entry; and the fourth flag is used to indicate that the current client page table entry has not been replaced by a shadow page table entry.

3. The hardware-assisted page table management system according to claim 2, characterized in that: The process of storing the found guest page table entry into a cache line in a preset format includes: The secondary cache determines the second shadow flag in the current customer page table entry; if the second shadow flag is the fourth flag, the current customer page table entry is converted into a corresponding shadow page table entry through the nested page table addresser in the memory unit, and the second shadow flag is set to the third flag; the replaced customer page table entry is stored in the current cache line, and the first shadow flag of the current cache line is set to the first flag.

4. The hardware-assisted page table management system according to claim 2, characterized in that: The interaction method of the system includes one or more of the following steps: If the L1 cache misses and the L2 cache hits, and the second shadow flag bit of the client page table entry of the hit request is the fourth flag, the client page table entry of the hit request is sent to the L1 data cache of the memory unit; If the L1 cache misses and the L2 cache hits, and the second shadow flag bit of the client page table entry of the hit request is the third flag, then other layers of cache structures or DRAM memory are requested to provide a cache line that does not contain the shadow page table entry, and the cache line that does not contain the shadow page table entry is sent to the L1 data cache of the memory unit; If the L1 cache misses and the L2 cache misses at the same time, the MMU unit and the memory unit perform a client page table entry consistency maintenance operation.

5. The hardware-assisted page table management system according to claim 1, characterized in that: The guest page table lookup module comprises: a guest page table walker and a first register; the first register comprises a valid bit and a host physical address bit, wherein an initial state of the valid bit is an invalid state.

6. The hardware-assisted page table management system according to claim 5, characterized in that: The process of the guest page table lookup module acquiring the host physical address corresponding to the access instruction based on the access instruction includes: The first register is communicatively connected with the second register; the first register obtains a guest physical address from the second register based on the access instruction; The second register searches the host page table walker for a corresponding host physical address based on the guest physical address, and sends the host physical address back to the first register; The MMU unit stores the host physical address in the first register and sets the valid bit in the first register to a valid state.

7. A hardware-assisted page table management method, characterized in that: The method is applied to a computer processor, and the method comprises: Receive an access instruction; perform a hit detection operation based on the access instruction, if the TLB does not hit, obtain a host physical address corresponding to the access instruction based on the access instruction, store the host physical address, and perform a valid bit setting operation; performing a page table lookup operation according to the host physical address; if the lookup fails, performing a page table lookup operation in the secondary cache based on the host physical address; if the lookup succeeds, storing the found client page table entry in a cache line of a preset format, and storing the cache line of the preset format in the secondary cache; Based on the shadow page table entry, a corresponding access operation is performed.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the hardware-assisted page table management method described in claim 7 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program codes, and when the computer program codes are executed on a computer, the computer is enabled to implement the hardware-assisted page table management method as claimed in claim 7.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the hardware-assisted page table management method of claim 7.

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