High-efficiency hypergraph processing method and device based on variable resistance type memory

Abstract

The invention discloses an efficient hypergraph processing method and device based on a variable resistance type memory, and aims to solve the bottleneck problem of a traditional hypergraph processing architecture in the aspect of memory access. Comprising the following steps: on the basis of a hybrid in-memory computing architecture of a variable resistive random access memory, combining two in-memory computing engines of an analog resistive random access memory and a digital resistive random access memory, and dividing the workload of a hypergraph into a dense format and a sparse format by utilizing the overlapping characteristic of the hypergraph; and different workloads can be efficiently executed on the adaptive processing engine, so that higher performance and energy efficiency are realized. According to the method, a novel efficient software and hardware collaborative design scheme is provided for hypergraph processing, and wide application of hypergraph processing is promoted.

Description

Technical Field

[0001] The present invention relates to the field of hypergraph computing, and in particular to an efficient hypergraph processing method and device based on a variable resistance memory. Background Art

[0002] Traditional graph structures are limited to capturing pairwise relationships between objects. However, real-world scenarios are often more complex and involve multilateral relationships. Therefore, hypergraphs have emerged to naturally represent these multilateral relationships, where each hyperedge can connect any number of vertices. Hypergraph processing enables expressive and efficient analysis of such relational data. Today, hypergraph processing has been widely used in many fields such as machine learning, drug discovery, and VLSI design.

[0003] Hypergraph processing corresponds to an iterative process with two computational kernels, including two basic computational kernels: hyperedge computation and vertex computation. The former uses active vertices to update the states of their related hyperedges through a hyperedge update function of a specific algorithm; the latter uses newly activated hyperedges to update vertex states through a vertex update function. Previous studies have shown that hypergraph processing is often limited by memory. The latest solutions based on CPUs and ASICs have improved the locality of hypergraph processing by exploiting the inherent overlap of hypergraph structures, but have not yet effectively solved the memory bottleneck problem in hypergraph processing.

[0004] Unlike the traditional von Neumann architecture that relies on a separate compute-memory hierarchy, Processing-in-Memory (PIM) is a promising technology that improves memory-constrained applications by integrating processing units in memory. Past studies have demonstrated that Resistive Random Access Memory (ReRAM) is effective in improving the performance of ordinary graph processing. Considering that ordinary graphs are special cases of hypergraphs (each hyperedge connects only two vertices), a feasible way to accelerate hypergraph processing is to directly reuse existing ReRAM-based graph accelerators to alternately support hyperedge computing and vertex computing cores. However, hypergraph processing exhibits unique irregularities caused by kernel differences and overlaps, so simply applying existing graph processing solutions to hypergraph applications cannot effectively improve performance.

[0005] On the one hand, traditional graph applications only need to update the vertex state using the same update operation in each iteration. In contrast, in hypergraph applications, the states of hyperedges and vertices are updated separately by two alternating kernels in each iteration. To support hypergraph processing, existing ReRAM-based graph accelerators must alternate between processing hyperedge computation and vertex computation kernels in each iteration. However, the update logic of these two kernels is completely different, so when performing kernel switching, we have to remap the kernel-specific data into the crossbar array. As a result, this may incur significant additional resistor write overhead, up to 2 times the kernel execution time. Moreover, this overhead may increase significantly as the number of iterations increases.

[0006] On the other hand, in order to exploit the huge parallelism provided by the matrix-structured crossbar array architecture, existing ReRAM-based graph processing accelerators must assume that the crossbar array cells are fully utilized. However, real-world hypergraph structures often overlap, and the vast majority of vertices are associated with at least two hyperedges, and vice versa. Therefore, hypergraph processing exhibits workload irregularities caused by overlap. That is, overlapping dense topological substructures form dense (or sparse) regions in the association matrix generated by the hypergraph. Mapping these sparse submatrices into the ReRAM crossbar array often results in most of the cells being unused, resulting in redundant resistor writes and analog signal conversions, with limited performance and energy improvements. Although some research efforts have attempted to alleviate the performance degradation caused by sparsity in the ReRAM architecture, few studies have considered the unique overlapping characteristics of hypergraphs, resulting in poor improvement.

[0007] We observe that the two computation kernels can be unified from the perspective of matrix-vector multiplication (MVM). The kernels of hyperedge computation and vertex computation can be formalized as a set of MVM operations, which only requires transposing the input matrices. For example, taking the PageRank algorithm as an example, its vertex and hyperedge update functions use the incidence matrix caused by the hypergraph, and its transposed matrix In addition, we also observe that there is no absolute winner between digital memristor-based processor-in-memory (DPIM) and analog memristor-based processor-in-memory (APIM) in efficiently processing all hypergraph workloads. By partitioning the hypergraph into dense and sparse workloads according to overlapping characteristics, APIM and DPIM can be used to accelerate different (dense or sparse) workloads to maximize the overall efficiency, thereby further alleviating the irregularity problem caused by overlap. Therefore, we design a hybrid architecture that integrates APIM and DPIM technologies to achieve hypergraph processing with significant performance and energy efficiency improvements.

[0008] However, there are still challenges in implementing the above ideas. First, the input matrix generated by the hyperedge computing kernel needs to be transposed to the matrix generated by the vertex computing kernel. Alternating the mapping of the association matrix and its transpose into the ReRAM crossbar array may introduce redundant resistor writes, thereby limiting the potential performance improvement. Second, in order to maximize the performance potential of the hybrid architecture, the most important task is to polarize the association matrix caused by the hypergraph into dense or sparse sub-matrices. However, due to the complex connection relationship between vertices and hyperedges, it is very difficult to design a fast and efficient partitioning strategy. Third, after the hypergraph partitioning, different tasks related to the same vertex or hyperedge may be executed in different processing engines, which may generate a large number of intermediate results, resulting in non-negligible reduction overhead.

[0009] In summary, the present invention aims to propose a ReRAM-based hypergraph processing solution and device with high performance and low energy consumption.

[0010] In addition, firstly, due to the possible differences in understanding among those skilled in the art; secondly, the inventor referred to a large number of documents and patents when conducting research on the present invention, but due to space limitations, all relevant details cannot be listed in detail. It should be pointed out that this does not mean that the present invention lacks the features of the prior art. On the contrary, the present invention already contains the features of all relevant prior art. At the same time, the applicant reserves the right to add relevant prior art content in the background technology section. Summary of the invention

[0011] The purpose of the present invention is to provide a hypergraph processing solution and device based on ReRAM to address the deficiencies of the prior art.

[0012] The objective of the present invention is achieved through the following technical solutions: an efficient hypergraph processing method based on a variable resistance memory, including an in-memory calculation method for hypergraph processing based on a variable resistance memory, in which the hyperedge calculation kernel and vertex calculation kernel in the hypergraph processing are formally converted into matrix-vector calculation operations, and then mapped to the variable resistance memory for calculation.

[0013] Furthermore, in the hyperedge calculation kernel, the active vertex updates its associated hyperedge through the update function; in the vertex calculation kernel, the active hyperedge updates its associated vertex through the update function; specifically, the PageRank algorithm is adopted, and its corresponding hyperedge calculation kernel and vertex calculation kernel are represented by the matrix-vector calculation in formula (1) and formula (2), respectively:

[0014] (1)

[0015] (2)

[0016] in, Represents the vertex attribute value, represents the hyperedge attribute value, represents the incidence matrix of the hypergraph, and the superscript T represents the transposition operation. represents the degree of the vertex, represents the degree of the hyperedge, is the weight parameter, is the number of vertices in the hypergraph.

[0017] Furthermore, the hypergraph processing is mapped to the variable resistance memory for calculation, including:

[0018] Variable resistance memory includes analog resistance random access memory and digital resistance random access memory;

[0019] Divide the hypergraph processing tasks into dense workloads and sparse workloads;

[0020] For dense computational loads in hypergraph processing, the corresponding hyperedge association matrix and the vertex incidence matrix The dense submatrices in are mapped to the cross arrays in APIM, and then the corresponding matrix-vector calculations are performed;

[0021] For sparse workloads in hypergraph processing, the corresponding bipartite edges are mapped to the rows of the DPIM crossbar array. By utilizing the row-level parallelism of DPIM, the calculation of multiple bipartite edges can be processed simultaneously.

[0022] Furthermore, the hypergraph processing tasks are divided into dense workloads and sparse workloads through an overlap-aware hypergraph partitioning strategy, including:

[0023] First, we need to construct s-line graphs for hyperedges and vertices respectively to record the overlapping hyperedges and vertices;

[0024] The construction process of the hyperedge s-line graph is as follows: each hyperedge in the hypergraph is regarded as a node in the s-line graph, and the overlap parameter s is determined, which is used to judge the overlap relationship between hyperedges. Next, by checking the number of common vertices connected between each pair of hyperedges, if the number of vertices shared by two hyperedges reaches or exceeds s, an edge is created for them in the hyperedge s-line graph, thereby forming a connection between the nodes;

[0025] Construct an s-line graph of vertices: The vertices of the hypergraph are still the vertices of the s-line graph of vertices. If the number of common hyperedges between two vertices exceeds s, an edge is established between the two vertices.

[0026] Based on the hyperedge s-line graph and the vertex s-line graph, a sub-association matrix is ​​induced; the hyperedges in the sub-association matrix come from the nodes in the hyperedge s-line graph, and the vertices in the sub-association matrix come from the nodes in the vertex s-line graph; the sub-association matrix is ​​divided into multiple sub-matrix blocks, and the density of each sub-matrix block, that is, the proportion of non-zero elements to total elements, is calculated; if the density of the sub-matrix block is greater than or equal to a first preset threshold D, it is marked as a dense workload; otherwise it is marked as a sparse workload.

[0027] Furthermore, it also includes the selection of the value of the overlap parameter s and the density threshold D;

[0028] The value of s is estimated by the following heuristic method:

[0029]

[0030] Where |V| and |H| are the number of vertices and hyperedges, respectively;

[0031] The D value is determined based on the global density of the hypergraph; the D value is obtained by the following formula:

[0032]

[0033] Among them, GD represents the global density of the hypergraph, and α indicates whether the hypergraph algorithm is fully activated or not.

[0034] Further, the difference in the number of bipartite edges of each APIM or DPIM cross array is within a second preset threshold; and the difference in the number of vertices and hyperedges in each cross array is within a third preset threshold.

[0035] Furthermore, how to map the workload of the partitioned blocks to the corresponding crossbar array.

[0036] The sparse workload is mapped to the DPIM cross array, including: the sparse workload is organized into a bipartite edge table, each bipartite edge will be mapped to a row of the DPIM cross array for parallel processing; during hyperedge calculation, the sparse bipartite edges are mapped to the DPIM rows in the order of the hyperedge index, and during vertex calculation, the sparse bipartite edges are mapped to the DPIM rows in the order of the vertex index.

[0037] Dense workloads are mapped to the DPIM cross array, including the data construction method and mapping granularity; data construction method: map the hypergraph topology to the APIM cross point, using a single-bit mode, where bits '1' and '0' represent the connection relationship between the corresponding hyperedges and vertices; mapping granularity: dense workloads include multiple dense sub-matrices, which are flattened to fill the APIM cross array, thereby achieving a good balance in the three dimensions of APIM cross array utilization, execution efficiency, and hardware cost.

[0038] The present invention also provides an efficient hypergraph processing device based on a variable resistance memory, comprising a plurality of processing units, a controller, an on-chip cache, an on-chip interconnection network, and a global reducer;

[0039] The processing unit includes two types of processing engines: dense processing engine and sparse processing engine; the former integrates APIM cross array to process workloads at the dense matrix level. The latter is responsible for processing workloads at the sparse bipartite graph edge level using DPIM cross array, supporting efficient calculation of dense and sparse workloads;

[0040] The crossbar array includes the APIM crossbar array and the DPIM crossbar array. The APIM crossbar array is used to store the association matrix and its transposition of the hypergraph, supporting highly parallel data access and calculation; the DPIM crossbar array uses its row-level parallelism to calculate the sparse bipartite edge part in the hypergraph workload;

[0041] The controller is responsible for coordinating data interaction and communication between different components. Its core functions include: managing data rewrite operations on the DPIM crossbar array, scheduling sparse block data to idle sparse processing engines, transferring off-chip sparse two-part edge data to the ReRAM in the sparse processing engine through the on-chip interconnect network and temporarily storing the data, thereby achieving partial parallelization of data acquisition and processing;

[0042] The on-chip cache is used to temporarily store the hypergraph data read from the memory;

[0043] The on-chip interconnection network adopts a Mesh network structure to provide data transmission channels for different processing units, so that on-chip caches inside different processing units can be shared, thereby improving the scalability of the on-chip caches;

[0044] The global reducer is used to reduce the intermediate results from different processing units after the calculation is completed to generate the final hypergraph processing result.

[0045] Further, the dense processing engine includes an APIM crossbar array, a simple arithmetic logic unit, and an input / output register;

[0046] The APIM crossbar array is used to store and process the matrix block parts corresponding to the dense workload in the hypergraph association matrix;

[0047] The simple algorithm logic unit is used to merge the intermediate result vectors obtained by the APIM cross array calculation to obtain the corresponding partial intermediate result values ​​after the vertex or hyperedge is updated;

[0048] The input / output register is used to store the value of the intermediate result obtained by the aggregation of the simple arithmetic logic unit.

[0049] Further, the sparse processing engine includes a DPIM crossbar array, a variable resistance memory, a parallel aggregation network, and an SPE on-chip cache;

[0050] The DPIM crossbar array is used to process workloads with sparse bipartite edge granularity;

[0051] The variable resistance memory is used to temporarily store the input sparse two-part edge data, and realizes partial overlap of data loading and calculation process through data pre-fetching strategy, thereby reducing the delay required when mapping data to the DPIM array;

[0052] The parallel aggregation network reduces the intermediate results obtained by calculating the two-part edges of the DPIM cross array;

[0053] The SPE on-chip cache is used to temporarily store the reduction results obtained after the parallel aggregation network is aggregated.

[0054] The SPE on-chip cache (14) is used to temporarily store the reduction result obtained after the parallel aggregation network is aggregated. The beneficial effects of the present invention are as follows: the present invention realizes efficient hypergraph processing based on the RERAM characteristics, utilizes the applicability of APIM and DPIM to different workloads, realizes a hybrid scheduling strategy that maps different hypergraph workloads to different execution units, and improves the execution efficiency of hypergraph processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0056] Figure 1 It is a schematic diagram of the hardware structure of a preferred high-efficiency supergraph device based on a variable resistance memory of the present invention;

[0057] Figure 2 This is a schematic diagram of the preferred APIM transposition storage crossbar array architecture of the present invention;

[0058] Figure 3 It is a schematic diagram of the preferred hypergraph sparse load and dense load mapping processing of the present invention;

[0059] Figure 4 This is a schematic diagram of the preferred APIM single-bit mapping of the present invention;

[0060] Figure 5 is a schematic diagram of a preferred hyperedge s-line graph of the present invention;

[0061] Figure 6 It is a schematic diagram of a preferred vertex s-line diagram of the present invention.

[0062] List of reference numerals:

[0063] 1: Processing unit; 2: Controller; 3: On-chip cache; 4: On-chip interconnect network; 5: Global reducer; 6: Dense processing engine; 7: APIM crossbar array; 8: Simple arithmetic logic unit; 9: Input / output register; 10: Sparse processing engine; 11: DPIM crossbar array; 12: Variable resistive memory; 13: Parallel aggregation network; 14: SPE on-chip cache. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of this application. In the absence of conflict, the features in the following embodiments and implementations can be combined with each other.

[0065] The problem of limited memory access in current hypergraph processing has caused memory access to become an obvious bottleneck in the hypergraph processing process. In scenarios with real-time requirements, existing hypergraph processing solutions are difficult to meet the requirements, thus hindering the development of hypergraph modeling problems. Furthermore, since memory access has become a bottleneck, the optimization of hypergraph processing at the computational level has also been limited to a certain extent. Processing solutions based on in-memory computing (Process in Memory) have been proven to be the best solution to the memory access bottleneck. Although there are many in-memory computing solutions for graph computing, and although hypergraph computing is a variant of graph computing, due to the difference in dual computing cores and special overlapping characteristics, existing in-memory computing designs are not suitable for the overall workflow of hypergraph processing. Therefore, the present invention provides an efficient in-memory computing solution for hypergraph processing based on a variable resistive memory and a corresponding device, aiming to solve the problem of limited memory access in hypergraph processing.

[0066] The present invention provides an efficient in-memory computing solution for hypergraph processing based on a variable resistance memory, comprising:

[0067] The hyperedge calculation kernel and vertex calculation kernel in hypergraph processing are formally converted into matrix-vector calculation operations, and then mapped to variable resistive memory for calculation. The hypergraph consists of a vertex set V and a hyperedge set H, and a hyperedge can connect any number of vertices. The association matrix of the hypergraph is called the occurrence matrix M, where the rows represent vertices and the columns represent hyperedges. The non-zero elements in the matrix represent the relationship between vertices and hyperedges. In the hyperedge calculation kernel, active vertices update their associated hyperedges through update functions; similarly, in the vertex calculation kernel, active hyperedges update their associated vertices through update functions. Taking the PageRank algorithm as an example, its corresponding hyperedge calculation kernel and vertex calculation kernel are represented by the matrix-vector calculations in formula (1) and formula (2), respectively. Formula (1) represents the process of obtaining hyperedge attribute values ​​from vertex attribute values ​​in the hyperedge calculation kernel corresponding to the Pagerank algorithm. Specifically, the vertex attribute value First, we need to divide by the vertex degree to get the message value passed to the hyperedge associated with the vertex. The message values ​​passed by all vertices form a vector, and then perform matrix-vector multiplication with the vertex association matrix, which means that the hyperedge aggregates the message values ​​passed by all its associated vertices, thereby obtaining a new hyperedge attribute value. Similarly, formula (2) represents the process of calculating a new round of vertex attribute values ​​based on the hyperedge attribute value. The hyperedge attribute value needs to be divided by the hyperedge degree as the message value passed by the hyperedge to its associated vertex, and then all the message values ​​passed by the hyperedge form a vector and perform matrix-vector multiplication with the hyperedge association matrix to obtain a new round of vertex attribute values. In order to introduce random jumps and solve the problem of hanging nodes, the PageRank algorithm usually introduces parameters. To increase the robustness of the algorithm, Represents the part transmitted from other vertices through hyperedges, represents the part that randomly jumps to any vertex, where is the number of vertices in the hypergraph.

[0068] (1) (2)

[0069] Variable resistive memory includes analog resistive random access memory (APIM) and digital resistive random access memory (DPIM). The dense computing load in hypergraph processing corresponds to the dense submatrix of the hyperedge association matrix and the vertex association matrix. The rows in the hyperedge association matrix represent hyperedges, the columns represent vertices, and the elements in the matrix represent the connection relationship between hyperedges and vertices; the rows in the vertex association matrix represent vertices, the columns represent hyperedges, and the elements in the matrix represent the connection relationship between vertices and hyperedges. In particular, the vertex association matrix and the hyperedge association matrix have a transposed relationship with each other. The dense submatrix corresponding to the dense computing load can be mapped to the cross array in the APIM, and then the corresponding matrix-vector calculation is performed. This mapping method can process dense workloads with lower time complexity. For sparse workloads in hypergraph processing, the corresponding bipartite edges can be mapped to the rows of the cross array. DPIM uses its row-level parallelism to process the calculation of multiple bipartite edges simultaneously.

[0070] Among them, dense workloads usually refer to blocks with high overlap in the hypergraph. The hyperedges in these blocks are associated with multiple identical vertices, and the vertices are also associated with multiple identical hyperedges. In this case, the density of non-zero elements (i.e., 1) in the sub-association matrix corresponding to the block is high. In contrast, sparse workloads refer to blocks with low overlap in the hypergraph. The connections between the vertices and hyperedges in this part are relatively sparse, resulting in a more dispersed distribution of non-zero elements in the association matrix, showing a sparse characteristic. Sparse workloads usually involve less calculations, but require frequent data access. Using different computing schemes according to different workloads can maximize execution efficiency.

[0071] The input hypergraph processing task is unloaded into different workloads and mapped to different processing components to achieve maximum execution efficiency. The hypergraph processing task can be effectively decomposed into dense and sparse workloads through the overlap-aware hypergraph partitioning strategy. The overlap-aware hypergraph partitioning strategy is as follows:

[0072] Taking the construction process of the hyperedge s-line graph as an example, each hyperedge in the hypergraph is regarded as a node in the s-line graph, and the overlap parameter s is determined, which is used to judge the connection relationship between the hyperedges. Next, by checking the number of common vertices connected between each pair of hyperedges, if the number of vertices shared by the two hyperedges reaches or exceeds s, an edge is created for them in the s-line graph to form a connection between the nodes. Finally, after further post-processing, the generated hyperedge s-line graph effectively expresses the overlap relationship between the hyperedges in the hypergraph, providing a structured basis for the subsequent dense and sparse workload partitioning and scheduling. The construction process of the vertex s-line graph is similar to that of the hyperedge s-line graph, except that the nodes in the vertex s-line graph correspond to the vertices in the hypergraph, and the edges correspond to the overlap relationship of the common hyperedges connecting the hypergraph vertices.

[0073] Then, different workloads are generated through the s-line graph, and the grid partitioning strategy is used to efficiently partition the association matrix representing the hyperedge and vertex relationships. According to the hyperedge s-line graph and vertex s-line graph constructed in the previous step, a sub-association matrix can be induced. The hyperedges in the sub-association matrix come from the nodes in the hyperedge s-line graph, and the vertices in the sub-association matrix come from the nodes in the vertex s-line graph. Next, in order to further identify dense and sparse workloads, we divide this association matrix into multiple sub-matrix blocks. The content is evenly divided according to the dimension of the matrix and the specified block size. For example, assuming that the dimension of the association matrix is ​​M×N, a fixed dimension (such as p×q) can be selected to determine the size of each sub-matrix block, and then the entire matrix can be divided into several p×q sub-matrix blocks. For each sub-matrix block, its density is calculated, that is, the proportion of non-zero elements to the total elements. Next, by comparing with the set threshold D, if the density of a submatrix block is higher than the threshold D, that is, it is a dense submatrix block, it will be marked as a dense workload, indicating that the hyperedges (vertices) corresponding to the area have a very high degree of overlap and are suitable for allocation to the DPE (Dense Processing Engine) with strong processing capabilities; on the contrary, if the density is lower than the threshold D, it is regarded as a sparse workload, indicating that the area is sparsely connected and is suitable for allocation to the SPE (Sparse Processing Engine) with lower computing resource requirements.

[0074] Furthermore, it is necessary to select appropriate values ​​of the overlap parameter s and the density threshold D. The selection of parameters s and D jointly affects the efficiency and effectiveness of the partitioning, and further affects the overall performance of the hypergraph processing. First, the impact of the s value is discussed. On the one hand, choosing an appropriate s is crucial to the efficiency of the partitioning. For a specific hypergraph, building an s-line graph with a small s value may be more time-consuming than a large s value. On the other hand, the number of dense partitions is determined by the s value and the size of the hypergraph. A small s value means generating a larger s-line graph, which further produces many dense partitions. Taking all the above factors into consideration, the s value can be estimated by the following heuristic method:

[0075]

[0076] where |V| and |H| are the number of vertices and hyperedges, respectively.

[0077] The D value is determined based on the global density of the hypergraph. For dense hypergraphs, a larger threshold is selected to achieve load balance between DPE and SPE. In addition, the characteristics of the hypergraph algorithm will also affect the selection of D. Based on experimental experience, we obtain the D value through the following formula:

[0078]

[0079] Where GD represents the global density of the hypergraph. α indicates whether the hypergraph algorithm is fully activated or not, and is represented by an empirical value of 1 or 10.

[0080] In one embodiment, a load balancing scheduling strategy is also included.

[0081] The load-balanced scheduling strategy refers to a hybrid partitioning scheduling strategy that ensures that the difference in the number of bipartite edges of each APIM and DPIM cross array is within a specific threshold, and the number of vertices and hyperedges in each cross array remains balanced. This strategy takes into account the limited local buffer size, ensures load balancing and maximizes data reuse.

[0082] It is necessary to map the different workloads of the partitioned blocks to the corresponding crossbar arrays. Due to the fine-grained parallelism of DPIM, its mapping method can be simple and direct. After the hypergraph is partitioned into sparse and dense partitions, the sparse partitions are organized into bipartite edge tables. Each bipartite edge will be mapped to the row of the DPIM intersection for parallel processing. Considering the hardware design requirements, we map the sparse bilateral edges to the DPIM rows in the order of the hyperedge index during hyperedge calculation, and map the sparse bilateral edges to the DPIM rows in the order of the vertex index during vertex calculation, so that SPE can efficiently process sparse partitions.

[0083] The mapping of dense partition blocks on the APIM crossbar array requires more considerations, including the data construction method and mapping granularity. First, the data mapped to the crossbar array is very important. Taking the calculation in formula (1) as an example, in traditional design, Mapped into the crossbar array, V is used as the input signal for calculation. However, this method is not suitable for hypergraph processing due to the different matrix coefficients of the hyperedge calculation and vertex calculation kernels. Therefore, we only map the hypergraph topology to the APIM crossbar, using a single-bit mode, where bit '1' ('0') represents the connection relationship between the corresponding hyperedge and vertex. In this case, different matrix sparsities can be achieved by different simple logic units. Mapping granularity is another key factor in the algorithm mapping on the APIM crossbar. For fine-grained mapping, such as when the crossbar array is divided into 2×2 small blocks, the high parallelism of APIM cannot be fully utilized, resulting in low performance. On the contrary, if coarse-grained mapping is adopted, many cells in the crossbar array will have zero values, resulting in a large number of invalid calculations. Since most overlaps occur only on a few hyperedges and vertices, hypergraph partitioning usually corresponds to small-sized dense submatrix blocks, such as 8×8. However, the size of APIM crossbars usually exceeds 128×128, which can share peripheral circuits to reduce the overall area overhead. Therefore, we limit the size of dense submatrices to 8×8 and flatten multiple dense submatrices to fill crossbar arrays of size 128×128 or larger, thus achieving a good balance among the three dimensions of crossbar array utilization, execution efficiency, and hardware cost.

[0084] The present invention also provides an efficient hypergraph processing device based on a variable resistance memory, comprising a plurality of processing units 1, a controller 2, an on-chip cache 3, an on-chip interconnection network 4, and a global reducer 5;

[0085] The processing unit 1 includes two types of processing engines: dense processing engines 6 (DPEs) and sparse processing engines 10 (SPEs). The former integrates an APIM crossbar array to process workloads at the dense matrix level. The latter is responsible for processing workloads at the sparse bipartite graph edge level using the DPIM crossbar array, supporting efficient computing of dense and sparse workloads;

[0086] The controller 2 is responsible for coordinating data interaction and communication between different components. Its core functions include: managing data rewrite operations on the DPIM cross array, and scheduling sparse block data to the idle sparse processing engine 10, transmitting the sparse two-part edge data outside the chip to the ReRAM in the sparse processing engine 10 through the on-chip interconnect network and temporarily storing the data, realizing partial parallelization of data acquisition and processing, thereby reducing the delay of data mapping to the DPIM cross array, so as to achieve efficient resource utilization and optimization of system performance.

[0087] The on-chip cache 3 is used to temporarily store the hypergraph data read from the memory, providing fast data access to support efficient computing processes;

[0088] The on-chip interconnect network 4 adopts a Mesh network structure to provide efficient data transmission channels for different processing units 1, so that the on-chip caches 3 inside different processing units 1 can be shared, which can effectively reduce redundant data storage and improve the efficiency of data access.

[0089] The global reducer 5 is used to reduce the intermediate results from different processing units 1 after the calculation is completed, generate the final hypergraph processing result, and ensure the consistency and integrity of the data.

[0090] In one embodiment, the dense execution engine 6 includes an APIM crossbar array 7, a simple arithmetic logic unit 8, and an input / output register 9;

[0091] The APIM crossbar array 7 is used to store and process the matrix block parts corresponding to the dense loads in the hypergraph association matrix. When the traditional APIM crossbar array is used to perform matrix-vector multiplication (MVM) operations, the input is a row vector and the output is a column vector. However, hypergraph processing requires iterative execution of hyperedge calculation and vertex calculation kernels, and their input matrices are transposed of each other. In the context of traditional crossbar arrays, the association matrix and its transposed matrix must be alternately loaded into the crossbar array and iteratively executed with the two calculation kernels. This inevitably introduces redundant resistor writing and analog signal conversion, resulting in additional performance and energy consumption overhead. By attaching simple logic circuit units to the traditional APIM crossbar array, a lightweight transposed storage crossbar array architecture can be constructed, such as Figure 2 The architecture allows voltages to be applied in the vertical and horizontal directions, with the input voltages coupled to the corresponding output currents in orthogonal directions. During processing, only one set of orthogonal directions can be used simultaneously. The transposed crossbar array can perform matrix-vector multiplications (by applying the input vectors as voltages on the rows and columns of the crossbar array, respectively). ) and transposed matrix-vector multiplication ( )operate.

[0092] The simple algorithm logic unit 8 is used to merge the intermediate result vectors calculated by the APIM cross array 7 to obtain the corresponding partial intermediate result values ​​after the vertex or hyperedge is updated;

[0093] The input / output register 9 is used to store the value of the intermediate result aggregated by the simple arithmetic logic unit 8 .

[0094] In one embodiment, the sparse processing engine 10 includes a DPIM crossbar array 11, a variable resistive memory 12, a parallel aggregation network 13, and an SPE on-chip cache 14;

[0095] The DPIM crossbar array 11 is used to process workloads with sparse bipartite edge granularity;

[0096] The variable resistor memory 12 is used to temporarily store the input sparse two-part edge data, and can achieve partial overlap of data loading and calculation processes through data pre-fetching strategy, effectively reducing the delay required when mapping data to the DPIM array 11;

[0097] The parallel aggregation network 13 reduces the intermediate results obtained by calculating the two-part edge by the DPIM cross array 11;

[0098] The SPE on-chip cache 14 is used to temporarily store the reduction results obtained after the parallel aggregation network is aggregated.

[0099] Embodiment 1:

[0100] This embodiment introduces the specific method of offloading hypergraph tasks to different computing arrays.

[0101] The method of offloading the hypergraph tasks to different computing arrays is as follows: Figure 3 As shown, we will divide the association matrix of the hypergraph into two partitions, dense and sparse. The dense partition contains nodes and hyperedges with a high degree of overlap, which is convenient for representation in dense matrix form. Next, we write the dense submatrix into the cross array of APIM for calculation. The cross array design of APIM enables it to efficiently handle matrix operations and is suitable for efficient processing of dense data. The sparse partition contains nodes and hyperedges with a low degree of overlap. We store them in the form of bipartite edge lists, which can effectively save storage space, and then map each bipartite edge to a row on the cross array of DPIM for calculation.

[0102] The specific mapping method for APIM is as follows Figure 2As shown, first, the matrix data is mapped to the ReRAM crossbar array in the form of conductivity G, which is the inverse of resistance. Through the digital-to-analog converter (DAC), the input vector is converted into a voltage signal V, which is then applied to the wordlines of the APIM. According to Kirchhoff's law, the current signal on the bitline can be calculated as I = V × G. The current is converted into a digital value through the analog-to-digital converter (ADC), and the output vector stores the multiplication result of the preloaded matrix and the input vector. The APIM crossbar array can natively perform matrix-vector multiplication (MVM) operations with a time complexity of O(1). In contrast, traditional architectures such as central processing units (CPUs) usually rely on arithmetic or bit operations as basic operations, and the time complexity of performing MVM is O(n²), accompanied by the movement of a large amount of data between memory and processing units. For applications based on MVM operations, such as hypergraph processing, the crossbar-based APIM architecture can significantly improve the overall performance. In traditional designs, Mapped to the cross array, V is used as the input signal for calculation. However, due to the different matrix coefficients of the hyperedge calculation and vertex calculation kernels, this method is not suitable for hypergraph processing. Therefore, we only map the hypergraph topology to the APIM intersection, using a single-bit mode, where bit '1' ('0') represents the connection relationship between the corresponding hyperedge and vertex, such as Figure 4 As shown in the mapping relationship, we will pre-process the output vector through an external simple logic circuit to complete the division calculation of hyperedge value / vertex degree and vertex value / hyperedge degree in advance. For example, from the hypergraph vertex association matrix mapped on APIM, we know that the degree of the vertex with index 0 is 3, so the signal of the first row input should be Similarly, the signal value of the first round of hyperedge at input also needs to be divided by the hyperedge degree. The hypergraph degree corresponds to Figure 4 The matrix is ​​the number of non-zero values ​​in the column vector. This process ensures the unification of the calculation mode of the hyperedge kernel and the vertex kernel on APIM.

[0103] For the specific calculation process of DPIM, two columns of data Write in a one-bit per ReRAM cell mode, corresponding to the value input of the superedge H and vertex V in the two-part edge, where the high resistance (10MΩ) in the first column represents the bit '0', and the low resistance (10KΩ) in the second column represents the bit '1'. In the third column, the output result is initialized to '1' (i.e. low resistance). Then, an isolation voltage is applied to unused rows and columns to isolate these cells. At the same time, a specific voltage and ground voltage is applied to the rows corresponding to the input and output columns, Used to select the activated row for calculation. If the input cell in the activated row is programmed to a low resistance state (i.e., '1'), according to Ohm's law, a high current will flow into the output cell, causing its resistance to increase from a low state to a high state (i.e., '1' → '0'). Similarly, if both input cells in the activated row are programmed to a high resistance state (i.e., '0'), the current will be limited and the resistance of the output cell will remain unchanged (i.e., '1'). Therefore, the output data can be viewed as the formula H NOR V. It has been proven that almost all arithmetic operations such as addition and multiplication can be expressed as a series of NOR operations, so any calculation process between hyperedge values ​​and vertex values ​​can be implemented by combining ReRAM cells, and the calculation of sparse bipartite edges is completed in the order of hyperedge or vertex indices.

[0104] Embodiment 2:

[0105] This embodiment introduces an overlap-aware hypergraph load partitioning strategy.

[0106] First, according to the number of hyperedges H and the number of vertices V of the hypergraph, we can use the formula ,The overlap parameter s is calculated and used to determine the degree of overlap captured by the s-line graph. It is the round-up symbol, indicating the smallest integer greater than or equal to this number.

[0107] Constructing the hyperedge s-line graph, the purpose of this stage is to capture the overlapping characteristics of hyperedges by abstracting the hyperedges into new vertices and creating new edges to represent the specified overlapping relationships. If the number of common vertices between two hyperedges exceeds s, an abstract edge is established between the corresponding abstract vertices. The s-line graph retains the key topological structure features of the original hypergraph while removing unimportant overlapping relationships.

[0108] Constructing a vertex s-line graph is similar to the construction method of the hyperedge s-line graph. The vertex s-line graph can reflect the connection relationship between the vertices in the original hypergraph. The hypergraph vertices are still the vertices of the vertex s-line graph. If the number of common hyperedges between two vertices exceeds s, an edge is established between the two vertices.

[0109] By choosing a suitable value of s, we can obtain an appropriate number of hyperedges and vertices to construct a preliminary dense sub-hypergraph. The remaining hyperedges and vertices are classified as sparse workloads. For the preliminary dense partitioning, we further adopt a grid partitioning strategy to divide the occurrence matrix induced by the sub-hypergraph into multiple sub-matrix blocks. If the density of a sub-matrix block is higher than the specified threshold 𝐷, it is regarded as a dense workload; otherwise, the sub-matrix block is regarded as a sparse workload. Figure 3 Taking the hypergraph as an example, according to the formula, it can be calculated that the overlap degree s should be set to 1.

[0110] When the overlap degree s is 1, the hyperedge s-line graph abstracted in the way of abstracting the s-line graph is as follows Figure 5 As shown, the vertex s-line graph is Figure 6 As shown in the figure, the initial dense blocks are generated according to the hyperedges and vertices in the two graphs. Figure 3 As shown in the dense partition part of , the remaining two-part edge part is classified as the sparse load part as Figure 3 The sparse partitioning section is shown in the figure.

[0111] according to The calculation formula is: First, calculate the global density of the hypergraph, which can be calculated according to the probability of 1 appearing in the association matrix of the hypergraph. Figure 3 The correlation matrix shown can calculate GD to be 0.56. Assuming that the current hypergraph application is the PageRank algorithm, then It should be 1, then the density threshold D should be 0.75. If the dense block initially obtained meets this density threshold, it will be classified as a dense load.

[0112] The above embodiments are only used to illustrate the design ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design ideas disclosed by the present invention are within the protection scope of the present invention.

Claims

1. An efficient hypergraph processing method based on variable resistance memory, characterized in that: The invention comprises an in-memory calculation method for hypergraph processing based on a variable resistance memory. The hyperedge calculation kernel and vertex calculation kernel in the hypergraph processing are formally converted into matrix-vector calculation operations, and then mapped to the variable resistance memory for calculation.

2. The method according to claim 1, characterized in that In the hyperedge calculation kernel, active vertices update their associated hyperedges through update functions; in the vertex calculation kernel, active hyperedges update their associated vertices through update functions. Specifically, the PageRank algorithm is adopted, and its corresponding hyperedge calculation kernel and vertex calculation kernel are represented by the matrix-vector calculations in formula (1) and formula (2), respectively: （1） （2） in, Represents the vertex attribute value, represents the hyperedge attribute value, represents the incidence matrix of the hypergraph, and the superscript T represents the transposition operation. represents the degree of the vertex, represents the degree of the hyperedge, is the weight parameter, is the number of vertices in the hypergraph.

3. The method according to claim 1, characterized in that: The hypergraph processing is mapped to the variable resistance memory for calculation, including: Variable resistance memory includes analog resistance random access memory and digital resistance random access memory; Divide the hypergraph processing tasks into dense workloads and sparse workloads; For dense computational loads in hypergraph processing, the corresponding hyperedge association matrix and the vertex incidence matrix The dense submatrices in are mapped to the cross arrays in APIM, and then the corresponding matrix-vector calculations are performed; For sparse workloads in hypergraph processing, the corresponding bipartite edges are mapped to the rows of the DPIM crossbar array. By utilizing the row-level parallelism of DPIM, the calculation of multiple bipartite edges can be processed simultaneously.

4. The method according to claim 3, characterized in that The hypergraph processing tasks are divided into dense workloads and sparse workloads through an overlap-aware hypergraph partitioning strategy, including: First, we need to construct s-line graphs for hyperedges and vertices respectively to record the overlapping hyperedges and vertices; The construction process of the hyperedge s-line graph is as follows: each hyperedge in the hypergraph is regarded as a node in the s-line graph, and the overlap parameter s is determined, which is used to judge the overlap relationship between hyperedges; next, by checking the number of common vertices connected between each pair of hyperedges, if the number of vertices shared by two hyperedges reaches or exceeds s, an edge is created for them in the hyperedge s-line graph, thereby forming a connection between the nodes; Construct an s-line graph of vertices: The vertices of the hypergraph are still the vertices of the s-line graph of vertices. If the number of common hyperedges between two vertices exceeds s, an edge is established between the two vertices. Based on the hyperedge s-line graph and the vertex s-line graph, a sub-association matrix is ​​induced; the hyperedges in the sub-association matrix come from the nodes in the hyperedge s-line graph, and the vertices in the sub-association matrix come from the nodes in the vertex s-line graph; the sub-association matrix is ​​divided into multiple sub-matrix blocks, and the density of each sub-matrix block, that is, the proportion of non-zero elements to total elements, is calculated; if the density of the sub-matrix block is greater than or equal to a first preset threshold D, it is marked as a dense workload; otherwise it is marked as a sparse workload.

5. The method according to claim 4, characterized in that It also includes the value of the overlap parameter s and the selection of the density threshold D; The value of s is estimated by the following heuristic method: Where |V| and |H| are the number of vertices and hyperedges, respectively; The D value is determined based on the global density of the hypergraph; the D value is obtained by the following formula: Among them, GD represents the global density of the hypergraph, and α indicates whether the hypergraph algorithm is fully activated or not.

6. The method according to claim 4, characterized in that The difference in the number of bipartite edges of each APIM or DPIM cross array is within a second preset threshold; and the difference in the number of vertices and hyperedges in each cross array is within a third preset threshold.

7. The method according to claim 3, characterized in that The sparse workload is mapped to the DPIM cross array, including: the sparse workload is organized into a bipartite edge table, each bipartite edge is mapped to a row of the DPIM cross array for parallel processing; in hyperedge calculation, the sparse bipartite edges are mapped to the DPIM rows in the order of the hyperedge index, and in vertex calculation, the sparse bipartite edges are mapped to the DPIM rows in the order of the vertex index; Dense workloads are mapped to the DPIM cross array, including the data construction method and mapping granularity; data construction method: map the hypergraph topology to the APIM cross point, using a single-bit mode, where bits '1' and '0' represent the connection relationship between the corresponding hyperedges and vertices; mapping granularity: dense workloads include multiple dense sub-matrices, which are flattened to fill the APIM cross array, thereby achieving a good balance in the three dimensions of APIM cross array utilization, execution efficiency, and hardware cost.

8. An efficient hypergraph processing device based on variable resistance memory, characterized in that: It includes a plurality of processing units (1), a controller (2), an on-chip cache (3), an on-chip interconnection network (4), and a global reducer (5); The processing unit (1) includes two types of processing engines: a dense processing engine (6) and a sparse processing engine (10); the former integrates an APIM cross array (7) for processing workloads at the dense matrix level; the latter is responsible for processing workloads at the sparse bipartite graph edge level using a DPIM cross array, supporting efficient calculation of dense and sparse workloads; The crossbar array includes an APIM crossbar array (7) and a DPIM crossbar array (11). The APIM crossbar array (7) is used to store the association matrix and its transpose of the hypergraph, supporting high-parallel data access and calculation; the DPIM crossbar array (11) uses its row-level parallelism to calculate the sparse bipartite edge part in the hypergraph workload; The controller (2) is responsible for coordinating data interaction and communication between different components. Its core functions include: managing data rewriting operations on the DPIM cross array, and scheduling sparse block data to idle sparse processing engines (10), transferring off-chip sparse two-part edge data to the ReRAM in the sparse processing engine (10) through the on-chip interconnect network (4) and temporarily storing the data, thereby realizing partial parallelization of data acquisition and processing; The on-chip cache (3) is used to temporarily store the hypergraph data read from the memory; The on-chip interconnection network (4) adopts a Mesh network structure to provide data transmission channels for different processing units (1), so that the on-chip cache (3) inside the different processing units (1) can be shared, thereby improving the scalability of the on-chip cache (3); The global reducer (5) is used to reduce the intermediate results from different processing units (1) after the calculation is completed, so as to generate a final hypergraph processing result.

9. The device according to claim 8, characterized in that The dense processing engine (6) includes an APIM crossbar array (7), a simple arithmetic logic unit (8), and an input / output register (9); The APIM crossbar array (7) is used to store and process the matrix block parts corresponding to the dense workload in the hypergraph association matrix; The simple algorithm logic unit (8) is used to merge the intermediate result vectors obtained by the APIM cross array calculation to obtain the corresponding partial intermediate result values ​​after the vertex or hyperedge is updated; The input / output register (9) is used to store the value of the intermediate result obtained by the simple arithmetic logic unit (8) aggregation.

10. The device according to claim 8, characterized in that The sparse processing engine (10) includes a DPIM crossbar array (11), a variable resistive memory (12), a parallel aggregation network (13), and an SPE on-chip cache (14); The DPIM crossbar array (11) is used to process workloads with sparse bipartite edge granularity; The variable resistance memory (12) is used to temporarily store the input sparse two-part edge data, and realizes partial overlap of data loading and calculation process through data pre-fetching strategy, thereby reducing the delay required when mapping data to the DPIM array (11); The parallel aggregation network (13) reduces the intermediate results obtained by calculating the two-part edge by the DPIM cross array (11); The SPE on-chip cache (14) is used to temporarily store the reduction results obtained after the parallel aggregation network is aggregated.

Images