Bonding method, wafer stacking structure and chip structure

Abstract

The invention provides a bonding method, a wafer stacking structure and a chip structure. The bonding method comprises the following steps: providing at least one first wafer stacking structure, and testing each chip area in the first wafer stacking structure; wherein the first wafer stacking structure comprises a plurality of first wafers which are bonded together; cutting the first wafer stacking structure to form a chip corresponding to the chip area; and bonding the chip with good function determined by the test with a second wafer. According to the method, after screening and testing, a small number of layers of chips with good functions are determined and then are further stacked, the bonded multi-layer stacked structure can be maintained at a high yield, the performance is achieved, and the loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a bonding method, a wafer stacking structure, and a chip structure. Background Art

[0002] With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology has been widely used, and the chip structure has developed in the three-dimensional direction. Among them, the chip-to-wafer (C2W) stacking structure can realize different functions in one, which can improve performance, enhance functions and reduce size.

[0003] The current C2W stacking structure uses multiple wafers to bond in sequence to form a multi-layer wafer bonding structure, and then cuts the wafer stacking structure to obtain the corresponding chip structure. Since it is difficult to maintain a 100% yield rate during the stacking process of multi-layer wafers, as the number of wafer stacking layers increases, the yield rate of the bonded wafer stacking structure will gradually decrease, and the loss will also become greater and greater. Summary of the invention

[0004] The present application provides a bonding method and a wafer stacking structure and a chip structure, which can not only realize multi-layer wafer or chip stacking, but also improve the yield of multi-layer wafer or chip stacking and reduce loss.

[0005] In order to solve the above technical problems, the first aspect of the present application provides a bonding method. The method includes: providing at least one first wafer stacking structure, testing each chip area in the first wafer stacking structure; wherein the first wafer stacking structure includes at least two first wafers bonded together; cutting the first wafer stacking structure to form chips corresponding to the chip area; and bonding the chips with good functions determined by the test to a second wafer.

[0006] In some embodiments, at least one first wafer stacking structure is provided, and each chip area in the first wafer stacking structure is tested, including: bonding at least two of the first wafers together in sequence to form the first wafer stacking structure; forming a test pad on a first surface of the first wafer stacking structure, the first surface being an outermost surface of the first wafer stacking structure perpendicular to the stacking direction; and testing the chip area in the first wafer stacking structure through the test pad to determine whether the corresponding chip area functions well.

[0007] In some embodiments, the first wafer stacking structure includes a top wafer located at the outermost side of the first wafer stacking structure perpendicular to the stacking direction, and a bottom wafer located at the other outermost side and arranged opposite to the top wafer, the top wafer is reserved with a test lead-out metal sheet, and the first surface is away from the bottom wafer; the test pad is formed on the first surface of the first wafer stacking structure, including: opening a through hole in the dielectric layer on the top wafer in the first wafer stacking structure to expose the test lead-out metal sheet; forming a connecting structure in the through hole, and forming the test pad on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the top wafer, and the test pad is connected to the test lead-out metal sheet through the connecting structure.

[0008] In some embodiments, after testing the chip region in the first wafer stacking structure through the test pad, the bonding method further includes: removing at least part of the test pad and the connection structure; and planarizing the first surface.

[0009] In some embodiments, cutting the first wafer stacking structure to form a chip corresponding to the chip area includes: temporarily bonding the first wafer stacking structure to a carrier wafer; cutting the first wafer stacking structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer; transferring the chip to a wafer rack using the carrier wafer, and removing the carrier wafer.

[0010] In some embodiments, temporarily bonding the first wafer stacking structure to the carrier wafer includes: using the first surface of the first wafer stacking structure as a bonding surface to bond to the carrier wafer, the first surface being an outermost surface of the first wafer stacking structure perpendicular to the stacking direction; after temporarily bonding the first wafer stacking structure to the carrier wafer, the bonding method further includes: thinning the bottom wafer of the first wafer stacking structure until the silicon vias in the bottom wafer and the metal columns in the silicon vias are exposed, the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

[0011] In some embodiments, bonding the chip whose functions are good as determined by the test to the second wafer includes: bonding the plurality of chips whose functions are good as determined by the test in sequence to the second wafer using a chip-to-wafer bonding technology.

[0012] To solve the above technical problems, the second aspect of the present application also provides a wafer stacking structure, including: a functional wafer; at least one first chip bonded to the functional wafer, the first chip including at least two grains bonded together, and one of the outer layer grains of the first chip forms a test lead-out metal sheet.

[0013] In some embodiments, the first chip is obtained by cutting a first wafer stack structure, and corresponds to a chip region of the first wafer stack structure that is tested and determined to have good functions;

[0014] The outer layer die of the first chip is bonded to the functional wafer, or bonded to other adjacent first chips.

[0015] To solve the above technical problems, the third aspect of the present application further provides a chip structure, including: at least one first chip, the first chip includes at least two grains bonded together, and one of the outer layer grains of the first chip forms a test lead-out metal sheet.

[0016] In some embodiments, the first chip is obtained by cutting a first wafer stacking structure, and corresponds to a chip area with good functions determined by testing in the first wafer stacking structure; the chip structure also includes a functional grain, and the functional grain is bonded to the outer grain of the first chip.

[0017] The bonding method provided in some embodiments of the present application includes: providing at least one first wafer stacking structure, and testing each chip area in the first wafer stacking structure; wherein the first wafer stacking structure includes a plurality of first wafers bonded together; forming a chip corresponding to the chip area by cutting the first wafer stacking structure; and bonding the chip with good function determined by the test to a second wafer. Compared with the traditional wafer multi-layer wafer bonding method, the present application tests each chip area of ​​a wafer stacking structure with fewer layers, and then bonds the chip with good function determined by the test to a second wafer, so as to achieve a higher number of chip-wafer stacking. During the chip stacking process, the bonded multi-layer stacking structure can maintain a higher yield, which not only achieves performance but also reduces losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1It is a schematic diagram of the structure of bonding two wafers in the prior art;

[0020] Figure 2 A schematic diagram of the structure of bonding two wafers in the prior art, wherein one wafer includes a through silicon via and a bonding metal pattern;

[0021] Figure 3 It is a schematic diagram of the structure of bonding three wafers in the prior art;

[0022] Figure 4 It is a schematic diagram of a wafer stacking structure after bonding multiple wafers in the prior art;

[0023] Figure 5 A flow chart of a bonding method provided for some embodiments of the present application;

[0024] Figure 6 Some embodiments of the present application provide Figure 5 Sub-flow chart of step S11;

[0025] Figure 7 A schematic diagram of a first wafer stacking structure provided in some embodiments of the present application;

[0026] Figure 8 for Figure 6 A schematic diagram of the wafer structure after being processed in step S112;

[0027] Fig. 9 Some embodiments of the present application provide Figure 6 Sub-flow chart of step S112;

[0028] Fig.10 for Figure 6 A schematic diagram of a wafer structure after being processed by step S114 and step S115;

[0029] Fig.11 Some embodiments of the present application provide Figure 5 Sub-flow chart of step S12;

[0030] Fig.12 for Fig.11 A schematic diagram of the wafer structure after being processed in step S121;

[0031] Fig.13 for Fig.11 A schematic diagram of the wafer structure after being processed in step S122;

[0032] Fig.14 for Fig.11 A schematic diagram of the wafer structure after being processed in step S123;

[0033] Fig.15 for Fig.11 A schematic diagram of the wafer structure after the chip is transferred to the wafer rack by using the carrier wafer in step S124;

[0034] Fig.16 for Fig.11 A schematic diagram of the wafer structure after the carrier wafer is removed by debonding in step S124;

[0035] Fig.17 for Figure 5 A schematic diagram of a wafer structure to which a chip having good functions determined by a test is bonded in step S13;

[0036] Fig.18 for Figure 5 A schematic diagram of a wafer structure of chips with good functions determined by bonding multiple tests in step S13;

[0037] Fig.19 A schematic diagram of a wafer stacking structure provided for some embodiments of the present application;

[0038] Fig. 20 Schematic diagram of the chip structure provided for some embodiments of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The terms "first" and "second" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0041] All directional indications in the embodiments of the present application (such as up, down, left, right, front, back, top, bottom...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0042] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0043] Unless otherwise defined, the term “substantially” mentioned in this application, with respect to numerical quantities or quantitative relationships, can be understood as a range of approximately ±15% of a certain numerical value.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The "front side" of the wafer mentioned in this article is the side with electronic components, and the "back side" is the side opposite to the "front side". The wafer bonding mentioned in this article is not limited to the bonding of the front side to the back side of the wafer, but can also be the bonding of the front side to the front side, or the bonding of the back side to the back side of the wafer.

[0046] Figure 1 It is a schematic diagram of the structure of bonding two wafers in the prior art; Figure 2 A schematic diagram of the structure of bonding two wafers in the prior art, wherein one wafer includes a through silicon via and a bonding metal pattern;

[0047] Figure 3 It is a schematic diagram of the structure of bonding three wafers in the prior art; Figure 4 It is a schematic diagram of a wafer stacking structure after multiple wafers are bonded in the prior art.

[0048] See also Figure 1-4In the prior art, the wafer stacking structure 90 adopts a method of bonding multiple wafers 91 in sequence to form a multi-layer wafer bonding structure. First, two wafers 91 are bonded front to front to form a 2-layer wafer stacking structure. Before bonding with the third wafer 91, the back of one of the wafers needs to be thinned to form a through silicon via 911, a metal layer 913 and a bonding metal pattern 912, wherein the through silicon via 911 connects the metal layer 913 on the front and back of the wafer 91; then bonded with the third wafer 91 to form a 3-layer wafer stacking structure; then repeat the above process until the required multi-layer wafer stacking structure 90 is formed. However, in the process of wafer stacking, it is difficult to maintain a 100% yield for wafer bonding. As the number of wafer stacking layers increases, the yield of the bonded wafer stacking structure will gradually decrease, and the loss caused will also become greater and greater. For example, if the yield of a wafer before bonding is 96% (assuming the yield of bonding between wafers is 100%), then after four stackings, that is, forming a five-layer wafer stacking structure, the yield will drop to 82%, and after eight stackings, that is, forming a nine-layer wafer stacking structure, the yield will drop to 69%. That is, forming a nine-layer wafer stacking structure will incur the cost of the process itself, and a 31% yield loss in addition to the cost.

[0049] In order to solve the above problems, the first aspect of the present application provides a bonding method. Figure 5 , Figure 5 A flowchart of a bonding method provided for some embodiments of the present application; the method specifically comprises:

[0050] Step S11: providing at least one first wafer stacking structure, and testing each chip region in the first wafer stacking structure; wherein the first wafer stacking structure includes at least two first wafers bonded together.

[0051] In the specific implementation process, see Figure 6 , Figure 6 Some embodiments of the present application provide Figure 5 Sub-flow chart of step S11 in FIG. 1 ; specifically, step S11 includes:

[0052] Step S111: bonding at least two of the first wafers together in sequence to form the first wafer stacking structure.

[0053] Among them, see Figure 7 , Figure 7Schematic diagram of the first wafer stacking structure provided for some embodiments of the present application. In the present embodiment, the first wafer stacking structure 10 is formed by bonding and stacking 4 first wafers 11, and the first wafer stacking structure 10 includes at least one chip area 12, and each first wafer 11 includes at least one through silicon via 111 and a metal layer 113, and the through silicon via 111 is filled with a conductive material to form a metal column 112, wherein the conductive material is copper, tungsten, or other metal material, and the metal layer 113 of adjacent first wafers 11 is electrically connected through the through silicon via 111 and the bonding metal pattern 114 correspondingly set in one of the first wafers 11. In other embodiments, the first wafer stacking structure 10 can be formed by stacking at least 2 first wafers 11 according to different needs or to achieve different functions, and can be specifically formed by stacking 3, 5, 6 or other numbers of first wafers 11. In some embodiments, the silicon through via 111 is made by via-middle and BVR (backside via review) processes, that is, the silicon through via 111 is prepared after FEOL (front end of line) (e.g., transistor) and MOL (middle of line) (e.g., metal contact) and before BEOL (back end of line) (e.g., metal layer). In other embodiments, to achieve different functions, the silicon through via 111 can be made by other processes, such as via-first or via-last. In some embodiments, the metal layer 113 and the bonding metal pattern 114 are formed by processes such as photolithography and etching.

[0054] Step S112: forming a test pad on a first surface of the first wafer stacking structure, where the first surface is an outermost surface of the first wafer stacking structure perpendicular to the stacking direction.

[0055] For details, see Figure 8 , Figure 8 for Figure 6Schematic diagram of the wafer structure after being processed by step S112; in this embodiment, the first wafer 11 of the first wafer stacking structure 10 is bonded from the front to the back as an example. In this embodiment, the first wafer stacking structure 10 includes a top wafer 11a which is arranged on the outermost side of the first wafer stacking structure 10 perpendicular to the stacking direction, and a bottom wafer 11b which is located on the other outermost side and is arranged opposite to the top wafer. Among them, the front side of the top wafer 11a, that is, the outermost side surface of the first wafer stacking structure 10 is the first surface 11a1. The top wafer 11a is reserved with a test lead-out metal sheet 121. In some embodiments, the test lead-out metal sheet 121 is formed at the same time as the metal layer 113 is formed in the dielectric layer 11a2 of the top wafer 11a, and the test lead-out metal sheet 121 is electrically connected to the metal layer 113 formed at the same time.

[0056] In the specific implementation process, see Fig. 9 , Fig. 9 Some embodiments of the present application provide Figure 6 Sub-flow chart of step S112 in FIG. 1 ; specifically, step S112 includes:

[0057] Step S1121: opening a through hole in the dielectric layer on the top wafer in the first wafer stacking structure to expose the test lead-out metal sheet;

[0058] Continue to see Figure 8 The top wafer 11a includes a dielectric layer 11a2, which is disposed on a side away from the bottom wafer 11b, and a test lead metal sheet 121 is embedded in the dielectric layer 11a2. A through hole 122 is opened in the dielectric layer 11a2, and the through hole 122 is disposed on a side of the test lead metal sheet 121 away from the bottom wafer 11b to expose the test lead metal sheet 121.

[0059] Step S1122: forming a connection structure in the through hole, and forming the test pad on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the bottom wafer, and the test pad being connected to the test lead-out metal sheet through the connection structure.

[0060] Continue to see Figure 8 , a conductive material is filled in the through hole 122 to form a connection structure 123, and a test pad 124 is formed on the first surface 11a1, so that the test lead metal sheet 121 is electrically connected to the test pad 124. Compared with other metal materials, such as copper, aluminum has an anti-oxidation property, so in some embodiments, the conductive material filled in the through hole 122 is aluminum.

[0061] Step S113: testing the chip region in the first wafer stacking structure by using the test pad to determine whether the corresponding chip region functions well.

[0062] Specifically, in some embodiments, the tests performed on the chip area 12 include but are not limited to: WAT (wafer acceptable test) and CP (chip probing). Among them, WAT is a test of a special test key (test pattern), which monitors whether each process step is normal and stable through electrical parameters; CP is a test of the wafer, including tests of some basic device parameters, such as vt (threshold voltage), Rdson (specific on-resistance), etc. Through the above tests, the chip area 12 with good functions can be determined and marked. In some embodiments, the chip area 12 with good functions is a chip area that can realize the corresponding electrical function.

[0063] In this embodiment, see Figure 6 , further comprising the following two steps after step S113:

[0064] Step S114: removing the test pad and at least part of the connection structure;

[0065] Step S115: performing planarization processing on the first surface.

[0066] For details, see Fig.10 , Fig.10 for Figure 6Schematic diagram of the wafer structure after being processed by step S114 and step S115. After the test is completed and the chip area with good function is screened out, the test pad 124 and the connection structure 123 need to be removed, that is, the electrical connection between the test lead metal sheet 121 and the outside of the corresponding chip area 12 needs to be disconnected. In order not to affect the subsequent chip stacking, it is necessary to fill the through hole 122 with a non-conductive material to form an insulating layer 125, and the first surface 11a1 needs to be flattened. Among them, for removing the test pad 124 and the connection structure 123, during the removal process, they can be completely removed; partial structures away from the bottom wafer 11b can also be removed; and the surrounding part of the first dielectric layer 11a2 can also be removed while removing the test pad 124 and the connection structure 123, as long as the electrical connection between the test lead metal sheet 121 and the outside of the corresponding chip area 12 can be disconnected, and the subsequent chip stacking will not be affected. In some embodiments, a wet etching process is used to etch the conductive material filled in the through hole 122, that is, the metal aluminum, so that the test pad 124 and the connection structure 123 can be removed. After the etching process is completed, in some embodiments, an oxide deposition process is used to fill the through hole 122, wherein the oxide deposition can be filled with silicon dioxide; then a CMP (Chemical Mechanical Polishing) process is used to planarize the first surface 11a1. In other embodiments, other methods can also be used to remove the conductive material, such as chemical etching, reactive ion etching or other dry etching.

[0067] Step S12: cutting the first wafer stack structure to form chips corresponding to the chip area.

[0068] In the specific implementation process, see Fig.11 , Fig.11 Some embodiments of the present application provide Figure 5 Sub-flow chart of step S12 in FIG. 1 ; specifically, step S12 includes:

[0069] Step S121: temporarily bonding the first wafer stacking structure to the carrier wafer.

[0070] For details, see Fig.12 , Fig.12 for Fig.11Schematic diagram of the wafer structure after processing by step S121. A carrier wafer 20 needs to be bonded before cutting the first wafer stacking structure 10. In this embodiment, the first surface 11a1 is set to bond with the carrier wafer 20, and the first wafer stacking structure 10 is bonded to the carrier wafer 20 by temporary bonding. Among them, in order to facilitate subsequent chip stacking, before bonding, a bonding metal pattern 114 can be formed in the dielectric layer 11a2, and the bonding metal pattern 114 is connected to the metal layer 113 in the top wafer 11a. In some embodiments, the bonding metal pattern 114 is formed by etching, deposition and other processes.

[0071] Step S122: thinning the bottom wafer of the first wafer stacking structure until the through silicon vias in the bottom wafer and the metal columns in the through silicon vias are exposed, the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

[0072] For details, see Fig.13 , Fig.13 for Fig.11 Schematic diagram of the wafer structure after processing in step S122. To facilitate subsequent chip stacking, the surface of the bottom wafer 11b away from the top wafer 11a, that is, the back side of the bottom wafer 11b, needs to be thinned to expose the through silicon vias 111 of the bottom wafer 11b and the metal pillars 112 in the through silicon vias 111. In some embodiments, the BVR (backside via review) process is still used to thin the bottom wafer 11b.

[0073] In this embodiment, the sequence of first temporarily bonding the carrier wafer 20 and then thinning the bottom wafer 11b of the first wafer stacking structure 10 is adopted. In other embodiments, the bottom wafer 11b of the first wafer stacking structure 10 may be thinned first and then the carrier wafer 20 is temporarily bonded, as long as it does not affect the subsequent chip stacking.

[0074] Step S123: cutting the first wafer stacking structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer.

[0075] For details, see Figure 13-14 , Fig.14 for Fig.11Schematic diagram of the wafer structure after processing in step S123. In some embodiments, the chip area 12 is first divided by photolithography scribing; then the first wafer stacking structure 10 is cut by etching to separate the chip area 12 to form a chip 30. Since the temporarily bonded carrier wafer 20 plays the role of carrying the chip 30 and does not participate in the subsequent chip stacking, in order to facilitate the subsequent removal of the carrier wafer 20, in some embodiments, when the first wafer stacking structure 10 is cut by etching, it stays on the bonding surface of the carrier wafer 20. In this way, a plurality of chips 30 bonded to the carrier wafer 20 can be obtained.

[0076] Step S124: using the carrier wafer to transfer the chip to a wafer rack, and removing the carrier wafer.

[0077] For details, see Figure 15-16 , Fig.15 for Fig.11 A schematic diagram of the wafer structure after the chip is transferred to the wafer rack by using the carrier wafer in step S124; Fig.16 for Fig.11 Schematic diagram of the wafer structure after the carrier wafer is removed in step S124. In the present embodiment, in order to facilitate the removal of the carrier wafer 20 and to facilitate the support and fixing of the chip 30 after the carrier wafer 20 is removed, the chip 30 needs to be transferred to the wafer rack 40 before the carrier wafer 20 is removed, wherein the surface of the chip 30 away from the carrier wafer 20 contacts the wafer rack 40. In the present embodiment, the carrier wafer is removed by debonding. In other embodiments, the carrier wafer can be removed by etching, CMP or other methods. In some embodiments, the wafer rack 40 is a blue film or a UV film (ultraviolet irradiation tape).

[0078] Step S13: bonding the chip with good functions determined by the test to a second wafer.

[0079] For details, see Figure 17-Figure 18 , Fig.17 for Figure 5 A schematic diagram of a wafer structure to which a chip having good functions determined by a test is bonded in step S13; Fig.18 for Figure 5 Schematic diagram of the wafer structure of the multiple functional chips determined to be good by the test in step S13. After the above steps, in this embodiment, the multiple functional chips 30 determined to be good by the test are sequentially bonded on the second wafer 50 using the chip-to-wafer bonding technology to form a multi-layer wafer stacking structure 100. In some embodiments, the second wafer 50 is a functional wafer, such as a logic wafer.

[0080] The bonding method provided in this embodiment provides a first wafer stacking structure 10 with at least 2 layers, and after testing the chip area 12, screens and marks the chip area 12 with good functions; then cuts the first wafer stacking structure 10 to obtain multiple chips 30 corresponding to the chip area 12, and multiple chips 30 with good functions can be selected. Finally, the multiple chips 30 with good functions determined by the test are bonded to the second wafer 50 in sequence using the chip-to-wafer bonding technology. In this way, a multi-layer wafer stacking structure 100 can be obtained, and each chip 30 to be bonded and stacked is functional, so that the wafer stacking structure 100 maintains a high yield.

[0081] Further, in order to solve the above problems, the second aspect of the present application provides a wafer stacking structure. Fig.19 , Fig.19 Schematic diagram of a wafer stacking structure provided for some embodiments of the present application. The wafer stacking structure 100 includes at least one first chip 110 and a functional wafer 120. In the present embodiment, a plurality of first chips 110 are provided and bonded in sequence to the functional wafer 120 to form a multi-layer stacking structure. The first chip 110 is obtained by cutting the above-mentioned first wafer stacking structure 10, and the first chip 110 corresponds to a chip area 12 with good function, that is, the first chip 110 is a chip with good function among the plurality of chips 30 obtained after cutting the above-mentioned first wafer stacking structure 10. In other words, the first wafer stacking structure 10 may include at least two first wafers 11 bonded together, and cutting the first wafer stacking structure 10 may obtain a plurality of chips 30, wherein a chip 30 with good function is selected from the chips 30 obtained by cutting as the first chip 110 to perform the subsequent operations described in the above-mentioned embodiments of the present application. In addition, those skilled in the art can understand that when cutting the first wafer stacking structure 10, each first wafer 11 in the first wafer stacking structure 10 is also cut into multiple grains 31 respectively, and the cut chip 30 and the first chip 110 are stacked by at least two grains 31 obtained by cutting the corresponding first wafer 11 in the first wafer stacking structure 10.

[0082] In some embodiments, one of the crystal grains 31 in the outer layer of the first chip 110 is formed with a tested test lead-out metal sheet 121. In some embodiments, the crystal grains 31 in the outer layer of the first chip 110 are used to be bonded with the functional wafer 120, or bonded with other adjacent first chips 110. In some embodiments, the functional wafer 120 is a logic wafer. In other embodiments, the functional wafer may also be a wafer that implements other functions.

[0083] Further, in order to solve the above problems, the third aspect of the present application provides a chip structure. Fig. 20 , Fig. 20Schematic diagram of a chip structure provided in some embodiments of the present application. The chip structure 200 includes at least one first chip 110. Similarly, the first chip 110 is obtained by cutting the above-mentioned first wafer stacking structure 10, and the first chip 110 corresponds to a well-functioning chip area 12, that is, the first chip 110 is a well-functioning chip. Similarly, the first chip 110 is formed by stacking at least two dies 31.

[0084] In some embodiments, a test lead-out metal sheet 121 is formed on one of the outer layers of the first chip 110 of the chip structure 200. In some embodiments, the chip structure 200 includes a functional die 210, and the functional die 210 is bonded to the outer layer die 31 of the first chip 110. When the chip structure 200 includes a plurality of first chips 110 bonded together, the outer layer die 31 of the first chip 110 is used to bond to the functional die 210, or to bond to other adjacent first chips 110. In some embodiments, the functional die 210 is a logic die. In other embodiments, the functional die may also be a die that implements other functions.

[0085] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A bonding method, characterized in that: include: Providing at least one first wafer stacking structure, and testing each chip region in the first wafer stacking structure; wherein the first wafer stacking structure comprises at least two first wafers bonded together; cutting the first wafer stack structure to form chips corresponding to the chip area; The chips that are determined to be functioning well by the test are bonded to a second wafer.

2. The bonding method according to claim 1, characterized in that: include: The providing at least one first wafer stacking structure and testing each chip region in the first wafer stacking structure comprises: bonding at least two of the first wafers together in sequence to form the first wafer stacking structure; forming a test pad on a first surface of the first wafer stacking structure, wherein the first surface is an outermost surface of the first wafer stacking structure perpendicular to a stacking direction; The chip region in the first wafer stacking structure is tested by the test pad to determine whether the corresponding chip region functions well.

3. The bonding method according to claim 2, characterized in that: The first wafer stacking structure comprises a top wafer located at an outermost side of the first wafer stacking structure perpendicular to the stacking direction, and a bottom wafer located at another outermost side and arranged opposite to the top wafer, the top wafer is reserved with a test lead-out metal sheet, and the first surface is away from the bottom wafer; The forming of a test pad on the first surface of the first wafer stack structure comprises: Opening a through hole in the dielectric layer on the top wafer in the first wafer stack structure to expose the test lead-out metal sheet; A connection structure is formed in the through hole, and the test pad is formed on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the bottom wafer, and the test pad is connected to the test lead-out metal sheet through the connection structure.

4. The bonding method according to claim 3, characterized in that: After testing the chip region in the first wafer stack structure by using the test pad, the bonding method further includes: removing the test pad and at least a portion of the connecting structure; The first surface is planarized.

5. The bonding method according to claim 1, characterized in that: The step of cutting the first wafer stack structure to form chips corresponding to the chip area includes: Temporarily bonding the first wafer stack structure to the carrier wafer; Cutting the first wafer stacking structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer; The chip is transferred to a wafer rack using the carrier wafer, and the carrier wafer is removed.

6. The bonding method according to claim 5, characterized in that: The step of temporarily bonding the first wafer stacking structure to the carrier wafer comprises: Bonding the first surface of the first wafer stacking structure to the carrier wafer as a bonding surface, wherein the first surface is an outermost surface of the first wafer stacking structure perpendicular to the stacking direction; After temporarily bonding the first wafer stack structure to the carrier wafer, the bonding method further comprises: The bottom wafer of the first wafer stacking structure is thinned until the through silicon vias in the bottom wafer and the metal columns in the through silicon vias are exposed, and the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

7. The bonding method according to claim 1, characterized in that: The step of bonding the chip having good functions determined by the test to a second wafer comprises: The plurality of chips having good functions determined by the test are bonded sequentially onto the second wafer using chip-to-wafer bonding technology.

8. A wafer stacking structure, characterized in that: include: Functional wafers; At least one first chip is bonded on the functional wafer, wherein the first chip comprises at least two crystal grains bonded together, and a test lead-out metal sheet is formed on one of the outer crystal grains of the first chip.

9. The wafer stacking structure according to claim 8, characterized in that: The first chip is obtained by cutting a first wafer stack structure, and corresponds to a chip area with good functions determined by testing in the first wafer stack structure; The outer layer die of the first chip is bonded to the functional wafer, or bonded to other adjacent first chips.

10. A chip structure, characterized in that: include: At least one first chip, the first chip includes at least two dies bonded together, and a test lead-out metal sheet is formed on one of the outer dies of the first chip.

11. The chip structure according to claim 10, characterized in that: The first chip is obtained by cutting a first wafer stack structure, and corresponds to a chip area with good functions determined by testing in the first wafer stack structure; The chip structure further includes a functional die, and the functional die is bonded to the outer layer die of the first chip.

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