Method and apparatus for constructing processing circuitry for target transform

Abstract

Embodiments of the present specification provide a method for constructing a processing circuit for a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes, for a K-point input coefficient sequence to be processed, determining a plurality of candidate decomposition points corresponding to a k-bit coefficient index. Then, starting from a low-bit decomposition point, for each candidate decomposition point, determining the minimum storage cost under each candidate decomposition point according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost evaluation function limits the storage cost to include the cost of a (n-p)th order first transform, the cost of a pth order second transform, and the local cost for inter-level rotation factor multiplication. According to the target decomposition mode, a corresponding memory for the rotation factor is allocated to form a processing circuit.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the present specification relate to optimization of hardware for accelerating polynomial multiplication, and in particular to optimization of rotation factor storage. BACKGROUND

[0002] Fast Fourier Transform (FFT) and Fast Number Theoretic Transform (NTT) are the most critical steps for accelerating polynomial multiplication, which have very broad application scenarios in the fields of communication and encryption. For example, FFT realizes the conversion between time domain and frequency domain when digital signal processing, and NTT and Negative Wrapped Convolution (NWC) using NTT accelerate polynomial multiplication under finite field in the design of fully homomorphic hardware acceleration chip.

[0003] At present, there are many implementations of FFT, NTT and their variants under different architectures, in which rotation factors need to be stored in advance, which greatly affects the memory overhead.

[0004] Therefore, it is desirable to have an improved scheme to reduce the storage cost of rotation factors. SUMMARY

[0005] One or more embodiments of the present specification describe a scheme for constructing a processing circuit for a target transform, which finds a target decomposition mode with the minimum storage cost and constructs a processing circuit accordingly, effectively saving the storage cost of rotation factors in the processing circuit, thereby effectively reducing the area of the processing circuit.

[0006] According to a first aspect, a method for constructing a processing circuit for a target transform is provided, the target transform being a discrete transform or its inverse transform based on rotation factors to transform an input coefficient sequence into an output coefficient sequence; the method comprising:

[0007] For a K-point input coefficient sequence to be processed, a plurality of candidate decomposition points corresponding to k-bit coefficient indexes are determined, wherein K is the k-th power of 2;

[0008] Starting from the low-bit decomposition point, for each candidate decomposition point, the minimum storage cost under each candidate decomposition point is determined according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, thereby determining the target decomposition mode of the k-bit coefficient index with the minimum storage cost; wherein the decomposition cost evaluation function defines that for an n-order target transform, the storage cost under a decomposition point p includes the storage cost of an (n-p) order first transform, the storage cost of a p order second transform, and the local storage cost for inter-level rotation factor multiplication, wherein the first transform and the second transform are each the target transform or its corresponding basis transform;

[0009] According to the target decomposition mode, a corresponding memory is allocated for the rotation factors to form the processing circuit.

[0010] In one embodiment, the first transform or the second transform is the target transform, and the minimum storage cost at each candidate decomposition point is determined by recursively decomposing the index bit number for several levels, comprising:

[0011] For the n-th target transform corresponding to the current candidate decomposition point, each candidate sub-decomposition point is traversed from low bit, and the storage cost at each sub-decomposition point is determined according to the decomposition cost evaluation function, and the minimum value thereof is taken as the minimum storage cost of the n-th target transform.

[0012] Further, in one example, the minimum storage cost at each sub-decomposition point is determined, and the minimum value thereof is taken as the minimum storage cost of the n-th target transform, comprising:

[0013] For the current sub-decomposition point p, the current storage cost is determined according to the decomposition cost evaluation function;

[0014] The current storage cost is compared with a first variable value, and if it is less than the first variable value, the first variable value is updated to the current storage cost; wherein the first variable value is used to store the minimum storage cost of the n-th target transform.

[0015] Further, in one example, for the current sub-decomposition point p, the current storage cost is determined according to the decomposition cost evaluation function, comprising:

[0016] The minimum storage cost of the (n-p)-th target transform is read as the storage cost of the (n-p)-th first transform, and / or the minimum storage cost of the p-th target transform is read as the storage cost of the p-th second transform, which is used to determine the current storage cost.

[0017] In one embodiment, the target transform is a fast Fourier transform FFT, and the first transform and the second transform are both target transforms; the local storage cost of the n-th target transform is 2 raised to the power of n-2, and the storage cost of the 1-st target transform is initialized to 0.

[0018] In one embodiment, the target transform is a fast number theory transform NTT, and the first transform and the second transform are both target transforms; the local storage cost of the n-th target transform is 2 raised to the power of n-1, and the storage cost of the 1-st target transform is initialized to 0.

[0019] In one embodiment, the target transform is an NTT transform obtained by fusing a pre-processing and a fast number theory transform NTT in a negative wrap convolution NWC; the first transform is the target transform, and the second transform is the NTT transform; the local storage cost of the n-th target transform is 2 raised to the power of n, and the storage cost of the 1-st target transform is initialized to 1.

[0020] In one embodiment, the target transform is an INTTP transform obtained by fusing an inverse fast number theory transform (INTT) with post-processing in a negative wrapped convolution (NWC); the first transform is an INTT transform, and the second transform is the target transform; the local storage cost of an n-order target transform is 2 raised to the power of n, and the storage cost of a first-order target transform is initialized to 1.

[0021] In one embodiment, the processing circuit further includes a butterfly operation unit and a twiddle factor multiplication unit; and the method further includes determining, according to the target decomposition manner, a calculation manner of a k-level basic butterfly operation and inter-stage twiddle factor multiplication, so as to determine a connection manner between the butterfly operation unit and the inter-stage twiddle factor multiplication unit.

[0022] In one embodiment, the processing circuit adopts a single-path delay feedback (SDF) pipeline architecture.

[0023] According to a second aspect, an apparatus for constructing a processing circuit for a target transform is provided, the target transform being a discrete transform or its inverse transform for transforming an input coefficient sequence into an output coefficient sequence based on a twiddle factor; the apparatus includes:

[0024] A first determining unit is configured to determine, for a K-point input coefficient sequence to be processed, a plurality of candidate decomposition points corresponding to a k-bit coefficient index, where K is 2 raised to the power of k;

[0025] A second determining unit is configured to determine, from a low-bit decomposition point, a target decomposition manner of the k-bit coefficient index with the minimum storage cost by recursively decomposing a number of index bits for each candidate decomposition point according to a decomposition cost evaluation function, so as to determine the target decomposition manner of the k-bit coefficient index with the minimum storage cost; where the decomposition cost evaluation function defines that, for an n-order target transform, a storage cost at a decomposition point p includes a storage cost of an (n-p)th-order first transform, a storage cost of a pth-order second transform, and a local storage cost for inter-stage twiddle factor multiplication, where the first transform and the second transform are each the target transform or a corresponding basic transform thereof.

[0026] A storage allocation unit is configured to allocate, according to the target decomposition manner, a corresponding memory for a twiddle factor, for forming the processing circuit.

[0027] According to a third aspect, a computing device is provided, including a memory and a processor, characterized in that the memory stores executable code, and the processor executes the executable code to implement the method of the first aspect.

[0028] In the embodiments of the present application, a method for constructing processing circuit for target transform is proposed. In the method, an evaluation function of storage cost of rotation factor of target transform under various decomposition manners is defined, and according to the function, a target decomposition manner with minimum storage cost is found by recursive decomposition, and a processing circuit is constructed according to the target decomposition manner. In this way, the storage cost of rotation factor in the processing circuit is effectively saved, and the area of the processing circuit is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0030] Figure 1a A schematic diagram of CT butterfly operation based on base 2 is shown;

[0031] Figure 1b A schematic diagram of performing FFT by CT butterfly operation based on base 2 in the case of N = 8 is shown;

[0032] Figure 2a A schematic diagram of a general pipeline stage based on SDF is shown;

[0033] Figure 2b A schematic diagram of a pipeline architecture for implementing a CT FFT of order 12 according to an embodiment is shown;

[0034] Figure 3a An example of 2-dimensional decomposition of an n-order FFT at a decomposition point p according to an embodiment is shown;

[0035] Figure 3b A schematic diagram of storage cost corresponding to a decomposition manner of Figure 3a according to an embodiment is shown;

[0036] Figure 3c A schematic diagram of storage cost obtained by further decomposing an example of Figure 3a according to an embodiment is shown;

[0037] Figure 4 Pseudo code for searching for minimum storage cost for a k-order FFT is shown;

[0038] Figure 5 A schematic diagram of a pipeline architecture for implementing a 12-order FFT according to an embodiment is shown;

[0039] Figure 6 Pseudo code algorithm of NWC operation is shown;

[0040] Figure 7 Pseudo code showing the algorithm to search for the minimum storage cost for k-th order NTT, NTTP and INTTP respectively;

[0041] Figure 8 Pseudo code showing the method flow chart for constructing processing circuit for target transform according to one embodiment;

[0042] Figure 9 Pseudo code showing the logical structure diagram of the circuit construction apparatus according to one embodiment. DETAILED DESCRIPTION

[0043] The schemes provided in the present specification are described below in conjunction with the accompanying drawings.

[0044] FFT (Fast Fourier Transform) is a widely used technique in digital signal processing, which significantly accelerates the calculation of DFT (Discrete Fourier Transform), and its calculation formula is as follows:

[0045]

[0046] where x i represents the input coefficient sequence, X o represents the output coefficient sequence, i and o are the indices of the input coefficient and the output coefficient respectively, and 0 <= i, o <= N-1.

[0047] The above N is the total number of each of the input and output coefficient sequences, and N is usually a power of 2, such as 1024 = 2^10.

[0048] The above is called a twiddle factor, where ω N is an N-point unit root, and the product value of i and o is a power of it. ω N is a special number that satisfies However, where 1 <= k < N. In the complex number field, we can usually set where j is the imaginary unit, i.e. j 2 = -1.

[0049] The twiddle factor has the following attractive properties:

[0050] (i) periodicity: since thus

[0051] (ii) semi-periodicity: since w2 = -1, thus

[0052] (iii) 1 / 4 periodicity: Since w4 = j, therefore

[0053] and Multiplication is often referred to as simple multiplication, which does not require actual multiplication operations, but only requires taking the negative number or swapping the real and imaginary parts.

[0054] To improve clarity and readability, in this embodiment, the input and output coefficient indices i and o are expressed in binary form, as shown in equation (2) below:

[0055]

[0056] Where n is the logarithm of N, base 2, rounded up. For example, when N is 1024, n = 10.

[0057] Therefore, the above formula (1) can be rewritten as the following formula (3):

[0058]

[0059] The FFT can be referred to as the N-point FFT, or the n-level or n-order FFT.

[0060] Several optimization schemes for FFT have been proposed, such as the Cooley-Tukey (CT) algorithm, which transforms the N-point FFT transformation into an n-level radix-2 butterfly operation, thereby effectively reducing the number of computations from N. 2 Reduced to N / 2 logN.

[0061] In the radix-2 CT algorithm, the input coefficients are decimated based on the least significant bit of index i. It can be rewritten as the following equation (4):

[0062]

[0063] X does not need to be calculated independently o and X o+N / 2 Instead, it can compute an FFT with two N / 2 coefficients: and Then through N / 2 Figure 1a The CT butterfly operation shown recovers all N / 2 pairs of X-rays. o and X o+N / 2 (0≤o<N / 2). Figure 1a The circle marked with an "o" indicates the rotation factor. Multiplication.

[0064] The analysis for equation (4) also applies to its sub-problems, i.e. the two N / 2-coefficient FFTs resulting from its decomposition: and can be further decomposed in the same way as equation (4). Based on the divide-and-conquer method, the final decomposition results in logN stages of N / 2-coefficient butterfly operations, for example Figure 1b as illustrated. Figure 1b A radix-2 CT FFT for N = 8 is given in dataflow representation, which shows 3 stages of 4 CT butterfly operations each. Since a butterfly operation consumes 2 inputs and produces 2 outputs, this algorithm is called radix-2 CT algorithm.

[0065] To efficiently implement various FFT algorithms, many processing circuit hardware architectures have been proposed, including pipelined architectures such as SDF (single-path delay feedback) pipelined architecture, etc. FFT implementations under pipelined architectures have the advantage of high throughput, and SDF pipelined architecture is a way of implementation that takes into account both area and throughput.

[0066] Figure 2a A general SDF pipelined stage is shown, which includes a FIFO (First-In-First-Out) memory for storing data to be delayed or reordered, a basic butterfly operation unit for the current stage, a twiddle factor multiplier for inter-stage, a ROM (Read-Only Memory) for storing twiddle factors, an address generator for generating the read address of the current twiddle factor, and a register REG, etc.

[0067] The SDF general pipelined stage shown in Figure 2a can be used to construct processing circuits for implementing various FFT algorithms of target point numbers.

[0068] For example, Figure 2b a SDF pipelined architecture for implementing a CT FFT transform of 2 12 point (also referred to as 12 stages or 12 orders) is shown, which has 12 basic butterfly operation units and 11 inter-stage twiddle factor multiplier operations. In addition, the memory above the basic butterfly operation unit corresponds to the FIFO memory in Figure 2a , and the memory below the multiplier operation represented by “*” corresponds to the ROM in Figure 2a for storing the values of the required twiddle factors calculated in advance.

[0069] For clarity and simplicity, Figure 2b the memory below the multiplier operation represented by “*” is not drawn in Figure 2aThe REG register and address generator in the memory below the multiplier are marked only with the I / O bit products used to generate the addresses of the corresponding twiddle factors (corresponding to the powers of the twiddle factors), that is, several bits in the input coefficient index i and the output coefficient index. The product of several digits in the equation.

[0070] like Figure 2b As shown, the power of the corresponding twiddle factor is displayed below the last (11th) inter-stage twiddle factor multiplier, i.e., the bit product of io is i0o. 10：0 In other words, the rotation factor required for this multiplication is It typically requires storage of 2 12 = 4096 rotation factors, which means it will occupy 4096 rotation factor storage units.

[0071] To reduce storage space usage, the properties of the aforementioned rotation factors, such as the semi-periodicity and quarter-periodicity brought about by w2=-1 and w4=j, can be utilized to reduce the number of rotation factors stored. Because as well as Therefore, it is sufficient to store only the values ​​of the twitch factors for k ∈ [0, N / 4). Thus, as... Figure 2b As shown, for the last (11th) inter-level twiddle factor multiplication operation, the actual 1024 twiddle factor storage units are used for... That's sufficient. Similarly, except for the special cases of the first and second multiplications, for the preceding m-th inter-level twiddle factor multiplication, 2 to the power of (m-1) twiddle factor storage units were used respectively. In the first multiplication, since w4 = j, a multiplier is not actually used; while in the second multiplication, only the value of ω8 needs to be stored.

[0072] therefore, Figure 2b The pipelined CT FFT processing circuit in the example uses a total of 2045 memory cells to store the rotation factor, but this still requires a significant amount of storage overhead. Further reductions in the storage cost of the rotation factor could effectively decrease the area of ​​the processing circuit implementing the FFT.

[0073] The foregoing discussion is not only applicable to FFT, but can be similarly applied to other FFT-like transforms, such as NTT (Number Theoretic Transform) which is a variant of FFT in finite field, and variants such as NTTP, INTTP, etc. in NWC (negative wrapped convolution). These transforms can be generalized as discrete transforms or their inverse transforms that transform an input coefficient sequence into an output coefficient sequence based on a twiddle factor. All the content discussed in this specification for FFT can be extended to these transforms with adaptive modification in some implementation details.

[0074] In view of this, in the embodiments of this specification, a scheme is proposed for constructing a processing circuit for a target transform, which is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a twiddle factor. In this scheme, an evaluation function of the storage cost of the twiddle factor of the target transform under various decomposition manners is defined, and according to this function, the target decomposition manner with the minimum storage cost is found through recursive decomposition, and the processing circuit is constructed accordingly. In this way, the storage cost of the twiddle factor in the processing circuit is effectively saved, thereby effectively reducing the area of the processing circuit.

[0075] To more clearly describe the scheme of the embodiments, first, the principle and implementation steps of the scheme are described taking FFT as an example.

[0076] The FFT represented by the foregoing formula (3) can be decomposed by the following formula (5):

[0077]

[0078] wherein, 1<=p<n. In formula (5), three sources of twiddle factors under this decomposition manner are also marked.

[0079] Specifically, in formula (5), the n-order FFT is decomposed into 2 p internal FFTs (which are (n-p)-order FFTs), 2 n-p external FFTs (which are p-order FFTs), and multiplication of 2 n points with a twiddle factor (which can also be referred to as inter-stage twiddle factor multiplication) between the internal FFT and the external FFT.

[0080] As shown in formula (5), under this decomposition manner, it can be considered that the n-bit coefficient index i is decomposed at the p-bit, into two index segments of p-bit and (n-p)-bit, and the corresponding external FFT and internal FFT are performed respectively.

[0081] This decomposition manner shown in formula (5) can be referred to as a decomposition manner obtained at a decomposition point p for an n-order FFT or n-bit coefficient index in the embodiments of the present specification.

[0082] Figure 3a A 2-dimensional decomposition diagram is used to intuitively represent the decomposition manner of formula (5) at the decomposition point p.

[0083] In Figure 3a , the vertical axis is sequentially from high to low n-bit of input coefficient index i from top to bottom, and the horizontal axis is sequentially from high to low n-bit of output coefficient index o from right to left, wherein the n-bit of i is decomposed at p bits, and the n-bit of o is also decomposed at (n-p) bits accordingly.

[0084] As Figure 3a shown, after decomposition, the highest (n-p) bits of i, i n-1:p , are subjected to internal (n-p) order FFT, the lowest p bits of i, i p-1:0 , are subjected to external p order FFT, and multiplication of the rotation factor of i p-1:0 o n-p-1:0 power, i.e., inter-stage rotation factor multiplication.

[0085] As shown in formula (5), the rotation factor of n order FFT at the decomposition point p has three sources: internal (n-p) order FFT, external p order FFT, and 2 n inter-stage rotation factor multiplications.

[0086] The storage cost of the rotation factor required by n order FFT can be defined as C FFT (n), the local storage cost required by inter-stage rotation factor multiplication is defined as L FFT (p, n-p). It should be understood that the "cost" or "storage cost" mentioned in the present specification refers to the storage cost of the rotation factor, which can be represented by the number of rotation factors required to be stored in some examples.

[0087] Therefore, the storage cost of n order FFT at the decomposition point p can be obtained as:

[0088] C FFT (n)=C FFT (n-p)+C FFT (p)+L FFT (p, n-p), (6)

[0089] which can be referred to as a decomposition cost evaluation function.

[0090] Correspondingly, Figure 3b the decomposition manner of Figure 3a is shown.

[0091] The above formula (5) and the decomposition technique shown in Figure 3a may be recursively applied to decompose the inner and outer FFTs until they are all decomposed into 1storder FFTs (i.e., 2-point FFTs, which are basic butterfly operations). That is, an n-thorder FFT is finally decomposed into n levels of basic butterfly operations and n-1 levels of secondary inter-stage twiddle factor multiplication operations.

[0092] Therefore, the above decomposition cost evaluation function can be recursively applied to calculate the storage cost of an n-thorder FFT under various decomposition manners, so as to find the decomposition manner with the minimum storage cost.

[0093] Figure 3c Exemplarily, the storage costs of the inner and outer FFTs in the decomposition manner of Figure 3a are further decomposed are respectively shown.

[0094] As shown in Figure 3c , the inner (n-p)-thorder FFT is similarly decomposed into an inner (n-p-q1)-thorder FFT, an outer q1-thorder FFT and 2 n-p inter-stage twiddle factor multiplications at a sub-decomposition point q1, so that its storage cost C FFT (n-p) becomes C FFT (n-p-q1)+C FFT (q1)+L FFT (q1,n-p-q1). Similarly, the outer p-thorder FFT is similarly decomposed into an inner (p-q2)-thorder FFT, an outer q2-thorder FFT and 2 p inter-stage twiddle factor multiplications at a sub-decomposition point q2, so that its storage cost C FFT (p) becomes C FFT (p-q2)+C FFT (q2)+L FFT (q2,p-q2).

[0095] By recursively decomposing the index bit number for several levels, all are finally decomposed into 1storder FFTs, so that the final storage cost can be recursively obtained.

[0096] As shown in the above formula (5), for an n-thorder FFT, the value of the decomposition point p can be in the interval of 1 to n-1. That is, the n-thorder FFT can have n-1 alternative decomposition points, and the storage cost under each alternative decomposition point can be different. The cost evaluation function of the above formula (6) can be used to calculate the cost under each alternative decomposition point, and then the minimum value is found as the storage cost C FFT (n) of the n-thorder FFT, and the decomposition manner corresponding to the minimum value is the target decomposition manner of the n-thorder FFT.

[0097] In each of the above alternative decomposition points, in the case where p or n-p is 1, since the 1st order FFT does not need to perform multiplication operation, the cost C FFT (1) = 0; while in the case where p or n-p is not 1, it can be further decomposed to 1st order FFT by recursion for several levels, so as to finally find the decomposition way with the minimum storage cost.

[0098] All the minimum costs C FFT (p) and their corresponding decomposition ways for p ∈ [1, n) can be searched and obtained in a bottom-up manner, and then the value of p is traversed, for example, p is scanned from 1 to n-1, the cost under each alternative decomposition point is calculated, so as to find the minimum cost C FFT (n) and its corresponding decomposition way.

[0099] In addition, regarding the local storage cost L FFT (p, n-p) of inter-stage rotation factor multiplication, the upper limit of the number of rotation factors that inter-stage multiplication needs to store is 2 n , but as mentioned before, it can be reduced to one fourth, i.e. 2 n-2 rotation factors, by using the semi-periodicity and 1 / 4 periodicity of FFT rotation factors. 2 n-2 is the upper limit value, and the number of rotation factors actually used will be different according to the number of io products corresponding to different decomposition points, but this actual number is complex, in order to simplify the cost calculation, L FFT (p, n-p) can also be directly taken as the upper limit value 2 n-2 .

[0100] Figure 4 Algorithm 1 shown by pseudo code gives an example of the method for searching the minimum storage cost for k order FFT.

[0101] As Figure 4 shown in the method example of algorithm 1, a bottom-up manner is adopted, i.e. starting from the low bit C FFT (2), the storage cost C FFT (k) of k order FFT of the target order is gradually calculated, wherein for each n order FFT, the cost under all decomposition points p is traversed, so as to find the minimum value as the final storage cost C FFT (n).

[0102] In line 1 of algorithm 1, the storage cost C FFT (1) of 1st order FFT is initialized to 0.

[0103] In line 5 of algorithm 1, the decomposition cost evaluation function (6) described above is used to calculate the cost TC FFTwhere the minimum storage cost of each lower order, i.e. each p and n-p order, has been calculated previously by Algorithm 1, so the minimum storage cost of the p and (n-p) order FFTs calculated previously is directly read as the storage cost C FFT (p), C FFT (n-p) respectively in the 5th row.

[0104] In addition, in the 6th row of Algorithm 1, the current storage cost T FFT C (n) is compared with the first variable value C FFT (n), if it is smaller than the current first variable value, the first variable value C FFT (n) is updated to the current storage cost T FFT ; otherwise the first variable value C FFT (n) remains unchanged, and in the 3rd row of Algorithm 1 the first variable value C FFT (n) is initialized to a maximum value. Thus it is guaranteed that the first variable value C FFT (n) always stores the minimum storage cost of the n order FFT at each decomposition point p that has been traversed.

[0105] Although only the storage costs C FFT (2) to C FFT (k) of the 2 to k order FFTs are returned in Algorithm 1 above, it should be understood that the values of the decomposition points p corresponding to these minimum storage costs respectively can also be returned, so that the decomposition points of minimum storage cost of each order FFT are obtained. Thus, using these decomposition points, the target decomposition way of minimum storage cost of the target k order FFT can be obtained by recursive decomposition of several levels.

[0106] The minimum storage costs of each order FFT and the values of the corresponding decomposition points obtained by Algorithm 1 above are given in Table 1 below.

[0107] Table 1

[0108]

[0109] “(n-p)+p” in Table 1 represents the decomposition way at decomposition point p or n-p (for FFT, the decomposition points p or n-p are symmetrical and have the same cost), “local cost” represents the local storage cost L FFT (p, n-p) of the inter-level rotation factor multiplication, and “total cost” represents the storage cost C FFT (n) of the n order FFT.

[0110] For a given n, the rotation factor storage cost of the n order FFT designed in the conventional design is 2 n-1For example, for n = 12, the traditional cost of FFT is 2048, but the optimized cost of the scheme of the embodiments of the present disclosure is 1060, as shown in Table 1, and the storage cost is reduced by (2048-1060) / 2048*100% = 48.24%.

[0111] In addition, the target decomposition mode with the minimum storage cost of each order FFT can be obtained from Table 1.

[0112] For example, for 12-order FFT, the decomposition point 6 can be used to obtain 6-order FFT + 6-order FFT, and then the sub-decomposition points 3 are used for the 6-order FFT to obtain 3-order FFT + 3-order FFT, and then the sub-decomposition points 1 or 2 are used for the 3-order FFT to obtain 1-order FFT + 2-order FFT, and then the 2-order FFT is decomposed to obtain 1-order FFT + 1-order FFT.

[0113] The entire FFT processing circuit can be designed according to the target decomposition mode obtained above, for example, the corresponding memory is allocated for the twiddle factor.

[0114] For example, the target decomposition mode obtained above can be used to change the SDF pipeline architecture of the 12-order FFT in the foregoing Figure 2b to the SDF pipeline architecture shown in Figure 5 The SDF pipeline architecture example is shown.

[0115] As shown in Figure 5 , compared with Figure 2b , with the change of the decomposition mode, the number of twiddle factors required by the multiplier between each stage also changes, and the number of storage spaces occupied by the memory under each multiplier also changes. As can be seen from Figure 5 , the number of required twiddle factors is significantly reduced from 2045 in Figure 2b to only 1060.

[0116] Figure 5 In , only the change of the memory allocated for the twiddle factor is shown for the sake of clarity and simplicity, but actually the data flow of the entire 12-stage basic butterfly operation and inter-stage twiddle factor multiplication has changed, and therefore some connection modes and the like also change accordingly.

[0117] As described above, the principles and schemes proposed above for FFT can be extended to other FFT-like transforms, such as NTT, NTTP, INTTP, etc. The application of the scheme of the embodiments of the present disclosure in NTT, NTTP, and INTTP will be discussed below.

[0118] NTT is a FFT variant in a finite field, and its calculation formula is as follows:

[0119]

[0120] where 0 <= i, o < N-1.

[0121] Compared with FFT, NTT has one more operation of modulo. Accordingly, the rotation factor ω N To satisfy But where 1 < k < N. The rotation factor of NTT has the periodicity and half-periodicity of the aforementioned FFT rotation factor, but does not have the 1 / 4 periodicity because w4 is no longer a special number.

[0122] Similar to FFT, the aforementioned NTT represented by equation (7) can be decomposed by the following equation (8):

[0123]

[0124] where 1 < p < n. In equation (8), three sources of rotation factors under this decomposition are also marked.

[0125] Similar to FFT, in equation (8), the n-order NTT is decomposed into 2 p internal NTTs (which are (n-p)-order NTTs), 2 n-p external NTTs (which are p-order NTTs), and inter-stage rotation factor multiplications between the internal NTTs and the external NTTs.

[0126] Similarly, the storage cost of the rotation factors required by the n-order NTT can be defined as C NTT (n), the local storage cost required by the inter-stage rotation factor multiplication can be defined as L NTT (p, n-p). Therefore, the storage cost of the n-order NTT at the decomposition point p can be obtained as:

[0127] C NTT (n) = C NTT (n-p) + C NTT (p) + L NTT (p, n-p) (9)

[0128] Because the NTT rotation factor no longer has the 1 / 4 periodicity, the upper limit of the number of rotation factors required to be stored by the inter-stage multiplication can only be reduced to 2 n-1 . Therefore, L NTT (p, n-p) can all take the upper limit value 2 n-1 . C NTT (1) is still 0.

[0129] Similar to the FFT, the above formula (8) can be applied recursively to index bit decomposition of several levels for the n-order NTT until it is finally decomposed into 1-order NTT. Therefore, the above decomposition cost evaluation function (9) can be applied recursively to calculate the storage cost of the n-order NTT under various decomposition modes, so as to find the decomposition mode with the minimum storage cost.

[0130] In addition to replacing 2 n-2 with 2 n-1 , the algorithm 1 for the FFT shown in the foregoing Figure 4 can also be applied to the NTT.

[0131] The following refers to Figure 6 , which introduces the operation of the NWC with pseudo code, and provides an effective method for calculating the polynomial product c(x).

[0132] In the calculation process shown in Figure 6 , a(x) and b(x) are polynomials in , and their coefficients are a N-1 to a0 and b N-1 to b0, where a i , b i ∈[0, q). The polynomial multiplication of a(x) and b(x) needs to find a polynomial c(x) with N coefficients, so that where 0≤o<N.

[0133] In addition to the standard operation in the third row, the NWC also needs an additional preprocessing step, in which a(x) and b(x) need to be multiplied with . In addition, after the inverse NTT (INTT), there is a similar post-processing step, which involves multiplying with .

[0134] In order to speed up the operation, the preprocessing step can be integrated into the NTT, and the post-processing step can be integrated into the INTT.

[0135] For the sake of simplicity, the embodiments of the present specification introduce NTTP to represent the transformation obtained by integrating the preprocessing into the NTT in the NWC, and introduce INTTP to represent the transformation obtained by integrating the INTT into the post-processing in the NWC, as follows:

[0136]

[0137] Substituting the calculation formula of the NTT and the INTT respectively, the NTTP and the INTTP transformation can be changed into the following formula respectively:

[0138]

[0139] where 0 <= i, o < N-1.

[0140] The computational framework of the NTTP and the INTTP is similar to that of the FFT and the NTT described above, except for the constant 1 / N.

[0141] Therefore, similar to the FFT and the NTT described above, the NTTP represented by the aforementioned equation (10) can be decomposed by the following equation (12):

[0142]

[0143] and the INTTP represented by the aforementioned equation (11) can be decomposed by the following equation (13) (where the constant 1 / N is omitted):

[0144]

[0145] where 1 <= p < n.

[0146] In equation (12), an n-th order NTTP is decomposed into 2 p internal NTTPs (which are (n-p)-th order NTTPs), 2 n-p external NTTs (which are p-th order NTTs), and inter-stage twiddle factor multiplications between the internal NTTPs and the external NTTs.

[0147] In equation (13), an n-th order INTTP is decomposed into 2 p internal INTTs (which are (n-p)-th order INTTs), 2 n-p external INTTPs (which are p-th order INTTPs), and inter-stage twiddle factor multiplications between the internal INTTs and the external INTTPs.

[0148] The storage cost of the twiddle factors required for an n-th order INTT, an n-th order NTTP, and an n-th order INTTP can be defined as C INTT (n), C NTTP (n), and C INTTP (n), respectively, and the local storage cost of the inter-stage twiddle factor multiplications required for an n-th order NTTP and an n-th order INTTP can be defined as L NTTP (p, n-p) and L INTTP (p, n-p), respectively.

[0149] Therefore, the storage cost of an n-th order NTTP and an n-th order INTTP at a decomposition point p can be obtained as follows:

[0150] C NTTP (n) = C NTTP (n-p) + C NTT (p) + LNTTP (p, n - p) (14)

[0151] C INTTP (n) = C INTT (n - p) + C INTTP (p) + L INTTP (p, n - p) (15)

[0152] Since the base of the rotation factor in the NTTP and INTTP transform is 2 n+1 instead of 2 in the previous NTT n , the upper limit of the number of rotation factors that need to be stored in the inter-stage multiplication becomes 2 n . Therefore, L NTTP (p, n - p) and L INTTP (p, n - p) can both take the upper limit value of 2 n . Also, C NTTP (1) and C INTTP (1) also correspondingly become 1, i.e. one rotation factor needs to be stored in the 1st order NTTP and INTTP transform.

[0153] Similar to the FFT, the above equations (12) and (13) can be recursively applied to perform several levels of index bit decomposition for the n-th order NTTP and n-th order INTTP respectively, until they are finally decomposed into 1st order transforms. Correspondingly, the above decomposition cost evaluation functions (14) and (15) can be recursively applied to calculate the storage cost of the n-th order NTTP and n-th order INTTP under various decomposition manners, so as to find the decomposition manner with the minimum storage cost.

[0154] However, as shown in the above equations (14) and (15), the decomposition cost functions of the n-th order NTTP and n-th order INTTP also involve the cost of lower order NTTs or INTTs, which can be proved to be the same, i.e. C NTT (n) = C INTT (n), so the storage cost of each lower order NTT also needs to be pre-calculated using the algorithm for NTT.

[0155] Thus, the algorithm 1 for FFT shown in Figure 4 can be modified to obtain the algorithm 2 shown in Figure 7 , which is used to search for the minimum storage cost for k-th order NTT, NTTP and INTTP respectively.

[0156] Similar to the algorithm 1, in the method example of the algorithm 2, a bottom-up manner is adopted, i.e. from the low bits C NTT (2), C NTTP (2) and C INTTP(2) Start, gradually calculate the storage cost C of k-th NTT, NTTP and INTTP to the target order NTT (k), C NTTP (k) and C INTTP (k), wherein for each n-th NTT, NTTP and INTTP, all the costs under all the decomposition points p are traversed respectively to find the minimum value as its final storage cost C NTT (n), C NTTP (n) and C INTTP (n).

[0157] The specific steps of algorithm 2 are similar to the aforementioned algorithm 1, and only the initialization value of the 1st order transformation, the decomposition cost evaluation function, and the value of the local cost are adaptively modified according to the previous relevant discussion.

[0158] Similarly, the minimum storage cost of each order NTT, NTTP and INTTP and the value of the corresponding decomposition point obtained by algorithm 2 are listed in Table 2 below.

[0159] Table 2

[0160]

[0161] “(n-p)+p” in Table 2 represents the decomposition mode of each n-th transformation under the decomposition point p (but for NTT, the decomposition points p or n-p are symmetrical, and the cost is the same), “local cost” represents the local storage cost of the inter-stage rotation factor multiplication of each n-th transformation, and “total cost” represents the storage cost of each n-th transformation.

[0162] For a given n, the storage cost of each n-th transformation under the conventional design is respectively: (1) NTT needs to store 2 n storage factors; (2) NTTP and INTTP both need to store 2 n+1 storage factors.

[0163] Taking n = 12 as an example,

[0164] (1) The conventional cost of NTT is 4096, but as shown in Table 2, the optimized cost of the scheme of the embodiment of the present specification is 2132, and the storage cost is reduced by (4096-2132) / 4096*100% = 47.95%;

[0165] (2) The conventional cost of NTTP and INTTP is 8192, but as shown in Table 2, the optimized cost of the scheme of the embodiment of the present specification is 4217, and the storage cost is reduced by (8192-4217) / 8192*100% = 48.52%.

[0166] Based on the basic principles and inventive concepts of the specific solutions implemented in the embodiments of this specification for FFT, NTT, NTTP, and INTTP transforms described above, a general solution can be obtained, for example... Figure 8 As shown, it is generally applicable to similar application scenarios and effectively saves the storage cost of the rotation factor.

[0167] Figure 8 A flowchart illustrating a method for constructing a processing circuit for a target transformation according to one embodiment is shown. The target transformation is a discrete transformation or its inverse transformation that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor, and the processing circuit is designed to perform this target transformation. Figure 8 The method shown includes the following steps:

[0168] Step S81: For the K-point input coefficient sequence to be processed, determine multiple candidate decomposition points corresponding to the k-digit coefficient indices, where K is a power of 2; thus, this target transformation can also be called a k-order target transformation.

[0169] Step S82: Starting from the lowest decomposition point, for each candidate decomposition point, according to the decomposition cost evaluation function, through a recursive decomposition of several levels of index bits, determine the minimum storage cost for each candidate decomposition point, thereby determining the target decomposition method with the minimum storage cost of the k-bit coefficient index; wherein, the decomposition cost evaluation function limits that, for the n-order target transformation, the storage cost at decomposition point p includes the storage cost of the (np)-order first transformation, the storage cost of the p-order second transformation, and the local storage cost for inter-level rotation factor multiplication, wherein the first transformation and the second transformation are each the target transformation or its corresponding basic transformation.

[0170] Step S83: According to the target decomposition method, allocate corresponding memory for the rotation factor to form the processing circuit.

[0171] The following section describes the execution of the above steps in detail with specific examples.

[0172] In step S81, for the k-th order target transformation, any number of values ​​in the interval [1, k-1] can be selected as candidate decomposition points. For example, as shown in Algorithms 1 and 2 above, the interval [1, k-1] can be traversed, meaning the candidate decomposition points include all integer values ​​from 1 to k-1. However, in some examples, due to the symmetry of the decomposition costs of FFT and NTT, i.e., the costs at decomposition points p and kp are equal, all integer values ​​from 1 to k / 2 can be taken as candidate decomposition points. In other examples, the values ​​of the candidate decomposition points can also be selected based on other considerations.

[0173] Then, in step S82, the minimum cost under each candidate decomposition point can be calculated in ascending order according to the decomposition cost evaluation function, and then the minimum value among them is obtained as the minimum cost of the k-th target transform, and the decomposition manner corresponding to the minimum cost is the target decomposition manner.

[0174] For example, in the current candidate decomposition point n, the decomposition cost evaluation function defines the current cost as the sum of the cost of decomposing the corresponding (k-n)th first transform, the cost of the n-th second transform, and the local cost for the k-th target transform.

[0175] In some of the foregoing examples, the local cost can be a preset numerical value, and to determine the minimum value of the current cost, the minimum value of the cost of the (k-n)th first transform and the n-th second transform needs to be determined first. It should be understood that the preset numerical value as the local cost is not limited to the upper limit value in the foregoing examples, and in some cases, the numerical value of the local cost can also be calculated in advance according to the actual situation.

[0176] In the case of the target transform being FFT or NTT, the first and second transforms are both the target transform itself. In the case of (k-n) or n being 1, the initialized value can be obtained directly, i.e., C FFT (1) or C NTT (1) = 0; and in the case of (k-n) or n not being 1, since the minimum cost value is not yet known, the minimum storage cost can be determined by recursively decomposing several levels of index bits until the decomposition is to the 1st FFT or NTT.

[0177] For example, for the n-th target transform corresponding to the current candidate decomposition point, similar to the foregoing k-th target transform, each candidate sub-decomposition point is traversed from low bits, and the storage cost under each sub-decomposition point is determined according to the decomposition cost evaluation function, and then the minimum value thereof is taken as the minimum storage cost of the n-th target transform; if the minimum value of the cost of the first or second transform corresponding to the current sub-decomposition is still unknown, the decomposition of the first or second transform is continued until the decomposition is to the known 1st transform. It should be understood that in other examples, the storage cost values of more orders of target transforms can also be initialized as needed, for example, the minimum cost values of 2nd or 3rd FFT or NTT are preset, and the terminal point of the recursive decomposition of higher order FFT or NTT can also include 2nd or 3rd FFT or NTT, etc.

[0178] In some examples, as described in the foregoing Algorithm 1 and Algorithm 2, for each n-order target transform, the current storage cost TC can be determined according to the decomposition cost evaluation function for the current sub-decomposition point p of the n-order target transform; the current storage cost TC is compared with the first variable value C, and if the current storage cost TC is smaller than the first variable value, the first variable value is updated as the current storage cost, i.e., C = min(TC, C), so that the minimum storage cost of the n-order target transform is obtained after all the sub-decomposition points are traversed.

[0179] In some examples, for each n-order target transform, the minimum cost of each low-order target transform can be determined in advance by the foregoing manner, and then the minimum cost of the current n-order target transform is determined. For example, as described in the foregoing Algorithm 1 and Algorithm 2, the minimum cost C of all p ∈ [1, n) can be obtained by using the step S82 from bottom to top. FFT (p) and the corresponding decomposition mode, and then the value of p is traversed, for example, p is scanned from 1 to n-1, the cost of each sub-decomposition point p of the n-order target transform is calculated, and thus the minimum cost C of the current n-order target transform is found. FFT (n) and the corresponding decomposition mode.

[0180] In the case where the minimum cost of each low-order target transform has been calculated in advance, when the storage cost of the current sub-decomposition point p is determined, the minimum storage cost of the (n-p) -order target transform can be read as the storage cost of the (n-p) -order first transform, and the minimum storage cost of the p-order target transform can be read as the storage cost of the p-order second transform.

[0181] In the case where the target transform is an NTTP transform, the first transform is the target transform itself and the second transform is an NTT; in the case where the target transform is an INTTP transform, the first transform is an INTT and the second transform is the target transform itself. Therefore, in addition to calculating the minimum cost value of each low-order target transform similarly as in the foregoing FFT or NTT case, the minimum cost value of each low-order NTT also needs to be obtained. The minimum cost value of each low-order NTT can be calculated in advance by using the foregoing example methods, and the calculated value of each-order NTT can be directly read when the cost of the NTTP transform or the INTTP transform is calculated.

[0182] Then, in step S83, the processing circuit can be constructed by using, for example, the SDF pipeline architecture shown in Figure 2a and Figure 5 It should be understood that the embodiments of the present specification are not limited to the SDF pipeline architecture, and the processing circuit can also be implemented by using other architectures, for example, other pipeline architectures.

[0183] The processing circuit can include a butterfly operation unit, a twiddle factor multiplication unit, and a memory for storing twiddle factors. In some of the foregoing examples, according to the target decomposition manner obtained in step S82, the calculation manner of the k-level basic butterfly operation and the inter-level twiddle factor multiplication can be determined, in addition to the corresponding memory for the twiddle factors being allocated accordingly, the connection manner between the butterfly operation unit and the inter-level twiddle factor multiplication unit in the processing circuit, etc. can also be determined.

[0184] As previously described, in the embodiments of the present specification, by searching for a target decomposition manner with the minimum storage cost and constructing a processing circuit accordingly, the storage cost of twiddle factors in the processing circuit can be effectively saved, thereby effectively reducing the area of the processing circuit.

[0185] According to another aspect, embodiments provide a device for constructing a processing circuit for a target transform, wherein the target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on twiddle factors. Figure 9 A logical structure diagram of a circuit construction device according to an embodiment is shown. It can be understood that the device can be implemented by any device, platform or device cluster with data storage, calculation and processing capabilities. As shown, the circuit construction device 900 includes: Figure 9

[0186] A first determination unit 91 is configured to determine a plurality of candidate decomposition points corresponding to a k-bit coefficient index for a K-point input coefficient sequence to be processed, wherein K is a k-th power of 2;

[0187] A second determination unit 92 is configured to determine, from a low-bit decomposition point, the minimum storage cost of each candidate decomposition point by recursive index-bit decomposition according to a decomposition cost evaluation function for each candidate decomposition point, thereby determining a target decomposition manner of the k-bit coefficient index with the minimum storage cost; wherein the decomposition cost evaluation function defines that, for an n-order target transform, the storage cost of a decomposition point p includes the storage cost of an (n-p) order first transform, the storage cost of a p order second transform, and the local storage cost for inter-level twiddle factor multiplication, wherein the first transform and the second transform are each the target transform or a corresponding basic transform thereof;

[0188] A storage allocation unit 93 is configured to allocate corresponding memory for the twiddle factors according to the target decomposition manner, for forming the processing circuit.

[0189] For examples of specific implementations of the circuit construction device 900, please refer to the foregoing examples and descriptions in conjunction with the circuit construction method, which will not be repeated here.

[0190] ​According to another aspect, embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the above-mentioned circuit construction method.

[0191] According to yet another aspect, embodiments also provide a computer program product comprising computer programs / instructions which, when executed by a processor, implement the above-mentioned circuit construction method.

[0192] According to still another aspect, embodiments also provide a computing device comprising a memory and a processor, the memory having stored therein executable code which, when executed by the processor, implements the above-mentioned circuit construction method.

[0193] Those skilled in the art should be aware that, in the above-mentioned one or more examples, the functions described in the present application can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium.

[0194] The above detailed description merely describes the specific implementation of the present application. It is to be understood that the above description is only used to explain the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the present application shall be included in the protection scope of the present application.

Claims

1. A method for constructing a processing circuit for a target transformation, wherein the target transformation is a discrete transformation or its inverse transformation that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor; The method includes: For the K-point input coefficient sequence to be processed, determine multiple candidate decomposition points corresponding to the k-digit coefficient indices, where K is a power of 2; Starting from the lowest decomposition point, for each candidate decomposition point, the minimum storage cost is determined through a recursive decomposition of several levels of index bits based on the decomposition cost evaluation function. This determines the target decomposition method with the minimum storage cost for the k-bit coefficient index. The decomposition cost evaluation function specifies that, for an n-order target transformation, the storage cost at decomposition point p includes the storage cost of the (np)-order first transformation, the storage cost of the p-order second transformation, and the local storage cost for inter-level rotation factor multiplication. The first and second transformations are each the target transformation or its corresponding basic transformation. According to the target decomposition method, corresponding memory is allocated to the rotation factor to form the processing circuit; wherein, the minimum storage cost at each candidate decomposition point is determined through a recursive multi-level index bit decomposition, including: For the nth-order target transformation corresponding to the current candidate decomposition point, each candidate sub-decomposition point is traversed starting from the least significant bit. Based on the decomposition cost evaluation function, the storage cost under each sub-decomposition point is determined, and the minimum value is taken as the minimum storage cost of the nth-order target transformation.

2. The method according to claim 1, wherein, Determine the storage cost at each sub-decomposition point, and take the minimum value as the minimum storage cost of the nth-order objective transformation, including: For the current sub-decomposition point q, the current storage cost is determined according to the decomposition cost evaluation function; The current storage cost is compared with the value of the first variable. If the current storage cost is less than the value of the first variable, the value of the first variable is updated to the current storage cost. The value of the first variable is used to store the minimum storage cost of the nth-order target transformation.

3. The method according to claim 2, wherein, For the current sub-decomposition point q, the current storage cost is determined according to the decomposition cost evaluation function, including: The minimum storage cost of the (nq)th order target transformation is read as the storage cost of the (nq)th order first transformation, and / or the minimum storage cost of the qth order target transformation is read as the storage cost of the qth order second transformation, to determine the current storage cost.

4. The method according to any one of claims 1-3, wherein, The target transformation is a Fast Fourier Transform (FFT), and both the first and second transformations are target transformations. The local storage cost for the nth-order target transformation is 2 raised to the power of n-2, and the storage cost for the first-order target transformation is initialized to 0.

5. The method according to any one of claims 1-3, wherein, The target transformation is the Fast Number Theory Transform (NTT), and both the first and second transformations are target transformations. The local storage cost for the nth-order target transformation is 2 raised to the power of n-1, and the storage cost for the first-order target transformation is initialized to 0.

6. The method according to any one of claims 1-3, wherein, The target transform is the NTTP transform obtained by fusing preprocessing and the fast number-theoretic transform (NTT) in negative wrap convolution (NWC); the first transform is the target transform, and the second transform is the NTT transform; the local storage cost for the nth-order target transform is a power of 2, and the storage cost for the first-order target transform is initialized to 1.

7. The method according to any one of claims 1-3, wherein, The target transform is the INTTP transform obtained by fusing the inverse fast number theory transform (INTT) with post-processing in negative wrap convolution (NWC); the first transform is the INTT transform, and the second transform is the target transform; the local storage cost for the nth-order target transform is a power of 2, and the storage cost for the 1st-order target transform is initialized to 1.

8. The method according to claim 1, wherein, The processing circuit further includes a butterfly operation unit and a rotation factor multiplication unit; the method further includes determining the calculation method of k-level basic butterfly operations and inter-level rotation factor multiplications according to the target decomposition method, thereby determining the connection method between the butterfly operation unit and the rotation factor multiplication unit.

9. The method according to claim 1, wherein, The processing circuit adopts a single-path delay feedback (SDF) pipeline architecture.

10. An apparatus for constructing a processing circuit for a target transformation, wherein the target transformation is a discrete transformation or its inverse transformation that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor; The device includes: The first determining unit is configured to input a coefficient sequence of K points to be processed and determine multiple candidate decomposition points corresponding to the k-bit coefficient indices, where K is a power of 2. The second determining unit is configured to, starting from the lowest decomposition point, sequentially determine the minimum storage cost for each candidate decomposition point through a recursive multi-level index bit decomposition based on the decomposition cost evaluation function, thereby determining the target decomposition method with the minimum storage cost for the k-bit coefficient index. The decomposition cost evaluation function specifies that, for an n-order target transformation, the storage cost at decomposition point p includes the storage cost of the (np)-order first transformation, the storage cost of the p-order second transformation, and the local storage cost for inter-level rotation factor multiplication. The first and second transformations are each the target transformation or their corresponding base transformations. Determining the minimum storage cost for each candidate decomposition point through a recursive multi-level index bit decomposition includes: for the n-order target transformation corresponding to the current candidate decomposition point, traversing each candidate sub-decomposition point starting from the lowest bit, determining the storage cost at each sub-decomposition point according to the decomposition cost evaluation function, and taking the minimum value as the minimum storage cost of the n-order target transformation. The storage allocation unit is configured to allocate corresponding memory to the rotation factor according to the target decomposition method, for forming the processing circuit.

11. A computing device, comprising a memory and a processor, characterized in that, The memory stores executable code, and when the processor executes the executable code, it implements the method of any one of claims 1-9.

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