A FPGA-based SpaceWire bus network time delay measurement method and device

Abstract

A kind of SpaceWire bus network time delay measurement method and device based on FPGA, SPW-EOP interrupt module is added in the interface controller of SpaceWire bus time delay network, and connect time delay measurement FPGA module, data sending end host CPU controls interface controller to send variable length data packet according to fixed cycle, when the end of each data packet leaves the host interface of interface controller, SPW-EOP interrupt module is triggered to generate interrupt signal, and is sent to time delay measurement FPGA;Data packet is forwarded to receiving end interface controller through SpaceWire bus, also triggers the interrupt signal generated by the SPW-EOP interrupt module of interface controller, and is sent to time delay measurement FPGA;Time delay measurement FPGA calculates transmission time delay in interrupt signal.This application realizes high-precision measurement of SpaceWire link data transmission delay on physical layer, and the measured data is accurate and has strong universality, and the measurement method is efficient, which provides reliable basis for time planning of spacecraft data transmission task.

Description

TECHNICAL FIELD

[0001] The application relates to an FPGA-based SpaceWire bus network time delay measurement method and device, and belongs to the field of spacecraft communication buses. BACKGROUND

[0002] The SpaceWire bus can provide high-reliable high-speed communication functions in extreme environments. With the increasingly wide application of the SpaceWire bus in spacecrafts with complex structures and high data transmission requirements, the delay and transmission rate of the network gradually become the focus. Because the SpaceWire bus supports a communication rate of 2 to 300 Mbps, the load rate and frequency of different nodes in the network are quite different, which can easily cause some paths to be overloaded or even blocked, thereby causing significant delay problems and affecting the time planning of the entire network. At present, there are many engineering solutions for the time planning of the SpaceWire network, but most of them are based on the worst delay calculated by a theoretical model, and there is a large error with the actual situation. Some test systems related to the SpaceWire bus mainly test through the application layer or the network layer, but because the real-time performance of these layers is poor, the delay data obtained has a large error. And directly affected by the processing delay of different types of host systems, the hardware delay of the SpaceWire network cannot be directly reflected, and the universality is poor. The method of testing the time delay through the redundancy of data packet bytes is affected by the cross-clock domain, and the accuracy is limited, and the data transmission efficiency of the SpaceWire bus is directly reduced. SUMMARY

[0003] The technical problem of the application is to overcome the shortcomings of the prior art and provide an FPGA-based SpaceWire bus network time delay measurement method and device. The SpaceWire bus data transmission time delay is tested from the physical layer based on the SPW-EOP trigger interrupt mode, the measurement accuracy is extremely high, and the SpaceWire bus data transmission efficiency is not affected. The host system processing delay is separated, and the time analysis and planning of the SpaceWire network composed of different host systems can be applied, and the measurement result has strong universality. Based on the FPGA, the automatic testing of a large number of different length data packet transmission time delays is realized, and the measurement efficiency is high.

[0004] The technical solution of the application is: in a first aspect, a SpaceWire bus network time delay measurement method based on FPGA is provided, wherein the SpaceWire bus network comprises: a first node host CPU, a first node high-speed SpaceWire interface controller, a high-speed SpaceWire router, a second node high-speed SpaceWire interface controller, and a second node host CPU, which are connected in sequence; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the second node high-speed SpaceWire interface controller are connected through a SpaceWire bus;

[0005] The measurement method comprises:

[0006] SPW-EOP interrupt modules are added to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller;

[0007] A time delay measurement FPGA module is connected in the SpaceWire bus network,

[0008] The first node host CPU controls the first node high-speed SpaceWire interface controller to cyclically send variable-length data packets at a fixed period, and when the packet tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller, the SPW-EOP interrupt module generates a sending node SPW-EOP interrupt signal and sends it to the time delay measurement FPGA module;

[0009] The data packet is transmitted along the SpaceWire bus to the high-speed SpaceWire router, and then forwarded to the second node high-speed SpaceWire interface controller through the SpaceWire bus;

[0010] When the packet tail of each data packet enters the host interface of the second node high-speed SpaceWire interface controller, the SPW-EOP interrupt module of the second node high-speed SpaceWire interface controller generates a receiving node SPW-EOP interrupt signal and sends it to the time delay measurement FPGA module;

[0011] The time delay measurement FPGA module cyclically collects and synchronizes the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, and records the values of the FPGA counters corresponding to the arrival of the two SPW-EOP interrupt signals, which are multiplied by the FPGA clock period to obtain the arrival time stamp of the corresponding signal. The time difference between the two time stamps is calculated to obtain the transmission time delay and stored in the BRAM of the time delay measurement FPGA module.

[0012] Preferably, the time delay measurement FPGA module comprises: a time delay measurement FPGA and a measurement node host CPU connected to the time delay measurement FPGA; the time delay measurement FPGA is connected to a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller respectively, and the measurement node host CPU is further connected to a PC.

[0013] The measurement node host CPU reads data in the BRAM of the time delay measurement FPGA and transmits the data to the PC, and the time delay data is saved and analyzed in the PC.

[0014] Preferably, the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller are provided with a SPW-EOP interrupt module.

[0015] Preferably, the SPW-EOP interrupt module comprises a SPW-EOP module and an interrupt controller, and specifically:

[0016] When the end of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller, the interrupt control register of the SPW-EOP module is enabled to allow the initiation of an interrupt application;

[0017] The SPW-EOP interrupt module compares the characters in the data packet with the standard packet end character "<" of the SpaceWire protocol. <xxxxxxx0>":

[0018] If not, continue to determine;

[0019] If consistent, the SPW-EOP module sends an interrupt application to the interrupt controller, sets the corresponding position in the interrupt status register to 1; the interrupt controller generates an interrupt signal, outputs a high level to the time delay measurement FPGA through the interrupt pin, and completes the sending of the interrupt signal.

[0020] Preferably, the FPGA sampling frequency is not less than 2 times the highest SPW-EOP interrupt signal frequency.

[0021] Preferably, the high-speed SpaceWire in the SpaceWire bus network can be cascaded for one or two levels.

[0022] Preferably, the process of FPGA collecting and timing the SPW-EOP interrupt signal is cyclically and parallelly running.

[0023] The worst time error of FPGA collecting and synchronizing signals is not more than 8ns.

[0024] Preferably, the measurement node host CPU communicates with the host PC through the UART serial communication protocol.

[0025] Preferably, the first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the SpaceWire bus run at a speed range of 2-300MHz.

[0026] In the second aspect, a FPGA-based SpaceWire bus network time delay measurement device is provided, comprising: an SPW-EOP interrupt module arranged in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller of the SpaceWire bus network, and a time delay measurement FPGA module; wherein:

[0027] The time delay measurement FPGA module comprises: a time delay measurement FPGA, and a measurement node host CPU connected to the time delay measurement FPGA; the time delay measurement FPGA is connected to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller at both ends, and the measurement node host CPU is connected to the host PC at the same time.

[0028] The SPW-EOP interrupt module comprises an SPW-EOP module and an interrupt controller; the SPW-EOP interrupt module enables an interrupt control register in the SPW-EOP interrupt module when a packet tail of each data packet leaves a host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller, and allows to initiate an interrupt application; the SPW-EOP interrupt module compares a character in the data packet with a standard packet tail character "<" stipulated in the SpaceWire protocol, and if the character is not the standard packet tail character "<", the SPW-EOP interrupt module generates an interrupt signal to the host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller. <xxxxxxx0>If not, continue to judge; if yes, the SPW-EOP module sends an interrupt application to the interrupt controller, sets the corresponding position in the interrupt status register to 1, the interrupt controller generates an interrupt signal and outputs a high level to the time delay measurement FPGA through the interrupt pin, thus completing the sending of the interrupt signal.

[0029] Compared with the prior art, the present application has the following advantages:

[0030] (1) The present application tests the SpaceWire bus data transmission time delay from the physical layer by the way of SPW-EOP triggered interrupt, has very high measurement accuracy and does not affect the original data transmission efficiency of the SpaceWire network;

[0031] (2) The time delay parameter measured by the present application separates the host system processing delay, and can be applied to the time analysis and planning of the SpaceWire network composed of different host systems;

[0032] (3) The automatic test device of the present application can continuously measure the delay of data packets of different lengths in large quantities, greatly saving the manual test time. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 Fig. 1 is a schematic diagram of the SpaceWire bus time delay measurement device of the present application; wherein (a) is a schematic diagram of a 1-level router cascade network, (b) is a schematic diagram of a 2-level router cascade network,

[0034] Figure 2 Fig. 3 is a working flow chart of the SPW-EOP interrupt module of the present application;

[0035] Figure 3 Fig. 4 is a working flow chart of the FPGA time delay measurement module of the present application;

[0036] Figure 4 Fig. 5 is a time delay measurement result diagram of the present application. DETAILED DESCRIPTION

[0037] A SpaceWire bus network time delay measurement method based on FPGA, specifically comprising the following steps:

[0038] The time delay measurement FPGA module is connected in a SpaceWire bus network, and the SpaceWire bus network comprises: a first node host CPU, a first node high-speed SpaceWire interface controller, a high-speed SpaceWire router, a second node high-speed SpaceWire interface controller, and a second node host CPU, which are sequentially connected; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the second node high-speed SpaceWire interface controller are connected through a SpaceWire bus.

[0039] The time delay measurement FPGA module comprises: a time delay measurement FPGA, and a measurement node host CPU connected to the time delay measurement FPGA; the time delay measurement FPGA is connected to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller at both ends, and the measurement node host CPU is connected to the host PC at the same time.

[0040] The first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller are provided with a SPW-EOP interrupt module.

[0041] The time delay test method is specifically:

[0042] (1) The first node host CPU controls the first node high-speed SpaceWire interface controller (interface controller B1) to cyclically send variable-length data packets at a fixed period, and when the packet tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller (interface controller B1), the SPW-EOP interrupt module is triggered to generate a sending node SPW-EOP interrupt signal and send it to the time delay measurement FPGA.

[0043] (2) At the same time, the data packet is transmitted to the high-speed SpaceWire router along the SpaceWire bus, and then forwarded to the second node high-speed SpaceWire interface controller (receiving node interface controller B2) through the SpaceWire bus.

[0044] (3) When the packet tail of each data packet enters the host interface of the second node high-speed SpaceWire interface controller (receiving node interface controller B2), the SPW-EOP interrupt module of the second node high-speed SpaceWire interface controller (receiving node interface controller B2) is triggered to generate a receiving node SPW-EOP interrupt signal and send it to the time delay measurement FPGA.

[0045] (4) The time delay measurement FPGA cyclically collects the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, records the time stamps of the two SPW-EOP interrupt signals, calculates the time difference between the two time stamps to obtain the transmission time delay, and stores the transmission time delay in the BRAM of the time delay measurement FPGA (the specific working process of the FPGA is shown in Figure 3 FIG. 1).

[0046] (5) The measurement node host CPU reads the data in the BRAM of the time delay measurement FPGA and transmits the data to the PC, and the PC saves and analyzes the time delay data.

[0047] In the SPW-EOP interrupt module in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller: the SPW-EOP interrupt module includes an SPW-EOP module and an interrupt controller;

[0048] When the end of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller (interface controller B1) or the second node high-speed SpaceWire interface controller (interface controller B2), the SPW-EOP interrupt module interrupt control register is enabled to allow the interrupt application to be initiated;

[0049] The SPW-EOP interrupt module compares the characters in the data packet with the standard packet end character "<1> <xxxxxxx0>":

[0050] If not, continue to judge;

[0051] If consistent, the SPW-EOP module sends an interrupt application to the interrupt controller, sets the corresponding position (SPW-EOP bit) in the interrupt status register to 1; the interrupt controller generates an interrupt signal, outputs a high level to the time delay measurement FPGA through the interrupt pin, and completes the sending of the interrupt signal.

[0052] The SPW-EOP interrupt module compares the data characters of the data packet sent by the first node host CPU with the standard trailer characters "<1> <xxxxxxx0>The valid SPW-EOP interrupt signal is triggered when the data packet leaves the host interface.

[0053] The FPGA sampling frequency is not less than 2 times the frequency of the SPW-EOP interrupt signal.

[0054] The process of the FPGA collecting and timing the SPW-EOP signal is cyclically run in parallel.

[0055] The worst time error of the FPGA collecting and synchronizing the signal is not more than 8ns.

[0056] The BRAM space instantiated in the FPGA is mapped to the IO space of the host CPU.

[0057] The host CPU of the measurement node communicates with the PC through a UART serial communication protocol.

[0058] The nodes and the router in the network are connected through a SpaceWire bus.

[0059] The routers in the network can be cascaded into 1 level and 2 levels respectively.

[0060] The first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the router and the link run at a speed range of 2-300MHz.

[0061] The measurement device comprises a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, an FPGA and a PC.

[0062] The application will be further described below in combination with the drawings and examples. The SpaceWire bus network of Example 1 is composed of a 1-level router, one sending node and one receiving node, and the SpaceWire bus network of Example 2 is composed of a 2-level serial router, one sending node and one receiving node.

[0063] Example 1:

[0064] Appendix Figure 1 (a) The device shown realizes high-precision SpaceWire bus delay measurement in a single-stage router network environment. The delay measurement device comprises a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, a delay measurement FPGA, and a host PC. The node host CPU is connected with the high-speed SpaceWire interface controller through 13-bit address lines, 32-bit data lines and other control lines, the high-speed SpaceWire interface controller is connected with the high-speed SpaceWire router through a SpaceWire link, the delay measurement FPGA is connected with the measurement node host CPU through 13-bit address lines, 32-bit data lines and other control lines, and the measurement node host CPU is connected with the host PC through a serial bus.

[0065] In the examples of the present application, in a typical application circuit, router A selects XXX006 developed by a certain company, interface controllers B1 and B2 select XXX005 developed by a certain company, the FPGA selects Xilinx Virtex-5 XC5VLX155T, the node host selects a Sparc-V8 architecture CPU, the FPGA delay measurement module selects a 50MHz crystal oscillator, and the SpaceWire node selects a 25MHz crystal oscillator.

[0066] According to the above-mentioned application circuit, the following steps are performed: Figure 1 (a) Link connection is performed on the SpaceWire bus network, and the SpaceWire link running rate is set to 300MHz. The FPGA delay measurement module is started, timing is started, and a SPW-EOP interrupt signal is collected. When the interrupt signal of the sending / receiving node is collected, the corresponding time stamp is recorded, and the transmission delay is calculated in the following manner:

[0067] T delay = T receive -T send

[0068] Wherein, T send represents the time stamp corresponding to the interrupt signal of the sending node, T receive represents the time stamp corresponding to the interrupt signal of the receiving node, and T delay represents the transmission delay. The FPGA sequentially calculates the transmission delay corresponding to each data packet and stores it in the BRAM.

[0069] The CPU2 program is configured to control the interface controller B2 to continuously wait for receiving data from the SpaceWire bus. The CPU1 program is configured to control the interface controller B1 to cyclically send data packets with a length of 124-12400 bytes to the SpaceWire bus at a fixed period, the length of the data packet in the 0th cycle is 124 bytes, the length of the data packet in the 1st cycle is 248 bytes, and the length of the data packet in the 99th cycle is 12400 bytes. The CPU3 program is configured to read the data in the BRAM and transmit the data to the upper computer, and record and process the experimental data. The corresponding time delay data of the data packets with different lengths from the sending node to the receiving node are shown in Table 1 and Table 2. Figure 4 and Table 1.

[0070] Table 1 Corresponding time delay data of data packets with different lengths from the sending node to the receiving node

[0071] Data packet size (bytes) Transmission latency (microseconds) 124 8.24 248 15.08 372 21.88 496 28.68 ··· ··· 12028 663.56 12152 670.4 12276 677.24 12400 684.04

[0072] As shown in the chart, the transmission time delay and the length of the data packet are in a linear relationship. In the 1st cycle, that is, when the length of the transmitted data packet is 124 bytes, the time delay is 8.24 microseconds, and in the 100th cycle, that is, when the length of the transmitted data packet is 12400 bytes, the time delay is close to 684.04us.

[0073] Example 2

[0074] Figure 1 shows the device for realizing high-precision SpaceWire bus time delay measurement in a two-level router cascade network environment. Figure 1 (b) The device shown in (b) realizes high-precision SpaceWire bus time delay measurement in a two-level router cascade network environment. The time delay measurement device comprises a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, an FPGA, and a PC upper computer.

[0075] In the example of the application, the router A and B in the typical application circuit are selected from XXX006 developed by a certain company, the interface controller B1 and B2 are selected from XXX005 developed by a certain company, the FPGA is selected from Xilinx Virtex-5 XC5VLX155T, the node host is selected from a Sparc-V8 architecture CPU, the FPGA time delay measurement module is selected from a 50MHz crystal oscillator, and the SpaceWire node is selected from a 25MHz crystal oscillator.

[0076] According to the above-mentioned SpaceWire bus time delay measurement device, the SpaceWire bus network is connected by links, and the running speed of the SpaceWire link is set to 300MHz. Figure 1 The FPGA time delay measurement module is started, and the timing is started and the SPW-EOP interrupt signal is collected. When the interrupt signal of the sending / receiving node is collected, the corresponding time stamp is recorded, and the transmission time delay is calculated as follows:

[0077] T delay = T receive - T send

[0078] Wherein, T send represents the time stamp corresponding to the interrupt signal in the sending node, T receive represents the time stamp corresponding to the interrupt signal in the receiving node, T delay represents the transmission delay. The FPGA will calculate the transmission delay corresponding to each data packet in sequence and store it in the BRAM.

[0079] The CPU2 program is configured to control the interface controller B2 to continuously wait for receiving data from the SpaceWire bus. The CPU1 program is configured to control the interface controller B1 to cyclically send data packets with a length of 124-12400 bytes to the SpaceWire bus at a fixed period, the length of the data packet in the 0th cycle is 124 bytes, the length of the data packet in the 1st cycle is 248 bytes, and so on, the length of the data packet in the 99th cycle is 12400 bytes. The CPU3 program is configured to read the data in the BRAM and transmit it to the upper computer, and record and process the experimental data.

[0080] The contents not described in detail in the specification of the present application belong to the prior art known to those skilled in the art.

Claims

1. A method for FPGA-based latency measurement of a SpaceWire bus network, the SpaceWire bus network comprising: The first node host CPU, the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router, the second node high-speed SpaceWire interface controller and the second node host CPU are connected in sequence; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router and the second node high-speed SpaceWire interface controller are connected through a SpaceWire bus; and the method comprises the following steps: SPW-EOP interrupt modules are added to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller; a time delay measurement FPGA module is connected in the SpaceWire bus network, the first node host CPU controls the first node high-speed SpaceWire interface controller to cyclically send variable-length data packets at a fixed period, and when the packet tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller, the SPW-EOP interrupt module is triggered to generate a sending node SPW-EOP interrupt signal and send it to the time delay measurement FPGA module; the data packet is transmitted along the SpaceWire bus to the high-speed SpaceWire router and then forwarded to the second node high-speed SpaceWire interface controller through the SpaceWire bus; when the packet tail of each data packet enters the host interface of the second node high-speed SpaceWire interface controller, the SPW-EOP interrupt module of the second node high-speed SpaceWire interface controller is triggered to generate a receiving node SPW-EOP interrupt signal and send it to the time delay measurement FPGA module; the time delay measurement FPGA module cyclically collects and synchronizes the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, records the values of the FPGA counters corresponding to the arrival of the two SPW-EOP interrupt signals, multiplies the values by the FPGA clock period to obtain the arrival time stamps of the corresponding signals, calculates the time difference between the two time stamps to obtain the transmission time delay and stores the time delay in the BRAM of the time delay measurement FPGA module.

2. The FPGA-based method for measuring the time delay of a SpaceWire bus network according to claim 1, wherein: The time delay measurement FPGA module comprises a time delay measurement FPGA and a measurement node host CPU connected to the time delay measurement FPGA; the time delay measurement FPGA is connected to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller at both ends, and the measurement node host CPU is further connected to a PC; the measurement node host CPU reads the data in the BRAM of the time delay measurement FPGA and transmits it to the PC, and the time delay data is saved and analyzed in the PC.

3. The FPGA-based SpaceWire bus network time delay measurement method according to claim 1, characterized in that: SPW-EOP interrupt modules are arranged in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller.

4. The FPGA-based method for measuring the time delay of a SpaceWire bus network according to claim 3, wherein: The SPW-EOP interrupt module comprises an SPW-EOP module and an interrupt controller, and specifically: When the end of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller, the SPW-EOP module interrupt control register is enabled to allow the initiation of an interrupt request; The SPW-EOP interrupt module compares the characters in the data packet with the standard trailer characters "<1> " as specified by the SpaceWire protocol. <xxxxxxx0> ”：< / xxxxxxx0> If not, continue to judge; If yes, the SPW-EOP module sends an interrupt request to the interrupt controller, sets the corresponding position in the interrupt status register to 1, the interrupt controller generates an interrupt signal and outputs a high level to the time delay measurement FPGA through the interrupt pin, thus completing the transmission of the interrupt signal.

5. The FPGA-based method for measuring latency of a SpaceWire network according to claim 1, wherein: The sampling frequency of the FPGA is not less than 2 times the highest SPW-EOP interrupt signal frequency.

6. The FPGA-based method for measuring latency of a SpaceWire network according to claim 1, wherein: The high-speed SpaceWire in the SpaceWire bus network can be cascaded for one or two levels.

7. The FPGA-based SpaceWire bus network time delay measurement method according to claim 1, characterized in that: The process of the FPGA collecting and timing the SPW-EOP interrupt signal is cyclically and parallelly run; The worst time error of the FPGA collecting and synchronizing the signals is not more than 8 ns.

8. The FPGA-based method for measuring latency of a SpaceWire network according to claim 1, wherein: The measurement node host CPU communicates with the host PC through a UART serial communication protocol.

9. The FPGA-based method for measuring latency of a SpaceWire network according to claim 1, wherein: The first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the high-speed SpaceWire router and the SpaceWire bus run at a speed ranging from 2 to 300 MHz.

10. A FPGA based SpaceWire bus network latency measuring device characterized in that It comprises: The SPW-EOP interrupt module and the time delay measurement FPGA module are arranged in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller of the SpaceWire bus network, wherein: The time delay measurement FPGA module comprises a time delay measurement FPGA and a measurement node host CPU connected to the time delay measurement FPGA; the time delay measurement FPGA is connected to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller at two ends, and the measurement node host CPU is connected to the host PC at the same time; The SPW-EOP interrupt module comprises an SPW-EOP module and an interrupt controller; the SPW-EOP interrupt module enables an interrupt control register in the SPW-EOP interrupt module when a packet tail of each data packet leaves a host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller, and allows to initiate an interrupt application; the SPW-EOP interrupt module compares a character in the data packet with a standard packet tail character "<" stipulated in the SpaceWire protocol, and if the character is not the standard packet tail character "<", the SPW-EOP interrupt module generates an interrupt signal to the host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller. <xxxxxxx0>If not, continue to judge; if yes, the SPW-EOP module sends an interrupt request to the interrupt controller, sets the corresponding position in the interrupt status register to 1, the interrupt controller generates an interrupt signal and outputs a high level to the time delay measurement FPGA through the interrupt pin, thus completing the transmission of the interrupt signal;< / xxxxxxx0> The time delay measurement FPGA module cyclically collects and synchronizes the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, records the values of the FPGA counters corresponding to the arrival of the two SPW-EOP interrupt signals, multiplies the FPGA clock period to obtain the arrival time stamp of the corresponding signal, calculates the time difference between the two time stamps to obtain the transmission time delay and stores it in the BRAM of the time delay measurement FPGA module.

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