Deep ultraviolet light emitting diode with light scattering structure and preparation method thereof

Abstract

The invention relates to a deep ultraviolet light-emitting diode with a light scattering structure and a preparation method of the deep ultraviolet light-emitting diode. The light-emitting diode comprises a substrate layer, a buffer layer and an N-type semiconductor transmission layer which are sequentially arranged along the epitaxial growth direction of a chip, wherein the shape of the N-type semiconductor transmission layer is divided into an upper part and a lower part, and the multi-quantum well active layer, the P-type semiconductor transmission layer and the P-GaN contact layer sequentially cover the surface of the upper part of the N-type semiconductor transmission layer; a horizontal light scattering structure layer and a vertical light scattering structure are respectively distributed in the upper part and the lower part of the N-type semiconductor transmission layer. According to the invention, the scattering effect of light in the N-type semiconductor transmission layer is improved, the optical waveguide effect of the N-type semiconductor transmission layer is broken, the light is effectively prevented from spreading to the metal n electrode, meanwhile, the light can be scattered, the bottom light emitting efficiency of the deep ultraviolet LED is improved, and the light extraction efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diode semiconductors, and in particular to a deep ultraviolet light emitting diode with a light scattering structure. Background Art

[0002] AlGaN-based deep ultraviolet light-emitting diodes (LEDs) usually use P-GaN materials as the P-type ohmic contact layer, but because P-GaN absorbs light in the deep ultraviolet band, a flip-chip structure is usually used to generate photons from the multi-quantum well active region through the N-type semiconductor transmission layer, buffer layer, and substrate to emit from the bottom of the device, reducing light absorption. However, during the propagation of photons, an optical waveguide is formed, making it difficult for some fixed-angle light to be emitted, which will also limit the improvement of light extraction efficiency to a certain extent. At present, making micro / nanoscale structures to increase the light extraction efficiency of ultraviolet LEDs is the most commonly used method.

[0003] The current technology proposes to use nanospheres or anodized aluminum holes as masks to etch the N-type semiconductor transmission layer to roughen the Ga-surface N-type semiconductor transmission layer between the mesa and the n-electrode (patent number: CN112885933 B). Although this method improves the light extraction efficiency to a certain extent, the depth of the micro-nano structure (perpendicular to the horizontal direction) of conventional dry etching is only 2 to 500 nm, and no transmission pores penetrating the N-type semiconductor are formed. Therefore, a large number of photons will still be transmitted along the N-type semiconductor to the n-electrode and then absorbed.

[0004] Therefore, based on the previous research of our research group on the scattering structure of nAlGaN etching, we proposed to use electrochemical etching technology to form a dense and penetrating array of nanoholes between the electrode and the mesa step and inside the N-type semiconductor transmission layer. This can effectively block the propagation of light to the metal n-electrode and at the same time scatter the light, thereby increasing the light extraction efficiency.

[0005] Invention patent content

[0006] The purpose of the present invention is to provide a method for preparing a deep ultraviolet light-emitting diode with a light scattering structure in view of the shortcomings in the current technology. After etching the mesa to expose the N-type semiconductor transport layer, the method sequentially completes the preparation of the N-type ohmic electrode and the P-type ohmic electrode, and then deposits SiO2, and opens a hole in the SiO2 layer above the etched mesa of the exposed N-type semiconductor transport layer not covered by the N-type ohmic electrode, and performs electrochemical etching in the horizontal and vertical directions. After the etching is completed, the SiO2 layer above the N-type ohmic electrode and the P-type ohmic electrode is opened to expose the N-type ohmic electrode and the P-type ohmic electrode. A deep ultraviolet light-emitting diode with a nanometer-sized horizontal light scattering structure (between the N-type ohmic electrode and the mesa step, inside the N-type semiconductor transport layer) is prepared in the N-type semiconductor transport layer. The patent of this invention improves the scattering effect of light inside the N-type semiconductor transmission layer, breaks the optical waveguide effect of the N-type semiconductor transmission layer, effectively blocks the propagation of light to the metal n-electrode, and can scatter light at the same time, improve the efficiency of light output from the bottom of the deep ultraviolet LED, and improve the light extraction efficiency.

[0007] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0008] A deep ultraviolet light-emitting diode with a light scattering structure, the light-emitting diode comprises: a substrate layer, a buffer layer, and an N-type semiconductor transmission layer in order along the chip epitaxial growth direction;

[0009] The N-type semiconductor transmission layer is in the shape of two parts, the lower part completely covers the buffer layer, and the upper part is divided into two terraces;

[0010] The thickness of the lower part of the N-type semiconductor transmission layer is 1 to 3 μm; the thickness of the upper part is 0.1 to 3 μm; the angle between the edge length and the bottom edge of the terrace is 15 to 90 degrees; the area of ​​the rectangular bottom of the terrace accounts for 50 to 90% of the area of ​​the N-type semiconductor transmission layer;

[0011] The multi-quantum well active layer, the P-type semiconductor transmission layer, and the P-GaN contact layer are all terraces with the same gradient as the N-type semiconductor transmission layer 103, and sequentially cover the upper surface of the N-type semiconductor transmission layer from bottom to top;

[0012] The P-type ohmic electrode layer is located in the middle of the upper part of the P-GaN contact layer terrace, and the N-type ohmic electrode layer is located in the middle of the upper part of the exposed N-type semiconductor transmission layer;

[0013] The area not covered by the N-type ohmic electrode and the P-type ohmic electrode, the outer edge of the N-type ohmic electrode layer, the outer edge of the P-type ohmic electrode layer, and the sidewall of the terrace are all covered with a SiO2 film;

[0014] A vertical light scattering structure is distributed inside the lower part of the N-type semiconductor transmission layer which is not covered with the N-type ohmic electrode layer and is located under the SiO2 film;

[0015] The vertical light scattering structure layer is an array distribution feature of nanometer-sized air cavities; the cross-sectional area of ​​the air cavities is 10% to 80% of the exposed area in the lower part of the N-type semiconductor transmission layer, and the pore diameter is 20 to 500 nm;

[0016] In the terrace structure of the upper part of the N-type semiconductor transmission layer, a horizontal light scattering structure is distributed and penetrates in the horizontal direction;

[0017] The horizontal light scattering structure layer is an array distribution feature of nanometer-sized air cavities. The cross-sectional area of ​​the air cavities is 10% to 80% of the vertical cross-sectional area of ​​the middle and side portions of the upper portion of the N-type semiconductor transmission layer, and the pore diameter is 20 to 500 nm;

[0018] The thickness of the SiO2 film is

[0019] The material of the N-type semiconductor transmission layer is AlGaN, wherein the Al component is 45-55%, and the Si doping concentration is (1.0E17-9.9E19) / cm -3 , the thickness of the N-type semiconductor transport layer is 1 to 5 μm, and the surface area of ​​the N-type semiconductor transport film layer is denoted as S1.

[0020] The exposed area of ​​the N-type semiconductor transmission layer is 10% to 60% S1, and the dry etching depth (perpendicular to the horizontal direction) is 1 to 4 μm.

[0021] The N-type semiconductor transmission layer is partially exposed, with pits distributed on the surface and a hole structure formed inside. The exposed portion of the N-type semiconductor transmission layer is covered with an N-type ohmic electrode.

[0022] The ratio of the exposed area of ​​the N-type semiconductor transmission layer to the total area of ​​the N-type semiconductor transmission layer is 10% to 60%;

[0023] The substrate is one of sapphire, Si, AlN, SiC or GaN, and the substrate can be a c-plane or an m-plane along the epitaxial growth direction.

[0024] The buffer layer material is Al x1 Ga 1-x1 N; wherein, 0≤x1≤1, 0≤1-x1≤1, and the thickness is 1 to 5 μm.

[0025] The material of the multi-quantum well active layer is Al x3 Ga 1-x3 N / A x4 Ga1-x4 N; where 0≤x3≤1, 0≤1-x3≤1, 0≤x4≤1, 0≤1-x4≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of quantum wells is greater than or equal to 3; quantum well Al x3 Ga 1-x3 N thickness is 0.5~5nm, quantum barrier Al x4 Ga 1-x4 The thickness of N is 3 to 50 nm.

[0026] The material of the P-type semiconductor transport layer is Al x6 Ga 1-x6 N; wherein, 0≤x6≤1, 0≤1-x6≤1, and the thickness is 50~250nm.

[0027] The material of the P-GaN layer is P-type doped GaN, and the thickness is 2-20 nm.

[0028] The material of the P-type ohmic electrode is Ni / Au, Cr / Au, Pt / Au or Ni / Al, wherein the area of ​​the P-type ohmic electrode occupies 10% to 80% of the area of ​​the N-type semiconductor transmission layer;

[0029] The material of the N-type ohmic electrode is Al / Au, Cr / Au or Ti / Al / Ti / Au, wherein the area of ​​the N-type ohmic electrode occupies 10% to 50% of the area of ​​the N-type semiconductor transmission layer.

[0030] The method for preparing the deep ultraviolet light-emitting diode with a light scattering structure comprises the following steps:

[0031] In the first step, an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum well active layer, a P-type semiconductor transport layer and a p-GaN contact layer are sequentially grown on the substrate using MOCVD (metal organic chemical vapor deposition) technology.

[0032] The second step is to dry-etch from the P-GaN contact layer to the N-type semiconductor transport layer through photolithography and etching processes based on the preparation of the epitaxial material in the first step, and the exposed area of ​​the N-type semiconductor transport layer accounts for 10% to 60% of the total area of ​​the N-type semiconductor transport layer, and then metal evaporation of the N-type ohmic electrode and the P-type ohmic electrode is performed in sequence;

[0033] In the third step, PECVD equipment is used to deposit SiO2 on the upper surface and sidewall of the epitaxial wafer prepared in the second step, followed by dry etching, and then BOE solution is used to wet etch the SiO2 film to expose the N-type semiconductor transport layer mesa etching cross section;

[0034] The fourth step is horizontal electrochemical corrosion. Prepare 0.1-0.3 mol / L acidic electrolyte, prepare a conductive metal layer on the side of the epitaxial wafer, clamp the conductive metal layer of the epitaxial wafer on the working electrode, set the voltage to 10-30 V, and the electrochemical corrosion time to 5-60 min. After the corrosion is completed, remove the conductive metal layer.

[0035] Step 5: SiO2 is deposited on the upper surface and sidewall of the epitaxial wafer prepared in step 4 by using PECVD equipment; then the SiO2 film is dry-etched to expose the N-type semiconductor transport layer mesa etching section;

[0036] The sixth step is electrochemical corrosion in the vertical direction. Prepare 0.1-0.5 mol / L alkaline electrolyte, prepare a conductive metal layer on the side of the epitaxial wafer, clamp the conductive metal layer of the epitaxial wafer on the working electrode, set the voltage to 30-50V, and the electrochemical corrosion time to 10s-30min; then reset the voltage to 10-30v, 0.1-0.3mol / L acidic or alkaline electrolyte, and the electrochemical corrosion time is 1-60min. After the corrosion is completed, remove the conductive metal layer.

[0037] Step 7. After completing the above steps, deposit a SiO2 film, use a SiO2 mask for photolithography, and perform dry etching after the photolithography is completed to expose the N-type ohmic electrode and the P-type ohmic electrode.

[0038] Thus, a deep ultraviolet light-emitting diode with a light scattering structure is obtained.

[0039] The beneficial effects of the present invention are:

[0040] (1) The present invention pre-deposits SiO on the N-type semiconductor transmission surface. 2， A hole is opened in the pre-deposited SiO2 thin film layer to penetrate to the N-type semiconductor transmission surface. On the one hand, it can effectively protect the N-type ohmic electrode, P-type ohmic electrode and multi-quantum well active epitaxial layer from electrochemical corrosion. On the other hand, it guides electrons along a specific path to preferentially corrode the N-type semiconductor transmission in the vertical direction, and increases the controllability of the corrosion process.

[0041] (2) The present invention adopts a step-by-step electrochemical corrosion method. On the one hand, an acidic electrolyte is used to etch in a horizontal direction (perpendicular to the epitaxial growth direction) to prepare nano-voids in the horizontal direction inside the N-type semiconductor transport layer; on the other hand, an alkaline electrolyte is fully used to etch in a vertical direction (parallel to the epitaxial growth direction). First, a high voltage, a high concentration electrolyte, and a short time of electrochemical corrosion are used to prepare large-aperture, vertically oriented nano-pores. Then, a low voltage, a low concentration, and a long time of electrochemical corrosion are used to further guide the electrolyte into the nano-pores through the formed pores based on the first step of electrochemical corrosion, thereby achieving shaping inside the pores and homogenization between the pores.

[0042] (3) Nanopores with light scattering structures are prepared in the N-type semiconductor transmission epitaxial layer to improve the light scattering effect inside the N-type semiconductor transmission layer, break the optical waveguide effect of the N-type semiconductor transmission layer, effectively change the light propagation path, improve the light output efficiency of the bottom of the deep ultraviolet LED, and improve the light extraction efficiency. Specifically, Figure 6 It can be seen that compared with a deep ultraviolet light-emitting diode without a scattering structure, the TE mode light extraction efficiency of the deep ultraviolet light-emitting diode with the light scattering structure described in the patent of the present invention can be increased by 75%, and the TM mode light extraction efficiency can be increased by 151%.

[0043] (4) The operating process of the method for preparing a deep ultraviolet light-emitting diode with a light scattering structure of the present invention is within the capabilities of technicians in this technical field. The raw materials involved can be obtained through general channels. The process is simple and reliable, has strong repeatability, and has low production costs. It is suitable for industrial promotion and can be applied to the field of lasers. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described below in conjunction with the accompanying drawings.

[0045] Figure 1 Schematic diagram of the epitaxial structure of deep ultraviolet light-emitting diodes in current technology.

[0046] Figure 2 Schematic diagram of the horizontal electrochemical corrosion exposure part of the N-type semiconductor transport layer.

[0047] Figure 3 Schematic diagram of the vertical electrochemical corrosion exposure part of the N-type semiconductor transport layer.

[0048] Figure 4 This is a process flow chart for electrochemical etching of N-type semiconductor transport layer.

[0049] Figure 5 A schematic diagram of a deep ultraviolet light-emitting diode with a light scattering structure.

[0050] Figure 6 The light extraction efficiency of a deep ultraviolet light-emitting diode with a light scattering structure.

[0051] Among them, 101. sapphire substrate, 102. AlN buffer layer, 103. N-type semiconductor transport layer, 104. multi-quantum well active layer, 105. P-type semiconductor transport layer, 106. P-GaN contact layer, 107. SiO2 film, 108. P-type ohmic electrode, 109. N-type ohmic electrode, 110. horizontal light scattering structure, 111. vertical light scattering structure. DETAILED DESCRIPTION

[0052] The present invention is further described below in conjunction with the embodiments and drawings, but this is not intended to limit the scope of protection of the claims of this application.

[0053] In the description of the present invention, unless otherwise specified, "multiple" means two or more; the terms "center", "longitudinal", "lateral", "up", "down", "left", "right", "inside", "outside", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third" and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0054] Example 1

[0055] See also Figure 5 , an embodiment of the present invention provides a deep ultraviolet light-emitting diode with a light scattering structure, comprising: a substrate layer 101, a buffer layer 102, and an N-type semiconductor transmission layer 103 in order along the chip epitaxial growth direction;

[0056] The N-type semiconductor transmission layer 103 is shaped into two parts, the lower part of 103 completely covers the buffer layer 102, with a height of 1.8 μm, denoted as H, and the upper part of 103 is composed of two rows of terraces (with a bottom spacing of 50.8 μm), with a height of 1.2 μm, denoted as h; the terrace surface is rectangular, square, etc. (specifically, a 508 μm*508 μm square chip in this embodiment), the angle between the terrace edge length and the bottom edge is 25°, denoted as θ, wherein the rectangular area at the bottom of the terrace accounts for about 70% of the area of ​​the N-type semiconductor transmission layer 103;

[0057] The multi-quantum well active layer 104, the P-type semiconductor transport layer 105, and the P-GaN contact layer 106 are all terraces with the same gradient as the N-type semiconductor transport layer 103, and sequentially cover the upper surface of the N-type semiconductor transport layer 103 from bottom to top;

[0058] The bottom side length of the above-mentioned step is recorded as L, and the top side length is recorded as W, then W = Lh / tanθ;

[0059] The surface area of ​​the N-type semiconductor transport film layer (i.e., the projected area of ​​the lower layer) is denoted as S1;

[0060] The P-type ohmic electrode 108 layer is located in the middle of the upper part of the terrace of the P-GaN contact layer 106, and the N-type ohmic electrode layer 109 is located in the middle of the upper part of the exposed N-type semiconductor transmission layer (i.e., the lower part of the N-type semiconductor transmission layer) 103;

[0061] The area not covered by the N-type ohmic electrode and the P-type ohmic electrode, the outer edge of the N-type ohmic electrode layer 109, the outer edge of the P-type ohmic electrode layer 108, and the sidewalls of the terrace are all covered with a SiO2 film 107;

[0062] A vertical light scattering structure 111 is distributed inside the lower part of the N-type semiconductor transmission layer 103 which is not covered with the N-type ohmic electrode layer 109 and is located under the SiO2 film 107;

[0063] The vertical light scattering structure layer is located between the N-type ohmic electrode and the MESA etching table, and extends from the upper surface 103 exposed but not covered by the N-type ohmic electrode to the upper surface 102, and is an array distribution feature of nanometer-sized air cavities. The cross-section of a single air cavity is rectangular, and the surface area of ​​the array air cavity is approximately (20±2)%S1, the width (parallel to the horizontal direction) is approximately 80 to 100nm, the length (perpendicular to the horizontal direction) is approximately 1.8μm, and the period (center distance between adjacent rectangles) is 100nm to 300nm.

[0064] In the terrace structure on the upper part of the N-type semiconductor transmission layer 103, a horizontal light scattering structure 110 is distributed, penetrating the 103 in the horizontal direction;

[0065] The horizontal light scattering structure layer is located inside the N-type semiconductor transmission layer and is an array-distributed nanometer-sized air cavity. The cross-section of a single air cavity is circular, and the cross-sectional area of ​​the air cavity accounts for approximately (70±2)% of the vertical cross-sectional area of ​​the middle and side portions of the upper portion of the N-type semiconductor transmission layer. The diameter is approximately 40 to 60 nm, the period (center spacing) is 40 to 80 nm, and the distribution area in the vertical direction accounts for 4 / 5 of the thickness of the N-type semiconductor transmission layer.

[0066] The deep ultraviolet light-emitting diode with a light scattering structure is projected into a square from top to bottom.

[0067] The sapphire substrate is square, with a size of 508*508 μm, and a thickness of 430 μm along the

[0001] direction;

[0068] The thickness of the SiO2 film 107 is

[0069] The Al content of the N-type semiconductor transport layer is (50±5)%, and the n-type doping concentration is 1.0E18 / cm -3, thickness is 3μm, and the surface area of ​​the N-type semiconductor transport film layer is denoted as S1.

[0070] The exposed area of ​​the N-type semiconductor transmission layer is 30% S1, and the dry etching depth (perpendicular to the horizontal direction) is 1.2 μm.

[0071] The N-type ohmic electrode layer 109 is 10% S1, and the P-type ohmic electrode layer 108 is 60% S1.

[0072] The material of the multi-quantum well active layer is Al 0.7 Ga 0.3 N / A 0.5 Ga 0.5 N; the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well. The number of quantum wells is equal to 3, and the number of quantum barriers is equal to 4; a single quantum well Al 0.7 Ga 0.3 N thickness is 4nm, and a single quantum barrier Al 0.5 Ga 0.5 The thickness of N is 10 nm.

[0073] The material of the P-type semiconductor transport layer is Al 0.5 Ga 0.5 N, thickness is 48nm.

[0074] The material of the P-GaN layer is P-type doped GaN, doped with Mg, and the doping concentration is about 1.0E18 / cm -3 , thickness is 10nm.

[0075] The preparation method of the above-mentioned deep ultraviolet LED chip structure with light scattering structure is as follows:

[0076] In the first step, an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum well active layer, a P-type semiconductor transport layer and a P-GaN contact layer are sequentially grown on a c-plane sapphire substrate using MOCVD (metal organic chemical vapor deposition) technology. The above layers constitute the basic structure of the epitaxial wafer.

[0077] In the second step, based on the preparation of the epitaxial material in the first step, dry etching is performed from the P-GaN contact layer to the N-type semiconductor transmission layer through photolithography and etching processes. The N-type semiconductor transmission dry etching depth is about 1.2 μm, and the exposed part accounts for 30% of the N-type semiconductor transmission layer. Then, Ti-Al-Ti-Au is evaporated on the N-type ohmic electrode, and Ni-Au is evaporated on the P-type ohmic electrode in turn.

[0078] The third step is to use PECVD equipment to deposit SiO2 with a deposition thickness of Dry etching, and then wet etching of SiO2 film using BOE solution, such as Figure 2 shown.

[0079] The fourth step is horizontal electrochemical etching. Prepare a 0.1 mol / L HNO3 electrolyte, prepare a conductive metal layer (indium or tin) on the side of the epitaxial wafer, clamp the epitaxial wafer conductive metal layer on the working electrode, set the voltage to 30V, and the electrochemical etching time to 5min. After the etching is completed, remove the conductive metal layer;

[0080] The mechanism is that, under the protection of the SiO2 insulating layer, the conductive electrons are transmitted laterally along the N-type semiconductor transmission layer above 103 that is not covered by SiO2. The equivalent resistance is minimal, and the electrolyte mass / ion transmission direction is horizontal, so corrosion occurs in the horizontal direction. Among them, the corroded part of the sample is immersed in the electrolyte, and the conductive metal layer is not immersed.

[0081] Step 5: Use PECVD equipment to deposit SiO2 with a deposition thickness of Dry etching of SiO2 thin films, such as Figure 3 shown.

[0082] The sixth step is electrochemical corrosion in the vertical direction. Prepare 0.3 mol / L KOH electrolyte, prepare a conductive metal layer on the side of the epitaxial wafer, clamp the conductive metal layer of the epitaxial wafer on the working electrode, set the voltage to 40V, and the electrochemical corrosion time to 5 minutes. Take out the sample, reset the voltage to 15V, the electrolyte is 0.1 mol / L KOH solution, and the electrochemical corrosion time is 30 minutes. After the corrosion is completed, remove the conductive metal layer.

[0083] The mechanism is that the vertical electrochemical corrosion utilizes the conductive electrons to be transmitted from bottom to top along the N-type semiconductor transmission layer between the N-type ohmic electrode and the MESA etching table under the protection of the SiO2 insulating layer. At this time, the equivalent resistance is minimum, and the electrolyte mass / ion transmission direction is along the vertical direction, so the corrosion is along the vertical direction; wherein, firstly, high voltage, high concentration electrolyte, violent reaction, and short-time electrochemical corrosion are used to prepare large-aperture, vertically oriented nanopores, and then low voltage, low concentration, relatively mild reaction, and long-time electrochemical corrosion are used. Based on the first step of electrochemical corrosion, the electrolyte is further preferentially directed into the nanopores through the formed pores, thereby realizing the shaping of the pores and the homogenization between the pores.

[0084] Step 7. After completing the above steps, deposit a SiO2 film, use a SiO2 mask for photolithography, and perform dry etching after the photolithography is completed to expose the N-type ohmic electrode and the P-type ohmic electrode.

[0085] Thus, a deep ultraviolet LED with a light scattering structure is obtained in this embodiment, such as Figure 5 shown.

[0086] In this embodiment, nano-holes with light scattering structures are prepared in the N-type semiconductor transmission epitaxial layer to improve the light scattering effect inside the N-type semiconductor transmission layer, breaking the optical waveguide effect of the N-type semiconductor transmission layer, which can effectively change the light propagation path, improve the light output efficiency of the bottom of the deep ultraviolet LED, and improve the light extraction efficiency. Figure 6 As shown (using 2D-FDTD simulation software), compared with a deep ultraviolet light-emitting diode without a scattering structure, the TE mode light extraction efficiency of the deep ultraviolet light-emitting diode with the light scattering structure described in the patent of the present invention can be increased by 75%, and the TM mode light extraction efficiency can be increased by 151%.

[0087] Example 2

[0088] The other steps are the same as in Example 1, except that the HNO3 solution is replaced by an oxalic acid solution with a concentration of 0.1 mol / L; the obtained material properties are similar;

[0089] The raw materials involved in the present invention can be obtained through known routes, and the operation process in the preparation method can be mastered by technicians in this technical field.

[0090] Any matters not described in the present invention are applicable to the prior art.

Claims

1. A deep ultraviolet light-emitting diode having a light scattering structure, characterized in that The light emitting diode comprises: a substrate layer, a buffer layer, and an N-type semiconductor transmission layer in order along the chip epitaxial growth direction; The N-type semiconductor transmission layer is in the shape of two parts, the lower part completely covers the buffer layer, and the upper part is divided into two terraces; The multi-quantum well active layer, the P-type semiconductor transmission layer, and the P-GaN contact layer are all terraces with the same gradient as the N-type semiconductor transmission layer, and sequentially cover the upper surface of the N-type semiconductor transmission layer from bottom to top; The P-type ohmic electrode layer is located in the middle of the upper part of the P-GaN contact layer terrace, and the N-type ohmic electrode layer is located in the middle of the upper part of the exposed N-type semiconductor transmission layer; The area not covered by the N-type ohmic electrode and the P-type ohmic electrode, the outer edge of the N-type ohmic electrode layer, the outer edge of the P-type ohmic electrode layer, and the sidewall of the terrace are all covered with a SiO2 film; A vertical light scattering structure is distributed inside the lower part of the N-type semiconductor transmission layer which is not covered with the N-type ohmic electrode layer and is located under the SiO2 film; The vertical light scattering structure layer is an array distribution feature of nanometer-sized air cavities; the cross-sectional area of ​​the air cavities is 10% to 80% of the exposed area in the lower part of the N-type semiconductor transmission layer, and the pore diameter is 20 to 500 nm; In the terrace structure of the upper part of the N-type semiconductor transmission layer, a horizontal light scattering structure is distributed and penetrates in the horizontal direction; The horizontal light scattering structure layer is an array distribution characteristic nanometer-sized air cavity; the cross-sectional area of ​​the air cavity accounts for 10% to 80% of the vertical cross-sectional area of ​​the middle and side parts of the upper part of the N-type semiconductor transmission layer, and the hole diameter is 20 to 500nm.

2. The deep ultraviolet light emitting diode with a light scattering structure as claimed in claim 1, characterized in that the material of the N-type semiconductor transmission layer is Al X Ga 1-X N, where Al component X = 45-55%, Si doping concentration (1.0E17-9.9E19) / cm -3 , the thickness of the N-type semiconductor transport layer is 1 to 5 μm. The ratio of the exposed portion area of ​​the N-type semiconductor transmission layer to the total N-type semiconductor transmission layer area is 10% to 60%.

3. The deep ultraviolet light-emitting diode with a light scattering structure as described in claim 1 is characterized in that the lower part of the N-type semiconductor transmission layer is 1 to 3 μm thick; the upper part is 0.1 to 3 μm thick; the angle between the edge length and the bottom edge of the terrace is 15 to 90°; the rectangular area at the bottom of the terrace accounts for 50 to 90% of the area of ​​the N-type semiconductor transmission layer.

4. The deep ultraviolet light-emitting diode with a light scattering structure as claimed in claim 1, characterized in that the substrate is one of sapphire, Si, AlN, SiC or GaN, and the substrate can be a c-plane or an m-plane along the epitaxial growth direction; The buffer layer material is Al x1 Ga 1-x1 N; among them, 0≤x1≤1,0≤1-x1≤1, thickness is 1~5μm; The material of the multi-quantum well active layer is Al x3 Ga 1-x3 N / A x4 Ga 1-x4 N; where 0≤x3≤1, 0≤1-x3≤1, 0≤x4≤1, 0≤1-x4≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of quantum wells is greater than or equal to 3; quantum well Al x3 Ga 1-x3 N thickness is 0.5~5nm, quantum barrier Al x4 Ga 1-x4 N thickness is 3 to 50 nm; The material of the P-type semiconductor transport layer is Al x6 Ga 1-x6 N; wherein 0≤x6≤1, 0≤1-x6≤1, and the thickness is 50 to 250 nm; The thickness of the SiO2 film is The material of the P-GaN layer is P-type doped GaN, and the thickness is 2-20 nm.

5. The deep ultraviolet light-emitting diode with a light scattering structure as claimed in claim 1, characterized in that the material of the P-type ohmic electrode is Ni / Au, Cr / Au, Pt / Au or Ni / Al, wherein the area of ​​the P-type ohmic electrode occupies 10% to 80% of the area of ​​the N-type semiconductor transmission layer; The material of the N-type ohmic electrode is Al / Au, Cr / Au or Ti / Al / Ti / Au, wherein: The area of ​​the N-type ohmic electrode occupies 10% to 50% of the area of ​​the N-type semiconductor transmission layer.

6. The method for preparing a deep ultraviolet light-emitting diode having a light scattering structure according to claim 1, characterized in that The following steps are involved: In the first step, an AlN buffer layer, an N-type semiconductor transport layer, a multi-quantum well active layer, a P-type semiconductor transport layer and a p-GaN contact layer are sequentially grown on the substrate using MOCVD (metal organic chemical vapor deposition) technology. The second step is to dry-etch from the P-GaN contact layer to the N-type semiconductor transport layer through photolithography and etching processes based on the preparation of the epitaxial material in the first step, and the exposed area of ​​the N-type semiconductor transport layer accounts for 10% to 60% of the total area of ​​the N-type semiconductor transport layer, and then metal evaporation of the N-type ohmic electrode and the P-type ohmic electrode is performed in sequence; In the third step, PECVD equipment is used to deposit SiO2 on the upper surface and sidewall of the epitaxial wafer prepared in the second step, followed by dry etching, and then BOE solution is used to wet etch the SiO2 film to expose the N-type semiconductor transport layer mesa etching cross section; The fourth step is horizontal electrochemical etching. A 0.1-0.3 mol / L acid electrolyte is prepared to prepare a conductive metal layer on the side of the epitaxial wafer. The conductive metal layer of the epitaxial wafer is clamped on the working electrode. The voltage is set to 10-30 V. The electrochemical etching time is 5-60 min. After the etching is completed, the conductive metal layer is removed. Step 5: SiO2 is deposited on the upper surface and sidewall of the epitaxial wafer prepared in step 4 by using PECVD equipment; then the SiO2 film is dry-etched to expose the N-type semiconductor transport layer mesa etching section; The sixth step is electrochemical corrosion in the vertical direction. Prepare a 0.1-0.5 mol / L alkaline electrolyte, prepare a conductive metal layer on the side of the epitaxial wafer, clamp the conductive metal layer of the epitaxial wafer on the working electrode, set the voltage to 30-50 V, and the electrochemical corrosion time to 10 s to 30 min; then reset the voltage to 10-30 V, 0.1-0.3 mol / L acidic or alkaline electrolyte, and the electrochemical corrosion time to 1-60 min. After the corrosion is completed, remove the conductive metal layer; Step 7: After completing the above steps, deposit a SiO2 film, use a SiO2 mask for photolithography, and after the photolithography is completed, perform dry etching to expose the N-type ohmic electrode and the P-type ohmic electrode; Thus, a deep ultraviolet light-emitting diode with a light scattering structure is obtained.

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