MPW automatic makeup optimization method and system based on genetic algorithm and Web service platform thereof

Abstract

The invention relates to the technical field of integrated circuit chip manufacturing, in particular to an MPW automatic makeup optimization system based on a genetic algorithm and a Web service platform of the MPW automatic makeup optimization system. The method has the beneficial effects that an approximately optimal layout scheme can be quickly found in a huge solution space; each generation of genetic algorithm can be screened and evolved according to the quality of the current layout, and finally, the optimal solution is gradually approached; the layout can be optimized through automatic global search, multiple iterations and manual adjustment are not needed, and the makeup efficiency is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip manufacturing, and in particular to a MPW automatic layout optimization method, system and Web service platform based on a genetic algorithm. Background Art

[0002] In the integrated circuit manufacturing process, MPW (Multi-Project Wafer) is a way to integrate multiple design projects on the same wafer to reduce manufacturing costs. Especially in the low-volume production and prototype verification stages, the MPW method is widely used. Traditional MPW layout usually relies on manual layout or simple rule-based automation tools. Such methods have limited effects on optimizing wafer area utilization and dicing times.

[0003] Since chip sizes, shapes, and process requirements vary among projects, the complexity of panelization is very high. Inefficient panelization will result in low wafer utilization, more dicing times, and increased manufacturing costs.

[0004] Therefore, how to efficiently and automatically complete MPW imposition through intelligent algorithms and provide a more convenient customer interaction platform is a problem that the industry urgently needs to solve.

[0005] Chinese patent CN114548015A, involving optimization technologies such as simulated annealing, realizes automatic MPW layout optimization.

[0006] For this algorithm, a series of fixed rules or search strategies are usually relied on to generate and optimize chip layout in MPW layout tasks. For chips of different sizes, the algorithm needs to use preset strategies for layout. Although it can give a feasible solution, due to the limitations of the algorithm itself, they often require a large number of iterations and calculation steps to gradually approach the optimal layout.

[0007] This method is less efficient, especially when faced with complex chip combinations, the assembly time is long and it is difficult to quickly find the optimal solution.

[0008] How to optimize the algorithm and speed up the splicing speed of complex chip combinations is an urgent pursuit of technical personnel in this field. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a MPW automatic layout optimization method, system and Web service platform based on genetic algorithm, which solves the problems existing in the prior art.

[0010] One of the purposes of the present invention is to provide an MPW automatic layout optimization method based on a genetic algorithm to solve the problem of slow layout speed of complex chip combinations;

[0011] The second object of the present invention is to provide a Web platform based on the MPW automatic imposition optimization method to provide automatic imposition services for customers;

[0012] The third object of the present invention is to provide a cutting system based on the MPW automatic panel optimization method to achieve automatic optimization of panelization and cutting.

[0013] The present invention discloses a MPW automatic layout optimization method based on a genetic algorithm, comprising the following steps:

[0014] S1, initial population generation;

[0015] S11. For each chip of a project, generate multiple initial layout plans according to its size, shape and process requirements;

[0016] S12, each typesetting scheme generated in S11 corresponds to an individual, and the number of individuals in the initial population can be set according to the complexity of the problem;

[0017] S2, fitness function definition:

[0018] Define a fitness function to evaluate the quality of each layout scheme;

[0019] S3, selection, crossover and mutation;

[0020] S31. Through the selection operation in the genetic algorithm, individuals with higher fitness are retained preferentially;

[0021] S32, generating new individuals through crossover and mutation operations, wherein the crossover operation combines partial solutions of two individuals with high fitness, and the mutation operation randomly changes the arrangement positions of individual chips to explore more possibilities of patchwork;

[0022] S4, iteration and termination; the above process is repeated until the optimal layout solution is found or the predetermined number of iterations is reached.

[0023] Furthermore, the fitness function in step S2 includes the following indicators:

[0024] Wafer area utilization: evaluates the proportion of wafer area effectively used after chip arrangement, with the goal of maximizing utilization;

[0025] Dicing times: evaluates the complexity of the dicing path, with the goal of minimizing the number of dicing operations;

[0026] Design rule constraints: Consider the process requirements of different projects and ensure that all design rules meet the standards.

[0027] Preferably, the S1 step is as follows:

[0028] The chip design of each project is represented by one or more two-dimensional rectangles, and the initial population is randomly generated in a variety of different arrangement schemes. The specific generation steps are as follows:

[0029] Input: wafer diameter, chip size and process requirements for each project;

[0030] Output: Multiple different initial layout schemes, each of which is represented as a set of layout coordinates (x, y) and a chip rotation angle (0° or 90°);

[0031] The size of the initial population can be set to N individuals, and the initial layout can be generated randomly or by rules.

[0032] Preferably, step S2 is implemented according to the following steps:

[0033] Area utilization: Assuming the total area of ​​the wafer is A_total and the actual used area is A_used, the area utilization can be expressed as:

[0034]

[0035] The higher the area utilization, the better the adaptability;

[0036] Number of dicing: The complexity of the dicing path directly affects the manufacturing cost. The number of dicing can be calculated by analyzing the chip arrangement and the number of horizontal and vertical cuts required. The fewer the number of dicing, the higher the adaptability;

[0037] Design rule constraints: ensure that the design rules of each chip (such as electrical isolation, number of process layers, etc.) meet the requirements. If a certain layout scheme violates the design rules, a lower fitness value will be given;

[0038] The final fitness function is defined as a weighted sum, expressed as:

[0039]

[0040] Among them, w_1, w_2 and w_3 are weight factors, which can be adjusted according to specific needs.

[0041] Furthermore, step S3 is performed as follows:

[0042] Selection operation: According to the fitness value, roulette wheel selection or tournament selection is used to select individuals with higher fitness; the selection mechanism ensures that the better layout solutions can participate more in subsequent iterations;

[0043] Crossover operation: For the two selected individuals, randomly select the intersection point and exchange some of the two mosaic schemes; the intersection point can be the arrangement position of a specific chip or a group of chips;

[0044] Mutation operation: Randomly select some chips from an individual, randomly change or rotate their positions, and generate new individuals.

[0045] Preferably, the probability of the mutation operation is set to a smaller value, more preferably, set to 5-10%.

[0046] Furthermore, the S4 step is performed as follows:

[0047] In each iteration, a new population is generated through selection, crossover, and mutation, and the process is repeated until the optimal solution is found or the predetermined maximum number of iterations is reached;

[0048] Preferably, the termination condition can be set to one of the following:

[0049] The maximum value of the fitness function does not change significantly within M generations; the number of iterations reaches the preset value.

[0050] The present invention also discloses a cutting system based on the MPW automatic imposition optimization method, comprising the following steps:

[0051] S1. Automated imposition process

[0052] S11. Project Input

[0053] Users upload chip design files (such as GDSII, LEF / DEF files) through the system and submit process requirements (such as design rules, process nodes, etc.);

[0054] The system converts this data into parameters such as the chip’s size, shape, and constraints that can be processed by algorithms;

[0055] S2. Imposition calculation

[0056] The background algorithm module receives the input data and starts running the genetic algorithm to generate the imposition plan;

[0057] The results of the imposition calculation include:

[0058] The arrangement position of each chip (x, y);

[0059] The rotation state of the chip;

[0060] Complete dicing path planning;

[0061] Statistics of area utilization and number of dicing times;

[0062] S3. Output of imposition results

[0063] After the calculation is completed, the system returns the imposition results to the user.

[0064] Furthermore, in the step S3, the results include a mosaic map, key statistical data, and a slicing path.

[0065] Furthermore, the present application also discloses a Web service platform based on the MPW automatic imposition optimization method, including:

[0066] User interface design

[0067] Users upload chip design files through the Web interface, view the imposition results, and adjust the algorithm parameters;

[0068] Backend architecture

[0069] The backend adopts a microservice architecture, where each service module is independently responsible for specific tasks, such as file uploading, imposition calculation, data storage, and report generation;

[0070] Data storage and management

[0071] Design files, layout results, reports and other data submitted by users will be stored in the cloud database;

[0072] Security and access control

[0073] The system has strict permission control on access to user data and files to ensure data security.

[0074] Preferably, in the backend architecture, the computing service module runs a genetic algorithm to speed up the imposition speed through distributed computing.

[0075] Preferably, in the security and access control, all transmission processes use encryption protocols (such as HTTPS), and user login adopts authentication mechanisms such as OAuth.

[0076] The beneficial effects of the present invention are:

[0077] It can quickly find a near-optimal layout solution in a huge solution space by simulating operations such as natural selection, crossover, and mutation;

[0078] Each generation of the genetic algorithm will be screened and evolved according to the quality of the current layout, and eventually gradually approach the optimal solution;

[0079] In the MPW imposition task, genetic algorithms can optimize the layout through automated global search without the need for multiple iterations and manual adjustments, significantly improving the efficiency of imposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 Logic diagram of the present invention. DETAILED DESCRIPTION

[0081] The specific implementation modes of the present invention are further described below in conjunction with examples. The following examples are only used to more clearly illustrate the technical embodiments of the present invention and are not intended to limit the protection scope of the present invention.

[0082] Example 1

[0083] A MPW automatic layout optimization method based on genetic algorithm includes the following steps:

[0084] S1. Initial population generation

[0085] The chip design of each project is represented by one or more two-dimensional rectangles, and the initial population is randomly generated in a variety of different arrangement schemes. The specific generation steps are as follows:

[0086] Input: wafer diameter, chip size and process requirements for each project.

[0087] Output: A variety of different initial layout schemes, each of which is represented by a set of layout coordinates (x, y), as well as parameters such as chip rotation angle (0° or 90°).

[0088] The size of the initial population can be set to N individuals, and the initial layout can be generated randomly or by rules. For example, larger chips can be arranged in the center area first, and smaller chips in the periphery.

[0089] S2. Fitness function design

[0090] The fitness function is the core of genetic algorithm optimization, which is used to evaluate the pros and cons of each imposition scheme.

[0091] For MPW panelization, the fitness function can combine the following indicators:

[0092] Area utilization: Assuming the total area of ​​the wafer is A_total and the actual used area is A_used, the area utilization can be expressed as:

[0093]

[0094] The higher the area utilization rate, the better the adaptability.

[0095] Number of dicing: The complexity of the dicing path directly affects the manufacturing cost. The number of dicing can be calculated by analyzing the chip arrangement and the number of horizontal and vertical cuts required. The fewer the number of dicing, the higher the adaptability.

[0096] Design rule constraints: Ensure that the design rules of each chip (such as electrical isolation, number of process layers, etc.) meet the requirements. If a certain layout scheme violates the design rules, a lower fitness value is given.

[0097] The final fitness function can be defined as a weighted sum, expressed as:

[0098]

[0099] Among them, w_1, w_2 and w_3 are weight factors, which can be adjusted according to specific needs.

[0100] S3, selection, crossover and mutation operations

[0101] Selection operation: According to the fitness value, roulette wheel selection or tournament selection is used to select individuals with higher fitness. The selection mechanism ensures that the better layout solutions can participate more in subsequent iterations.

[0102] Crossover operation: For the two selected individuals, randomly select the crossover point and exchange some of the two layout schemes. The crossover point can be the arrangement position of a specific chip or a group of chips.

[0103] Mutation operation: Randomly select some chips in an individual, perform random position changes or rotation operations on them, and generate new individuals. The probability of mutation operation is generally set to a small value, such as 5%-10%.

[0104] S4. Iteration and termination

[0105] In each iteration, a new population is generated through selection, crossover, and mutation, and the process is repeated until the optimal solution is found or the predetermined maximum number of iterations is reached. The termination condition can be set to one of the following:

[0106] The maximum value of the fitness function does not change significantly over several generations;

[0107] The cutting system based on the MPW automatic imposition optimization method comprises the following steps:

[0108] S1. Project Input

[0109] Users upload chip design files (such as GDSII, LEF / DEF files) through the system and submit process requirements (such as design rules, process nodes, etc.). The system converts these data into parameters such as chip size, shape, constraints, etc. that can be processed by algorithms.

[0110] S2. Imposition calculation

[0111] The background algorithm module receives the input data and starts running the genetic algorithm to generate the layout plan. The layout calculation results include:

[0112] The arrangement position of each chip (x, y);

[0113] The rotation state of the chip;

[0114] Complete dicing path planning;

[0115] Statistics on area utilization and number of dicing cycles.

[0116] S3. Output of imposition results

[0117] After the calculation is completed, the system returns the layout results to the user. The results include the layout map, key statistics, slicing paths, etc., and can be exported to multiple formats of reports (such as PDF, CSV). The user can choose to accept the plan, or regenerate the layout plan by adjusting parameters (such as giving priority to improving area utilization or reducing the number of slicing times).

[0118] The Web service platform based on the MPW automatic imposition optimization method includes:

[0119] S1. User interface design

[0120] Users upload chip design files through the web interface, view the imposition results, and adjust the parameters of the algorithm. The front end is developed using mainstream web frameworks (such as React, Vue.js) to ensure smooth interaction and user experience.

[0121] S2. Backend architecture

[0122] The backend adopts a microservice architecture, and each service module is independently responsible for specific tasks, such as file upload, imposition calculation, data storage, and report generation. The calculation service module runs a genetic algorithm to speed up the imposition speed through distributed computing.

[0123] S3, data storage and management

[0124] The design files, layout results, reports and other data submitted by users will be stored in the cloud database. The system supports data version management, allowing users to access historical layout results in the future.

[0125] S4. Security and Access Control

[0126] The system has strict permission control on user data and file access to ensure data security. All transmission processes use encryption protocols (such as HTTPS), and user login uses authentication mechanisms such as OAuth.

[0127] Application Example 1

[0128] In order to better demonstrate the specific implementation of the present invention, an actual project layout is used as an example for explanation below:

[0129] There are four chip sizes, and the goal is to fit them onto a single wafer:

[0130] Chip 1: size 300μm x 500μm

[0131] Chip 2: 800μm x 1200μm

[0132] Chip 3: size 1500μm x 2500μm

[0133] Chip 4: size 2000μm x 2500μm

[0134] These chips need to be assembled on a single wafer, with the goal of maximizing wafer utilization, ensuring that the spacing between chips meets manufacturing requirements, avoiding chip overlap, and ensuring that the dicing paths do not cross.

[0135] Assumptions:

[0136] The size of the wafer is 3000μm x 3000μm.

[0137] The minimum spacing between each chip is 100μm.

[0138] The lower the intersection of the dicing paths, the better, which means that the dicing process should be as simple as possible to avoid complex paths.

[0139] The goal is to maximize wafer utilization and optimize panelization time and dicing path.

[0140] The algorithm described in Example 1 is used for calculation

[0141] 1. Initialize the population: Randomly generate several layout plans, each of which consists of parameters such as chip placement and rotation angle.

[0142] 2. Evaluation and selection: Evaluate the quality of each layout based on indicators such as area utilization, panelization time, and intersection of dicing paths.

[0143] 3. Crossover and mutation: Combine genes of excellent solutions through crossover operation, and randomly change some gene values ​​through mutation operation to generate a new layout.

[0144] 4. Iterative optimization: Multiple generations of iterative optimization gradually approach the optimal solution.

[0145] Application Example 1

[0146] The conditions of Comparative Example 1 are the same as those of Application Example 1, except that the algorithm uses the traditional simulated annealing algorithm to perform chip layout.

[0147] That is, first layout according to the size and shape of the chip, and ensure that the spacing between the chips does not overlap. Then, by gradually adjusting the position of each chip, try to avoid wasting space.

[0148] The output results of the application examples and comparative examples are summarized to obtain the following data:

[0149] Table 1 Summary of results

[0150]

[0151] From the above comparison, it can be seen that the present application has significant advantages in the following aspects:

[0152] 1. Efficiency of plate making:

[0153] Comparative Example 1: The platemaking time is relatively long, especially when processing an ultra-large chip, the platemaking time reaches 360 seconds, and as the chip size increases, the platemaking time increases significantly.

[0154] Application example 1: Through intelligent optimization and global search, the imposition time is significantly shortened. For example, the imposition time of a super-large chip is reduced from 360 seconds with the traditional method to 180 seconds, saving 50% of the time.

[0155] 2. Wafer utilization rate:

[0156] Comparative Example 1: The wafer utilization rate is low, especially when processing medium and large chips, the area utilization rate is only 70%-75%. There will be a large amount of blank area on the wafer, wasting valuable production space.

[0157] Application Example 1: It can maximize the utilization of wafers, especially when laying out large chips, the utilization of wafers can reach 93%. Genetic algorithms reduce blank areas through global optimization and achieve higher area utilization.

[0158] 3. Degree of intersection of dicing paths:

[0159] Comparative Example 1: The degree of intersection of the dicing paths is high, especially in the layout of super-large chips, where the degree of intersection is as high as 35%, which makes the dicing process more complicated and increases the difficulty of production.

[0160] Application Example 1: The dicing path is optimized and the crossover is significantly reduced. For example, the crossover of the dicing path for ultra-large chips is reduced from 35% to 15%. This means that the dicing process is smoother, reducing possible errors and unnecessary complexity.

[0161] 4. Flexibility and adaptability:

[0162] Comparative Example 1: Since traditional algorithms mostly rely on manual adjustments and fixed rules, they have poor flexibility in dealing with complex and changing chip imposition tasks.

[0163] Application Example 1: It has strong adaptability and flexibility, can automatically adjust the layout, and as the imposition tasks increase, the algorithm can continuously optimize and improve performance.

[0164] From the above analysis, it can be seen that compared with the prior art, this application has the following advantages:

[0165] Platemaking efficiency: Significantly shortens the platemaking time, saving a lot of time especially when processing complex and extra-large chips.

[0166] Wafer utilization: It can maximize the utilization of wafers, improve the space utilization efficiency of chip layout, and reduce waste.

[0167] Dicing path optimization: The dicing path is optimized and the intersection degree is reduced, making the dicing process more efficient.

[0168] Flexibility and adaptability: It can automatically adjust and optimize the layout according to task requirements, which improves the adaptability and flexibility of the algorithm.

[0169] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A MPW automatic layout optimization method based on genetic algorithm, characterized in that: The steps include: S1, initial population generation; S11. For each chip of a project, generate multiple initial layout plans according to its size, shape and process requirements; S12, each typesetting scheme generated in S11 corresponds to an individual, and the number of individuals in the initial population can be set according to the complexity of the problem; S2, fitness function definition: Define a fitness function to evaluate the quality of each layout scheme; S3, selection, crossover and mutation; S31. Through the selection operation in the genetic algorithm, individuals with higher fitness are retained preferentially; S32, generating new individuals through crossover and mutation operations, wherein the crossover operation combines partial solutions of two individuals with high fitness, and the mutation operation randomly changes the arrangement positions of individual chips to explore more possibilities of patchwork; S4, iteration and termination; the above process is repeated until the optimal layout solution is found or the predetermined number of iterations is reached.

2. The MPW automatic layout optimization method based on genetic algorithm according to claim 1, characterized in that: The fitness function in step S2 includes the following indicators: Wafer area utilization: evaluates the proportion of wafer area effectively used after chip arrangement, with the goal of maximizing utilization; Dicing times: evaluates the complexity of the dicing path, with the goal of minimizing the number of dicing operations; Design rule constraints: Consider the process requirements of different projects and ensure that all design rules meet the standards.

3. The MPW automatic layout optimization method based on genetic algorithm according to claim 1, characterized in that: The S1 step is as follows: The chip design of each project is represented by one or more two-dimensional rectangles, and the initial population is randomly generated by a variety of different arrangement schemes. The specific generation steps are as follows: Input: wafer diameter, chip size and process requirements for each project; Output: Multiple different initial layout schemes, each of which is represented as a set of layout coordinates (x, y) and a chip rotation angle (0° or 90°); The size of the initial population can be set to N individuals, and the initial layout can be generated randomly or by rules.

4. The MPW automatic layout optimization method based on genetic algorithm according to claim 3 is characterized in that: In step S2, the following steps are implemented: Area utilization: Assuming the total area of ​​the wafer is A_total and the actual used area is A_used, the area utilization can be expressed as: The higher the area utilization, the better the adaptability; Number of dicing: The complexity of the dicing path directly affects the manufacturing cost. The number of dicing can be calculated by analyzing the chip arrangement and the number of horizontal and vertical cuts required. The fewer the number of dicing, the higher the adaptability; Design rule constraints: ensure that the design rules of each chip (such as electrical isolation, number of process layers, etc.) meet the requirements. If a certain layout scheme violates the design rules, a lower fitness value will be given; The final fitness function is defined as a weighted sum, expressed as: Among them, w_1, w_2 and w_3 are weight factors, which can be adjusted according to specific needs.

5. The MPW automatic layout optimization method based on genetic algorithm according to claim 1, characterized in that: Step S3 is performed as follows: Selection operation: According to the fitness value, roulette wheel selection or tournament selection is used to select individuals with higher fitness; the selection mechanism ensures that the better layout solutions can participate more in subsequent iterations; Crossover operation: For the two selected individuals, randomly select the intersection point and exchange some of the two mosaic schemes; the intersection point can be the arrangement position of a specific chip or a group of chips; Mutation operation: Randomly select some chips from an individual, randomly change or rotate their positions, and generate new individuals. Preferably, the probability of the mutation operation is set to a smaller value, more preferably, set to 5-10%.

6. The MPW automatic layout optimization method based on genetic algorithm according to claim 1, characterized in that: The S4 step is performed as follows: In each iteration, a new population is generated through selection, crossover, and mutation, and the process is repeated until the optimal solution is found or the predetermined maximum number of iterations is reached; Preferably, the termination condition can be set to one of the following: The maximum value of the fitness function does not change significantly within M generations; the number of iterations reaches the preset value.

7. A cutting system based on the MPW automatic imposition optimization method, characterized in that: The steps include: S1. Automated imposition process S11. Project Input Users upload chip design files (such as GDSII, LEF / DEF files) through the system and submit process requirements (such as design rules, process nodes, etc.); The system converts this data into parameters such as the chip’s size, shape, and constraints that can be processed by algorithms; S2. Imposition calculation The background algorithm module receives the input data and starts running the genetic algorithm to generate the imposition plan; The results of the imposition calculation include: The arrangement position of each chip (x, y); The rotation state of the chip; Complete dicing path planning; Statistics of area utilization and number of dicing times; S3. Output of imposition results After the calculation is completed, the system returns the imposition results to the user.

8. The cutting system based on the MPW automatic imposition optimization method according to claim 7, characterized in that: The following steps are included: In the S3 step, the results include a mosaic map, key statistical data, and a slicing path.

9. A cutting system based on the MPW automatic imposition optimization method, characterized in that: The Web service platform based on the MPW automatic imposition optimization method includes: User interface design Users upload chip design files through the Web interface, view the imposition results, and adjust the algorithm parameters; Backend architecture The backend adopts a microservice architecture, where each service module is independently responsible for specific tasks, such as file uploading, imposition calculation, data storage, and report generation; Data storage and management Design files, layout results, reports and other data submitted by users will be stored in the cloud database; Security and access control The system has strict permission control on access to user data and files to ensure data security.

10. The cutting system based on the MPW automatic imposition optimization method according to claim 9, characterized in that: In the backend architecture, the computing service module runs a genetic algorithm to speed up the imposition speed through distributed computing.

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