Coordination module and associated method for collision avoidance

Abstract

A coordination module for a node of a multipoint bus network, the coordination module comprising circuitry configured to: receive data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data; when the data is received from the MAC module, a conflict signal is asserted by default, so that the MAC module stops continuously sending the data; and controlling a listening signal to cause the MAC module to resend the data as part of a second transmission attempt such that the data can be transmitted over the multipoint bus network via the PHY module of the node at an upcoming transmission opportunity.

Description

Technical Field

[0001] The present disclosure relates to multi-drop bus networks, and in particular, to an apparatus and associated method for collision avoidance of nodes of a multi-drop bus network. Background Art

[0002] Conflicts on the bus of a multi-drop bus network may result in reduced bus efficiency and throughput. The devices and associated methods described herein can address this problem. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a coordination module for a node of a multi-point bus network, the coordination module comprising a circuit system, the circuit system being configured to:

[0004] receiving data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data;

[0005] asserting a conflict signal by default when receiving the data from the MAC module so that the MAC module stops sending the data; and

[0006] A snoop signal is controlled to cause the MAC module to resend the data as part of a second transmission attempt so that the data can be transmitted on the multi-point bus network via the PHY module of the node at an upcoming transmission opportunity.

[0007] In one or more embodiments, the coordination module may be configured to control the listening signal such that the second transmission attempt is synchronized with the upcoming transmission opportunity of the node.

[0008] In one or more embodiments, the coordination module may be configured to: assert the listening signal when the data is received from the MAC module as part of a first transmission attempt; and keep the listening signal asserted until the data can be transmitted at the upcoming transmission opportunity as part of the second transmission attempt, at which time the listening signal may be de-asserted by the coordination module.

[0009] In one or more embodiments, the MAC module may be configured to delay the retransmission of the data for a waiting time after de-assertion of the listening signal, and the coordination module may be configured to transmit a fill sequence during the waiting time of the MAC module to prevent the upcoming transmission opportunity of the node from timing out.

[0010] In one or more embodiments, the waiting time may be equal to the packet gap length.

[0011] In one or more embodiments, the upcoming transmission opportunity may have a duration less than one packet gap length.

[0012] In one or more embodiments, the MAC module may require a recovery time after assertion of the conflict signal, after which the MAC module may resend the data as part of the second transmission attempt, and the coordination module may be configured to wait at least the recovery time before deasserting the listening signal.

[0013] In one or more embodiments, the coordination module may be configured to determine the recovery time of the MAC module.

[0014] In one or more embodiments, the coordination module may be configured to determine the recovery time of the MAC module by monitoring a timing property of the MAC module or by obtaining the timing property from a register.

[0015] In one or more embodiments, the coordination module may be configured to receive a detection signal from the PHY module indicating activity from other nodes on the multi-point bus network, and to de-assert the listening signal when the detection signal indicates that the immediately preceding node in the bus schedule of the multi-point bus network is no longer active or has timed out.

[0016] In one or more embodiments, the coordination module may be configured to:

[0017] re-asserting the sense signal during the second transmission attempt by the MAC module;

[0018] Once the data has been transmitted on the multi-drop bus network, de-asserting the snoop signal again; and

[0019] The snoop signal remains de-asserted until additional data is received from the MAC module.

[0020] In one or more embodiments, the retransmitted data may include a first data frame, and the MAC module may first attempt to transmit a second data frame together with the first data frame. If the node is only allowed to transmit one frame per transmission opportunity, the coordination module may be configured to:

[0021] passing the first data frame to the PHY module for transmission on the multi-point bus network;

[0022] When transmission of the first data frame has been completed, asserting a conflict signal for the second data frame by default; and

[0023] The listening signal is de-asserted when a subsequent transmission opportunity arrives to enable transmission of the second data frame.

[0024] In one or more embodiments, the data received from the MAC module may include multiple data frames within the same sequence for transmission at the upcoming transmission opportunity, and the coordination module may be configured to insert an active-idle sequence between adjacent data frames to prevent the multi-point bus network from becoming idle before the multiple data frames have been transmitted.

[0025] In one or more embodiments, the coordination module may be unbuffered.

[0026] In one or more embodiments, the coordination module may be configured to examine the data and take any necessary action after the conflict signal has been asserted and before the data has been transmitted.

[0027] According to a second aspect of the present disclosure, a node of a multi-point bus network is provided, the node comprising the coordination module, MAC module and PHY module of the first aspect.

[0028] In one or more embodiments, the multi-point bus network may be an Ethernet network, the MAC module may be an Ethernet CSMA / CD MAC layer, and the PHY module may be a 10BASE-T1S PHY layer.

[0029] According to a third aspect of the present disclosure, a multi-point bus network is provided, comprising a plurality of nodes of the second aspect.

[0030] According to a fourth aspect of the present disclosure, there is provided a method for avoiding conflicts among nodes of a multi-point bus network, the method comprising:

[0031] receiving data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data;

[0032] asserting a conflict signal by default when receiving the data from the MAC module so that the MAC module stops sending the data; and

[0033] A snoop signal is controlled to cause the MAC module to resend the data as part of a second transmission attempt so that the data can be transmitted on the multi-point bus network via the PHY module of the node at an upcoming transmission opportunity.

[0034] According to a fifth aspect of the present disclosure, a computer program is provided, comprising computer code, wherein the computer code is configured to control the coordination module of the first aspect, control the node of the second aspect, control the multi-point bus network of the third aspect, or execute the method of the fourth aspect.

[0035] Although the present disclosure allows various modifications and alternative forms, the details of the present disclosure have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments outside the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed.

[0036] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed descriptions also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed descriptions in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0038] Figure 1 Shows the IEEE standard medium independent interface (MII) between the MAC module and the PHY module;

[0039] Figure 2 A coordination module between a MAC module and a PHY module is shown to avoid bus conflicts, wherein both the MAC module and the PHY module communicate with the coordination module using MII;

[0040] Figure 3 A coordination module having a data buffer between a MAC module and a PHY module is shown;

[0041] Figure 4 Shown by Figure 3 transmission attempts by a MAC module of a node on a fully loaded bus, wherein each first transmission attempt by the MAC module occurs well before a transmission opportunity of the node;

[0042] Figure 5 Shown by Figure 3 A transmission attempt by a MAC module of a node where the transmission opportunity has timed out;

[0043] Figure 6 Shown by Figure 3 A transmission attempt made by the MAC module of the node, in which the consecutive transmission opportunities have timed out;

[0044] Figure 7 A coordination module is shown without a data buffer between the MAC module and the PHY module;

[0045] Figure 8 Shown by Figure 7 The MAC module of the node attempts to transmit on a fully loaded bus;

[0046] Fig. 9 Shown by Figure 7 A transmission attempt by a MAC module of a node where the transmission opportunity has timed out;

[0047] Fig.10 Shown by Figure 7 A transmission attempt made by the MAC module of the node, in which the consecutive transmission opportunities have timed out;

[0048] Fig.11 Show Figure 8 a transmission attempt by the other node, wherein if there are no frames pending for retransmission, a snoop signal to the MAC module remains de-asserted during transmission by the other node;

[0049] Fig.12 Show Fig. 9 a transmission attempt by the other node, wherein if there are no frames pending for retransmission, a snoop signal to the MAC module remains de-asserted during transmission by the other node;

[0050] Fig.13 Show Fig.10 a transmission attempt by the other node, wherein if there are no frames pending for retransmission, a snoop signal to the MAC module remains de-asserted during transmission by the other node;

[0051] Fig.14 A method of conflict avoidance for nodes of a multi-point bus network is shown; and

[0052] Fig.15 is shown to include being configured to control, execute or enable Fig.14 A computer readable medium containing a computer program for the method. DETAILED DESCRIPTION

[0053] Ethernet Standards

[0054] Although the recent focus of Ethernet development has been on high data rates, not every application requires speeds of up to 400Gbps. For some applications, including the Internet of Things (IoT), industrial and automotive, 10Mps is sufficient for certain functions. For these use cases, factors such as cost, weight, distance and space required for cables are more important.

[0055] Recognizing these evolving requirements, the IEEE began defining IEEE 802.3cg, a single-pair Ethernet standard supporting 10Mbps, in early 2017. The goal of IEEE 802.3cg is to define short-range standards for point-to-point and multipoint with a maximum length of 25 meters, as well as a long-range point-to-point standard supporting distances up to 1,000 meters. The resulting IEEE 802.3cg specification includes two link layer standards: 10BASE-T1S and 10BASE-T1L.

[0056] The 10BASE-T1S short-range standard is primarily targeted at automotive and industrial applications. Multiple nodes on the network can share the cable in half-duplex shared media mode (multipoint mode) using the standard Ethernet Carrier Sense Multiple Access and Collision Detection (CSMA / CD) access method, or operate using PHY-level collision avoidance (PLCA). The cable can be an unshielded twisted pair (UTP) that can have multiple nodes with a media dependent interface (MDI) attached to them. Therefore, 10BASE-T1S can also be referred to as multi-point single-pair Ethernet.

[0057] The 10BASE-T1L long-range option is designed for IoT and industrial control applications. The 1,000-meter range is sufficient for use in large factories or warehouses, and 10Mbps is sufficient to collect data from sensors and monitor and control many types of industrial machinery. It shares the advantages of the short network variant: MAC-level compatibility with multi-pair Ethernet, as well as lower cost, weight, and required space.

[0058] The following description refers to the 10BASE-T1S standard, but may also be applicable to other (including future) networking standards, and thus is not necessarily limited to Ethernet or 10BASE-T1S.

[0059] Technical issues

[0060] Figure 1The carrier sense multiple access and collision detection (CSMA / CD) medium access control (MAC) protocol is shown. CSMA / CD uses carrier sense (CRS) to delay transmission until no other nodes on the network are transmitting. When the PHY module / layer of a node detects a collision (CRS=1), the PHY module / layer stops transmitting the frame, asserts a collision signal (COL=1) to the MAC module / layer of the node, and waits until the bus is silent before deasserting the listening signal (CRS=0). The MAC module keeps transmitting for a predefined (blocking) time to ensure that all nodes on the bus will observe the collision, then stops transmitting and waits until the listening signal (CRS-M) is deasserted, and then attempts to resend the frame to the PHY module for retransmission on the bus. The first retransmission attempt occurs one IPG time after the listening signal (CRS) is deasserted again. However, if this will result in another collision, the MAC module introduces a random variable backoff time starting from the second retransmission attempt to avoid infinitely repeated collisions.

[0061] The problem with CSMA / CD is that when the bus is quiet, multiple nodes may attempt to transmit data on the bus simultaneously. This results in collisions, corrupted data, timeouts, and loss of bus capacity, which in turn may cause the effective bus throughput to drop significantly or even completely collapse as the total bus load approaches the maximum bus capacity (e.g., becomes approximately 70% of the maximum bus capacity).

[0062] Figure 2 An example of a collision avoidance mechanism developed to increase bus capacity is shown. This mechanism is called physical layer collision avoidance (PLCA) and uses a coordination module / layer connected between the MAC module and the PHY module using the corresponding IEEE standard media independent interface (MII). Each MII may include the same set of pins: transmit data (TXD[3:0]), transmit enable (TXEN), transmit error (TXER), receive data (RXD[3:0]), received data valid (RXDV), receive error (RXER), collision detection (COL) and carrier sense (CRS), and in addition two clock signals (TXCLK and RXCLK, not shown), as defined in IEEE802.3 Clause 22.

[0063] PLCA uses a round-robin scheme in which nodes are numbered and have the opportunity to transmit one at a time starting from a dedicated time slot (or transmission opportunity) in a round-robin manner based on their number. One node is assigned as the head node (or PLCA coordinator) and each cycle begins with a beacon. If a node does not transmit data at its transmission opportunity, the transmission opportunity is passed to the next node. The coordination module knows when its node's transmission opportunity occurs based on the node number, and manages the MAC module using conflict (COL-M) and listen (CRS-M) signal manipulation to prevent the MAC module from sending data that cannot be transmitted by the PHY module. In this way, the coordination module passes data to the PHY module only when there is a transmission opportunity. Therefore, the combination of the round-robin scheme and the coordination module avoids conflicts on the bus. Since there should be no conflict events for the PHY module to report, the COL-P pin becomes functionally redundant (and therefore in Figure 3 grayed out in the display), but can still be used to detect real bus problems.

[0064] Figure 3 An example of a PLCA mechanism involving a coordination module having a data buffer (e.g., a first-in, first-out buffer) is shown. The data buffer addresses a scenario where the coordination module begins receiving data from the MAC module shortly before a node's transmission opportunity. In this scenario, the data has been sent from the MAC module too early to be transmitted immediately, but too late for the coordination module to signal a conflict and retransmit the data in time for the upcoming transmission opportunity. Therefore, the data buffer enables the coordination module to temporarily store data sent from the MAC module so that the data can be passed to the PHY module for transmission at the upcoming transmission opportunity.

[0065] Figure 4 Shows the use of the MAC module by the node Figure 3 1. Transmission attempts (MAC-TXDATA) on a fully loaded bus with a collision avoidance mechanism, where frames are available in the MAC modules of the respective nodes in time to take advantage of each transmission opportunity. In this figure, four nodes are transmitting data on the bus, where each node transmits a single data frame at each of its respective transmission opportunities. The numbering of the nodes is provided for illustrative purposes and is non-limiting (e.g., in practice, the head node may be numbered "0"). The first transmission attempt of node 2 for data frames 1-3 is denoted F1-F3, respectively, and the second (re)transmission attempt is denoted F1'-F3', respectively.

[0066] The coordination module receives a detection signal (CRS-P) from the PHY module indicating transmission activity detected on the bus. The detection signal substantially follows the bus schedule, but with a slight delay, depending on the responsiveness of the PHY module to detect and report bus activity. The coordination module is configured to de-assert the listening signal (CRS-M) whenever the detection signal (CRS-P) is de-asserted, unless the MAC module has made an earlier transmission attempt for the same frame, as described below.

[0067] The MAC module is configured to send data to the coordination module whenever the MAC module has a pending frame for transmission and the listening signal (CRS-M) has been de-asserted by the coordination module. However, in order to ensure the minimum gap between frames of most Ethernet PHY types, the MAC module will delay the waiting time for sending data to the coordination module after the de-assertion of the listening signal (CRS-M). In this example shown, the waiting time of the MAC module is equal to the packet gap (IPG) length (e.g., 12 bytes). Then, the coordination module re-asserts the listening signal (CRS-M) again when receiving data from the MAC module or when detecting activity on the bus via the detection signal (CRS-P). In the example shown in this article, the de-assertion of the listening signal (CRS-M) is directly related to the de-assertion of the detection signal (CRS-P), but the re-assertion of the listening signal (CRS-M) is slightly delayed relative to the re-assertion of the detection signal (CRS-P). This is intended to help ensure that the MAC module sends pending data after the waiting time, even if the transmission opportunity is shorter than 1 IPG (but this may not be necessary). Therefore, the re-assertion of the listening signal (CRS-M) may also be directly related to the re-assertion of the detection signal (CRS-P).

[0068] When the listening signal (CRS-M) is deasserted, data from the MAC module is buffered in the coordination module, provided that the buffer does not overflow. If the transmission attempt made by the MAC module cannot be fully aligned with the transmission opportunity of the node using the buffer, the coordination module is configured to assert the conflict signal (COL-M) to stop the MAC module from continuing to send data. This occurs by default when another node starts transmitting a data frame on the bus and the detection signal (CRS-P) is asserted. The coordination module then deasserts the conflict signal (COL-M). The conflict signal (COL-M) only needs to be asserted long enough to be recognized by the MAC module, and ideally should be as short as possible (e.g., one clock cycle) to avoid any time loss before recovery.

[0069] After the collision signal (COL-M) is asserted by the coordination module, the listening signal (CRS-M) is not immediately de-asserted. This is for two reasons. First, the MAC module requires a recovery time (CR) after the assertion of the collision signal, and then the MAC module can resend the data as part of the upcoming transmission attempt. Secondly, it is more efficient for the bus to try and ensure that the retransmission attempt is synchronized with the upcoming transmission opportunity to avoid any additional delay in transmitting the data frame. To achieve this, the listening signal (CRS-M) remains asserted until the data can be transmitted directly at the upcoming transmission opportunity without buffering, and then is de-asserted after the recovery time of the MAC module to enable the transmission.

[0070] The data frame is then passed by the coordination module to the PHY module for transmission (PHY-TXDATA) starting from the upcoming transmission opportunity. It should be mentioned that the transmission opportunity can be relatively short (e.g., shorter than the IPG length) and generally does not provide enough time for a node to transmit a complete frame. Instead, they provide a time slot or window for a node to claim the bus before the opportunity times out and the next node has a chance. A node can claim the bus during a transmission opportunity by starting to transmit a data frame or a fill sequence (SYNC symbol). For example, the coordination module can be configured to transmit a SYNC symbol on the bus via the PHY layer module during the waiting time of the MAC module. Once the bus has been claimed by a node, the node can continue to transmit any frame size or even multiple data frames (if configured to allow this).

[0071] exist Figure 4 In the example of FIG. 1 , the upcoming transmission opportunity of frame 1 of node 2 is the next transmission opportunity on the bus schedule after the (virtual) collision. On the other hand, for frames 2 and 3 of node 2, there are intervening transmission opportunities of other nodes on the bus schedule. Since the coordination module keeps the listening signal (CRS-M) asserted until the frame can be retransmitted at the corresponding upcoming transmission opportunity, the de-assertion of the listening signal (CRS-M) that would otherwise follow the detection signal (CRS-P) from the PHY module is skipped.

[0072] Figure 5 Shows the use of the MAC module by the node Figure 3 The conflict avoidance mechanism of the bus is used to avoid additional transmission attempts. Figure 4Unlike the example of , one of the transmission opportunities of node 2 has timed out. This is because frame 3 of node 2 only becomes available in the MAC module at some time during the transmission of frame 3 of node 1. Since the MAC module will delay the waiting time of one IPG for sending data to the coordination module after the de-assertion of the listening signal (CRS-M), if the transmission opportunity ends within about 1 IPG length after the de-assertion of the listening signal (CRS-M), there is not enough time for the node to start transmitting frame 3 of node 2 in the upcoming transmission opportunity. Therefore, the coordination module asserts the collision signal (COL-M) and the listening signal (CRS-M), and keeps the listening signal (CRS-M) asserted until the next transmission opportunity of the node is detected, at which time the listening signal is de-asserted to enable the transmission of the frame on the bus. It is worth noting here that although the coordination module can temporarily store a limited amount of data in the buffer, if any other node transmits data between the transmission opportunities of this node, the buffer is refreshed (otherwise, a large buffer will be required in the coordination module to store the complete frame). For this reason, Frame 3 cannot be stored in the buffer in preparation for the next transmission opportunity of Node 2 (hence, the collision signal is asserted and the first transmission attempt is aborted).

[0073] Figure 6 Shows the use of the MAC module by the node Figure 3 In this example, the consecutive transmission opportunities of nodes 3, 4, and 1 have each timed out, leaving node 2 the only node transmitting on the bus for the duration. This is referred to herein as a "boomerang transmit opportunity" for node 2, where the transmission opportunity of this node returns without any intervening transmissions from other nodes.

[0074] As shown, one IPG length after the listening signal (CRS-M) is deasserted after node 1 transmits the first frame, the MAC module of node 2 attempts to transmit frame 1. Since this is too late for transmission at the upcoming transmission opportunity of node 2, the coordination module temporarily stores frame 1 in a buffer until the next transmission opportunity arrives, at which time frame 1 is transmitted on the bus by the PHY module. This is only possible because there are no intervening transmissions from other nodes, otherwise the buffer would have been flushed and the conflict signal would have been asserted (according to Figure 5). The result is that the transmission of frames 1-3 by node 2 is delayed by the buffer until the corresponding transmission opportunity of the node, without any retransmission attempt by the MAC module. In contrast, the collision signal (COL-M) is asserted for frames 4 and 5, because frames 4 and 5 are received from the MAC module in the presence of intervening transmissions by other nodes. Therefore, similar to the previous example, these frames are retransmitted at the next transmission opportunity.

[0075] Although the PLCA mechanism successfully avoids conflicts on the bus by preventing transmissions outside of a node's scheduled transmission opportunities, the use of data buffers in the coordination module complicates the system and the benefits of using data buffers in the coordination module are lost when the MAC module attempts to send more data than the buffer can temporarily store before the data can be transmitted on the bus, or when any other node transmits a frame. In addition, the time period during which data is transmitted too early from the MAC module but too late to retransmit after a virtual conflict is relatively short relative to the total bus cycle time. In view of the above, it may be difficult to justify the additional cost and complexity associated with the data buffer.

[0076] Embodiments of the present disclosure

[0077] Figure 7 An example of a collision avoidance mechanism involving a coordination module (or layer) is shown that solves the above problem without requiring a data buffer. In this example, the coordination module is configured to assert a collision signal by default when a MAC module (or layer) sends data as part of a first transmission attempt, and to control a listening signal to enable retransmission of data at a second transmission attempt by the MAC module.

[0078] The expression "by default" may be used to mean that the conflict signal is asserted regardless of when data is received from the MAC module relative to the bus schedule of the multi-drop bus network. In addition, the coordination module is configured to perform the above assertion and control steps for all data (e.g., data frames or data packets) received from the MAC module.

[0079] The upcoming transmission opportunity may be the first or second upcoming transmission opportunity on the bus schedule of the node, depending on how much time is left until the start of the first upcoming transmission opportunity. In other words, there is a cut-off time point (known to the coordination module) when data can no longer be transmitted in the first upcoming transmission opportunity and needs to be postponed until the second upcoming transmission opportunity. It is worth noting here that there is no real penalty for postponing the transmission of data by one bus cycle. For coordination modules with data buffers, there is also a cut-off point, the only difference is that buffering allows the cut-off point to be closer in time to the start of the first upcoming transmission opportunity because the data is available in the buffer for passing to the PHY module (or layer).

[0080] Figure 8 Show the use Figure 7 The collision avoidance mechanism of the node avoids the transmission attempt (MAC-TXDATA) made by the MAC module of the node and the associated data transmission (PHY-TXDATA) made by the PHY module of the node on the fully loaded bus to Figure 4 For comparison. Although the bus schedule is shown as having a fixed bus cycle time and a fixed frame length for a node, this is merely an example and is not required. Each attempt by the MAC module to transmit a frame is initially blocked by asserting a collision signal (COL-M), and retransmission of the data frame is initiated by de-assertion of the listen signal (CRS-M) when approaching a transmission opportunity, so that the retransmitted data frame can be transmitted directly on the bus by the PHY module without buffering.

[0081] exist Figure 8 In the example, all collisions occur substantially before the first upcoming transmission opportunity of the node. Therefore, there is sufficient time to retransmit all data frames at the first upcoming transmission opportunity, rather than deferring the data frames until the second upcoming transmission opportunity. However, in other examples, collisions may occur closer to the cutoff point. The cutoff point itself depends on a number of factors and may be determined by the coordination module. For example, the coordination module may be configured to determine the recovery time (CR) and latency of the MAC module of the coordination module by monitoring the timing properties of the MAC module or by obtaining the timing properties from a register. In addition, the response time taken by the PHY module to provide a detection signal (CRS-P) indicating activity from other nodes on the bus may vary, but should be known for a particular PHY module design.

[0082] Since the amount of data transmitted by each node is variable and some transmission opportunities may time out, the node needs to monitor bus activity to determine when the bus has been released by the immediately preceding node. To achieve this, the coordination module can be configured to receive a detection signal (CRS-P) from the PHY module indicating activity from other nodes on the network, and de-assert the listening signal (CRS-M) once the detection signal indicates that the immediately preceding node is no longer active or has timed out.

[0083] Compared to the case where the coordination module has a data buffer Figure 4 In the example of , the transmission attempt made by the MAC module of node 2 (MAC-TXDATA) and the resulting transmission on the bus (PHY-TXDATA) are unchanged. This is because Figure 4 The transmission attempt of each data frame in is consistent with the transmission opportunities of other nodes, thereby requiring the assertion of a virtual collision (COL-M) and subsequent retransmission of the frame.

[0084] Fig. 9 The MAC module of node 2 uses Figure 7 The transmission attempt of the collision avoidance mechanism is to Figure 5 For comparison. Similar to Figure 5 In the example of Node 2, the transmission opportunity of frame 3 times out because the frame arrives too late to be used for transmission at the first upcoming transmission opportunity.

[0085] Fig.10 The MAC module of node 2 uses Figure 7 The additional transmission attempts by the collision avoidance mechanism are Figure 6 . As previously described, the consecutive transmission opportunities of nodes 3, 4, and 1 have each timed out, leaving node 2 as the only node transmitting on the bus for the duration (i.e., the boomerang transmission opportunity). However, this time, rather than buffering portions of frames 1-3 as they are received from the MAC module, the coordination module aborts the first transmission attempt by asserting a collision signal (COL-M) and deasserting a listen signal (CRS-M) at the upcoming transmission opportunity to enable transmission of these frames at the second transmission attempt. The transmission attempt by the MAC module and the resulting transmission on the bus remain unchanged for frames 4 and 5, since frames 4 and 5 are received from the MAC module during transmissions by other nodes.

[0086] The above example shows that the use of data buffers in the coordination module has no effect on bus efficiency unless the suspension and retransmission of data frames cannot adapt to the time between boomerang transmission opportunities. This situation is unlikely to occur in most practical situations because the duration of a transmission opportunity (although not absolutely quantitative in the standard) may not actually be very short, and may therefore be a considerable portion of the IPG. Therefore, only about 2-3 skipped transmission opportunities may be required to adapt. In addition, even if the suspension and retransmission do not fully adapt, the coordination module can be configured to declare the bus at the upcoming transmission opportunity and send a SYNC symbol until the MAC module is ready for retransmission. This is possible because once the coordination module has asserted a conflict, the coordination module knows that the frame is pending.

[0087] The advantage of communicating the collision to the MAC module for each first transmission attempt of a data frame, rather than buffering the data in the coordination module, is that it allows the frame to be inspected and any necessary action taken before it is transmitted. For example, it may be checked whether a given destination and / or message type is allowed for use by this node, and if not, the frame may be deleted by not sending it on the bus when it is retransmitted.

[0088] Figure 11-13 Shown separately Figure 8-10 transmission attempts, wherein the listening signal is deasserted between transmissions of the node. This aspect of the present disclosure recognizes that it is neither necessary nor effective for the coordination module's listening signal (CRS-M) to follow the PHY module's detection signal (CRS-P). Figure 8-10 It can be seen that whenever another node is transmitting on the bus, the assertion of the listening signal (CRS-M) blocks the MAC module's first transmission attempt for a data frame, and when the listening signal (CRS-M) is de-asserted, the data frame is unavailable. To address this, the coordination module can be configured to de-assert the listening signal (CRS-M) once the data frame has been transmitted, and then keep the listening signal (CRS-M) de-asserted until the next data frame is received from the MAC module.

[0089] like Figure 11-13 As shown in , this approach means that the MAC module can initiate a first transmission attempt for a data frame whenever data becomes available (even after a waiting time) without being blocked by transmissions from other nodes. In addition, the assertion and de-assertion of the listen signal after a virtual collision (CRS-M) is not affected and follows the previously described behavior to enable transmission of the data frame at the second transmission attempt.

[0090] If the bus is overloaded, there may be more than one frame pending transmission in the MAC module at the node's earlier transmission opportunity. If the node is only allowed to transmit one frame per transmission opportunity, and the MAC module attempts to send the second data frame for the first time directly after the first data frame, the coordination module may be configured to pass the first data frame to the PHY module for retransmission on the bus, and when the retransmission of the first data frame has been completed, the conflict signal (COL-M) is asserted by default for the second data frame. In this case, the second data frame will be automatically prepared by the MAC module so that it can be retransmitted at a subsequent transmission opportunity when the coordination module de-asserts the listening signal (CRS-M). This can help reduce inefficiencies on the bus. On the other hand, if the node is allowed to transmit multiple frames per transmission opportunity, the first N frames can be transmitted directly (assuming that the MAC module has at least N frames in its buffer), and the conflict signal (COL-M) can be used to prevent the (N+1)th frame from being transmitted.

[0091] Although the illustrated example shows that each transmission opportunity is limited to the transmission of a single data frame, a node may also transmit multiple data frames within a single sequence starting from a transmission opportunity. To allow this, the coordination module may be configured to insert an active-idle sequence between adjacent data frames in the sequence to prevent the bus from becoming idle before multiple data frames have been transmitted. Note that in this scenario, the listen signal to the MAC module is de-asserted after each frame, while the signal driven on the bus is active-idle. This is done to ensure that the MAC module keeps sending frames until a predefined maximum number of frames in the burst. Once the maximum number is reached, any additional frames will be blocked by indicating a conflict to the MAC module, where a retransmission is performed at the next transmission opportunity. If the number of frames for the MAC module is less than the maximum allowed number of frames available for transmission as a burst, the transmission will time out and stop driving active-idle.

[0092] like Figure 7 As shown in , each node of the multi-point bus network may include a MAC module, a PHY module and a coordination module. The multi-point bus network may be an Ethernet network, the MAC module may be an Ethernet CSMA / CD MAC layer, and the PHY module may be a 10BASE-T1S PHY layer. In addition, in view of the Figure 7 The coordination module described does not require a data buffer; the coordination module may be unbuffered. Even in the "unbuffered" example where there is no data buffer for storing the first portion of a frame until the next transmission opportunity, the coordination module may still include a small buffer of a few bits in size to facilitate parsing of data between layers / modules of the Ethernet protocol. However, even if the coordination module includes a data buffer (e.g., Figure 3), the associated collision avoidance mechanism still applies. As mentioned previously, one possible advantage of maintaining a data buffer in the coordination module is that if the buffered data is immediately available for transfer to the PHY module, the cutoff point for deciding whether to retransmit data from the MAC module at the first upcoming transmission opportunity or whether to defer retransmission until the second upcoming transmission opportunity can be closer to the start of the first upcoming transmission opportunity.

[0093] It should be noted here that the head node of the 10BASE-T1S bus utilizing PLCA transmits a beacon to indicate the start of a new bus cycle. This also allows other nodes to synchronize and detect how many nodes are present on the bus (node ​​count before the cycle restarts). For simplicity, beacons are not included in the figure. However, the presence of beacons does not hinder the applicability of the ideas / concepts described in this article.

[0094] Although the coordination module (or layer) has been described herein with reference to the MAC and PHY modules (or layers), the coordination module may be formed independently of the other modules and incorporated into the node during a subsequent modular assembly process. In some cases, the coordination module may even be retrofitted to an existing node. Alternatively, the coordination module may be integrated with other modules of the node at the time of manufacture (e.g., as a different part / portion of the same chip). One or more (or each) modules may include a circuit system including at least one processor and at least one memory including computer program code. The at least one memory and computer program code may be configured to, together with the at least one processor, cause the module to perform the associated functionality described herein.

[0095] Fig.14 The main steps of the method for conflict avoidance of nodes in a multi-point bus network are schematically shown. As shown in the figure, the method comprises:

[0096] receiving data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data;

[0097] asserting a conflict signal by default when receiving the data from the MAC module so that the MAC module stops sending the data; and

[0098] A snoop signal is controlled to cause the MAC module to resend the data as part of a second transmission attempt so that the data can be transmitted on the multi-point bus network via the PHY module of the node at an upcoming transmission opportunity.

[0099] Fig.15Schematically illustrates a computer / processor readable medium providing a computer program according to an example. The computer program may include computer code configured to execute, control or enable the use of the coordination module described herein. Fig.14 In this example, the computer / processor readable medium is an optical disc, such as a digital versatile disc (DVD) or a compact disc (CD). In other embodiments, the computer / processor readable medium can be any medium that has been programmed in a manner to perform the functions of the present invention. The computer / processor readable medium can be a removable storage device, such as a memory stick or memory card (SD, mini SD, micro SD or nano SD) or an embedded or external non-volatile memory (e.g., flash memory or MRAM).

[0100] Unless a specific order is explicitly stated, the instructions and / or flow chart steps in the above figure may be executed in any order. Moreover, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to produce other examples and should be understood within the context provided in this specific embodiment.

[0101] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed and controlled with the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.

[0102] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. One or more non-transitory machine or computer usable media as defined herein do not include signals, but such one or more media are capable of receiving and processing information from signals and / or other temporary media.

[0103] Example embodiments of the materials discussed in this specification may be implemented in whole or in part via network, computer or data-based devices and / or services. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services.

[0104] In one example, one or more instructions or steps discussed herein are automatic. The term automation or automatic (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems and / or processes without human intervention, observation, effort and / or decision making.

[0105] It should be understood that any components that are said to be coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be placed between the two components that are said to be coupled.

[0106] In this specification, example embodiments have been presented in terms of a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A coordination module for a node of a multipoint bus network, characterized in that: The coordination module includes a circuit system configured to: receiving data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data; asserting a conflict signal by default when receiving the data from the MAC module, so that the MAC module stops sending the data; as well as The snoop signal is controlled to cause the MAC module to resend the data as part of a second transmission attempt, so that the data can be transmitted on the multi-point bus network via the PHY module of the node at an upcoming transmission opportunity.

2. The coordination module according to claim 1, characterized in that: The coordination module is configured to control the listening signal such that the second transmission attempt is synchronized with the upcoming transmission opportunity of the node.

3. The coordination module according to claim 1 or 2, characterized in that: The coordination module is configured to: asserting the sense signal when the data is received from the MAC module as part of a first transmission attempt; and The sense signal is maintained asserted until the data can be transmitted at the upcoming transmission opportunity as part of the second transmission attempt, at which time the sense signal is de-asserted by the coordination module.

4. The coordination module according to claim 3, characterized in that: The MAC module is configured to delay retransmission of the data by a waiting time after de-assertion of the listening signal, and wherein the coordination module is configured to transmit a fill sequence during the waiting time of the MAC module to prevent the upcoming transmission opportunity of the node from timing out.

5. The coordination module according to claim 4, characterized in that: The waiting time is equal to the packet gap length.

6. The coordination module according to any one of claims 3 to 5, characterized in that: The MAC module requires a recovery time after assertion of the collision signal, whereupon the MAC module can resend the data as part of the second transmission attempt, and wherein the coordination module is configured to wait at least the recovery time before deasserting the listening signal.

7. A node of a multipoint bus network, characterized in that: The node comprises the coordination module according to any of the preceding claims, the MAC module and the PHY module.

8. A multi-point bus network, characterized in that: Comprising a plurality of nodes according to claim 7.

9. A method for avoiding conflicts among nodes in a multipoint bus network, characterized in that: The method comprises: receiving data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data; asserting a conflict signal by default when receiving the data from the MAC module so that the MAC module stops sending the data; and The snoop signal is controlled to cause the MAC module to resend the data as part of a second transmission attempt, so that the data can be transmitted on the multi-point bus network via the PHY module of the node at an upcoming transmission opportunity.

10. A computer program, characterized in that comprising computer code configured to perform the method according to claim 9.

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