Apparatus and method for separate write enable for single pass access of data, metadata, and parity information

By introducing a multi-column planar structure and corresponding write enable signals and column selection signals into semiconductor memory, the problem of difficulty in efficient single-pass access in the memory in the prior art is solved, efficient access to data, metadata and error correction information is achieved, and the performance and efficiency of the memory are improved.

CN119856149APending Publication Date: 2025-04-18MICRON TECHNOLOGY INC
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Patent Information

Application Number
CN202380064291.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2022-11-15
Filing Date
2023-10-10
Publication Date
2025-04-18

AI Technical Summary

Technical Problem

When existing semiconductor memory stores error correction information and metadata associated with data, it is difficult to efficiently perform single pass access, resulting in increased performance losses and delays.

Method used

By introducing a multi-column planar structure in memory, including a data column plane, a metadata column plane and an error correction code column plane, and using write enable signals and column selection signals, efficient single pass access to data, metadata and error correction information is achieved.

Benefits of technology

It realizes simultaneous storage and accessing data, metadata and error correction information in a single access pass, reducing the access delay and power consumption of the memory, and improving the performance and efficiency of the memory.

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Abstract

Devices, systems, and methods for separate write enable signals for data, metadata, and parity information. The memory array is divided into a column plane and an additional column plane. In some modes of the memory device, data and parity information are stored in the column plane and metadata is stored in the additional column plane. The additional column plane includes separate write enable signals (or separate states of a single signal) that activate different portions of bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the additional column plane along with one or another write enable signal such that fewer bit lines than all the bit lines activated by the column select signal provide data.
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