Design method for PCIE interface communication between processor and FPGA

Abstract

The invention belongs to the technical field of digital communication, and particularly relates to a PCIE (Peripheral Component Interconnect Express) interface communication design method between a processor and an FPGA (Field Programmable Gate Array), which comprises the following steps of: after the FPGA is powered on, reading a configuration data stream from a FLASH to a static region, and after the FPGA is configured, preparing a PCIE interface, so that the FPGA sets a reset signal of a CPU (Central Processing Unit) to be invalid, and the CPU starts to scan the PCIE of the FPGA. After the CPU is started, the configuration data flow is written into the internal ICAP core of the FPGA through the PCIE interface, and then full-function configuration of the FPGA is achieved. According to the method, the control of the FPGA on the CPU reset signal is realized, the separation design of the PCIE interface program and other functional software is realized through the FPGA software design, and finally the problems that the CPU fails to enumerate the PCIE interface of the FPGA in the initialization stage and the PCIE driver at the CPU end collapses due to reconfiguration of the FPGA in the use process are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of digital communication, and in particular relates to a PCIE interface communication design method between a processor and an FPGA. Background Art

[0002] As communication systems place increasingly higher latency requirements on data processing in link node devices, latency requirements in aerospace and other electronic systems have even reached microseconds. The processing performance of processors (such as general-purpose processor chips such as CPU / DSP) can no longer meet such low latency requirements. Therefore, heterogeneous computing has become the mainstream of embedded board design, and processor + FPGA hardware architecture design has become the mainstream approach in communication systems.

[0003] Due to the microsecond processing delay requirement, the traditional low-speed interface (local bus / SPI / UART) transmission between the processor and FPGA can no longer meet the requirements. Currently, PCIE interface communication has become the first choice for the communication interface between the processor and FPGA. The processor serves as the host of PCIE and the FPGA serves as the slave of PCIE.

[0004] If hardware using the processor + FPGA architecture is designed using traditional methods, there are often two common problems: 1. The processor fails to scan the PCIE interface. After the processor is powered on, it will first scan the peripheral hardware. If the FPGA is not successfully started at this time, the scan will fail. After the system is loaded, the FPGA's PCIE interface cannot be recognized, and the processor and FPGA will eventually fail to communicate. A more clumsy method is to modify the processor's startup configuration items until a suitable startup time is found to wait for the FPGA to start successfully, and then scan the peripheral hardware.

[0005] 2. During use, if the FPGA needs to be reconfigured and its internal functions need to be changed, during the reconfiguration process, due to the reconfiguration of the PCIE interface, it is found in actual projects that the operating system in the processor will cause a crash. Even if it does not crash, subsequent interface communications will still be abnormal, which is quite troublesome. Summary of the invention

[0006] In order to solve the interface problem caused by the failure of processor enumeration PCIE and reconfiguration of FPGA in the hardware architecture design of processor+FPGA, the present invention provides a method for designing PCIE interface communication between a processor and FPGA.

[0007] The present invention is implemented by adopting the following technical solution: a design method for PCIE interface communication between a processor and an FPGA, the specific method is as follows: 1) Connect the processor's reset signal to the FPGA, configure the FPGA to start in Master mode, and start by reading the external configuration Flash; before the FPGA is successfully configured, the processor is in a reset state. After the FPGA is successfully configured, the FPGA sets the processor's reset signal to be invalid, and the processor starts to scan the peripheral hardware. This time, the PCIE interface must be scanned successfully; 2) Compile the PCIE interface program into the internal static area of ​​the FPGA. After the FPGA is powered on, the static area content is automatically configured. The other functions of the FPGA are configured by writing the processor into the FPGA's ICAP core, which will not cause any impact on the FPGA's PCIE interface, thereby solving the interface crash problem caused by reconfiguring the FPGA.

[0008] The present invention realizes FPGA's control of CPU reset signals through hardware design, realizes the separation design of PCIE interface program and other functional software through FPGA software design, and finally solves the problem that CPU fails to enumerate FPGA's PCIE interface in the initialization stage and the problem that FPGA reconfiguration during use causes CPU-side PCIE driver crash. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a hardware composition diagram provided by the present invention.

[0010] Figure 2 The present invention provides an implementation flow chart. DETAILED DESCRIPTION

[0011] The present invention designs the hardware of the processor + FPGA architecture and separates the functional development of the FPGA program, thereby solving the processor PCIE interface scanning problem and the PCIE interface reconfiguration problem. The specific method is as follows: 1. The reset signal of the processor is connected to the FPGA, and the FPGA is configured to start in Master mode, and it starts by reading the external configuration Flash. Before the FPGA is successfully configured, the processor is in a reset state. After the FPGA is successfully configured, the reset signal of the FPGA setting processor is invalid, and the processor starts to scan the peripheral hardware. This time, the PCIE interface can be scanned successfully with high real-time performance.

[0012] 2. Design and compile the PCIE interface program and other programs of the FPGA separately. Because the PCIE interface program is relatively fixed, once the link rate and version are determined, there is no need to change it; and as a programmable logic device, FPGA often needs to be reconfigured to achieve other functions. The traditional development method of FPGA is to treat the PCIE interface program and other functions as a project, compile and download them uniformly, which will lead to modifications of FPGA functions, and the PCIE interface program will also change due to configuration, because not all PCIE interfaces on the processor side support hot plugging, which can easily cause processor-side driver crashes and communication failures. The present invention utilizes the local dynamic reconfigurable technology of FPGA, compiles the PCIE interface program into the internal static area of ​​FPGA, and automatically configures the static area content after FPGA is powered on. The other functions of FPGA are configured by writing the processor into the ICAP core of FPGA, which will not cause any impact on the PCIE interface of FPGA, thereby solving the interface crash problem caused by reconfiguring FPGA. Example

[0013] A hardware design scheme of CPU+FPGA mode is provided. FPGA can support multiple business functions, which are called business components x. After FPGA is powered on, it automatically reads the configuration data stream (PCIE interface program) from SPI FLASH to the static area. After FPGA configuration is completed, the PCIE interface is ready. At this point, FPGA sets the reset signal of CPU to invalid, and CPU starts to scan PCIE of FPGA.

[0014] After the CPU is started, it reads data from the component storage FLASH to the memory according to demand, and then writes the configuration data stream of the business component x into the internal ICAP core of the FPGA through the PCIE interface, thereby realizing the full function configuration of the FPGA. At this point, the FPGA has completed full function loading and can provide related services.

Claims

1. A method for designing PCIE interface communication between a processor and an FPGA, characterized in that: The specific method is as follows: 1) Connect the processor's reset signal to the FPGA, configure the FPGA to start in Master mode, and start by reading the external configuration Flash; before the FPGA is successfully configured, the processor is in a reset state. After the FPGA is successfully configured, the FPGA sets the processor's reset signal to be invalid, and the processor starts to scan the peripheral hardware. This time, the PCIE interface must be scanned successfully; 2) Compile the PCIE interface program into the internal static area of ​​the FPGA. After the FPGA is powered on, the static area content is automatically configured. The other functions of the FPGA are configured by writing the processor into the FPGA's ICAP core, which will not cause any impact on the FPGA's PCIE interface, thereby solving the interface crash problem caused by reconfiguring the FPGA.

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