Defect detection system for ferromagnetic metal device

Abstract

The invention provides a defect detection system for a ferromagnetic metal device, which is characterized in that a magnetic flux leakage detection excitation coil winds around a C-shaped magnetic core to apply a first magnetic field to a to-be-detected ferromagnetic metal device, and an eddy current detection excitation coil applies a second magnetic field to the to-be-detected ferromagnetic metal device, the tunneling effect magnetoresistive sensor array collects a first magnetic signal under the action of a first magnetic field and collects a second magnetic signal under the action of a second magnetic field; each signal processing circuit receives a first magnetic signal and a second magnetic signal from the connected tunneling effect magnetoresistive sensor; and the FPGA main control module is used for respectively determining a magnetic flux leakage detection result and an eddy current detection result based on the first magnetic signals and the second magnetic signals received by all the signal processing circuits. According to the technical scheme, eddy current detection and magnetic flux leakage detection methods are combined, the high-sensitivity TMR sensor array and the efficient FPGA data processing system are adopted, and the detection capacity of the buried defects in the ferromagnetic metal material is improved.

Description

Technical Field

[0001] The present application relates to the technical field of metal detection, and in particular to a defect detection system for ferromagnetic metal devices. Background Art

[0002] Ferromagnetic metal materials are widely used in the manufacture of mechanical parts, vehicle pipelines, etc. Structural inspection during their production and use is essential to ensure product quality and structural safety. Electromagnetic testing technologies, including eddy current testing (ECT) and magnetic flux leakage testing (MFL), play an irreplaceable role in metal structure testing. However, existing testing technologies have some limitations when facing ferromagnetic metal materials with high magnetic permeability.

[0003] The eddy current detection method determines whether there are defects in the sample by measuring the secondary magnetic field generated by eddy currents in the sample being tested. However, for ferromagnetic metal materials with high magnetic permeability, such as carbon steel, the eddy current detection method faces challenges in detecting buried defects in metals. Since the penetration depth of eddy currents in these materials is very small, this characteristic is not conducive to the use of eddy currents to detect buried defects in metals. In order to increase the penetration depth of eddy currents inside metal materials, the frequency of the excitation signal should be reduced. However, for traditional eddy current detection probes that use induction coils as secondary magnetic field signal receiving sensors, as the frequency of the excitation signal decreases, the sensitivity of the signal receiving coil will also decrease, which will cause the signal-to-noise ratio of the detection system to deteriorate.

[0004] Magnetic flux leakage detection is another widely used technique for defect detection of ferromagnetic materials. This method requires applying a strong magnetic field to the sample to magnetize it and reach a state of magnetic saturation, and then using a magnetic sensor to detect the magnetic flux leakage caused by the defect, ultimately achieving the detection of metal defects. However, the main disadvantage of magnetic flux leakage detection is that it is insensitive to small defects, especially defects such as cracks that form in a direction parallel to the magnetic field lines.

[0005] Therefore, how to overcome the limitations of eddy current testing and magnetic flux leakage testing in the existing technology and improve the detection capability of buried defects in ferromagnetic metal materials has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The embodiment of the present application provides a defect detection system for ferromagnetic metal devices, aiming to solve the technical problem in the related art that eddy current detection and magnetic flux leakage detection are insufficient in detecting buried defects in ferromagnetic metal materials.

[0007] In a first aspect, an embodiment of the present application provides a defect detection system for ferromagnetic metal devices, including: a defect detection probe, including a leakage magnetic detection excitation coil, an eddy current detection excitation coil, a C-shaped magnetic core, a printed circuit board, an insulating shell and a tunneling effect magnetoresistive sensor array, the leakage magnetic detection excitation coil is wound around the C-shaped magnetic core, and is configured to apply a first magnetic field to the ferromagnetic metal device to be tested through the C-shaped magnetic core when it is in a power-on state, the eddy current detection excitation coil is wound around the insulating shell, and is configured to apply a second magnetic field to the ferromagnetic metal device to be tested when it is in a power-on state, the tunneling effect magnetoresistive sensor array includes a plurality of tunneling effect magnetoresistive sensors fixed on the printed circuit board, each of the tunneling effect magnetoresistive sensors is configured to collect a first magnetic signal under the action of the first magnetic field and a second magnetic signal under the action of the second magnetic field; a plurality of signal processing circuits, respectively. Connected to multiple tunneling effect magnetoresistive sensors, each of the signal processing circuits is configured to receive the first magnetic signal and the second magnetic signal from the connected tunneling effect magnetoresistive sensor; a data acquisition module is connected to the multiple signal processing circuits and is configured to obtain the first magnetic signal and the second magnetic signal received by each signal processing circuit; an FPGA main control module is connected to the data acquisition module and an external computer, and is configured to drive the data acquisition module to obtain the first magnetic signal and the second magnetic signal received by each signal processing circuit in response to a detection instruction from the computer, and determine the leakage magnetic detection result and the eddy current detection result based on the first magnetic signal and the second magnetic signal received by all the signal processing circuits, and is also configured to feed back the leakage magnetic detection result and the eddy current detection result to the computer.

[0008] In one embodiment of the present application, optionally, a plurality of the tunneling effect magnetoresistive sensors are arranged in a single row with their sensitive axes parallel to each other, a first end of each of the tunneling effect magnetoresistive sensors is grounded, and a second end of each of the tunneling effect magnetoresistive sensors is connected to the corresponding signal processing circuit.

[0009] In one embodiment of the present application, optionally, the C-shaped magnetic core includes a first part, a second part parallel to the first part, and a middle part connecting the first part and the second part, the first part, the second part and the middle part are surrounded to form a C-shaped structure, and the leakage magnetic detection excitation coil is wound around the middle part; the insulating shell has a bottom supporting foot, and the eddy current detection excitation coil is wound around the bottom supporting foot; the printed circuit board is embedded in a recess surrounded by the first part, the second part and the middle part, the insulating shell is embedded in the recess and wraps the printed circuit board, and the first part and the second part each have one end away from the middle part on the same side as the bottom supporting foot; the direction of the magnetic lines of force of the C-shaped magnetic core in the ferromagnetic metal device to be tested is from the first part to the second part, and is perpendicular to the sensitive axis direction of each of the tunneling effect magnetoresistive sensors.

[0010] In one embodiment of the present application, optionally, the insulating shell has two bottom supporting feet, the two bottom supporting feet are arranged opposite to each other, the first coil portion and the second coil portion of the eddy current detection excitation coil are respectively wound on the two bottom supporting feet, and the first coil portion and the second coil portion are connected in series.

[0011] In one embodiment of the present application, optionally, for each of the multiple signal processing circuits, the input end of the signal processing circuit is connected to the corresponding tunneling effect magnetoresistive sensor via a Wheatstone half bridge, and the output end of the signal processing circuit is connected to the data acquisition module; the signal processing circuit includes a differential amplifier circuit and a filter amplifier circuit connected in series, and the first magnetic signal and the second magnetic signal each enter the signal processing circuit and are sequentially amplified by the differential amplifier circuit and the filter amplifier circuit before entering the data acquisition module.

[0012] In one embodiment of the present application, optionally, the data acquisition module includes a first analog-to-digital conversion chip and a second analog-to-digital conversion chip, and the multiple signal processing circuits include a first group of signal processing circuits and a second group of signal processing circuits, and the multiple signal processing circuits in the first group of signal processing circuits are respectively connected to the multiple data acquisition channels provided by the first analog-to-digital conversion chip, and the multiple signal processing circuits in the second group of signal processing circuits are respectively connected to the multiple data acquisition channels provided by the second analog-to-digital conversion chip; the first analog-to-digital conversion chip and the second analog-to-digital conversion chip are respectively connected to a power supply module, which obtains an external input reference voltage, and are respectively connected to the FPGA main control module, which obtains an FPGA control signal, and are respectively connected to an external control module, which obtains an external control signal.

[0013] In one embodiment of the present application, optionally, for each analog-to-digital conversion chip in the first analog-to-digital conversion chip and the second analog-to-digital conversion chip, the analog-to-digital conversion chip is respectively connected to the power supply module through a VIN interface, a VCC interface, a VSS interface and a VREF interface to obtain an external input reference voltage provided by each of the VIN interface, the VCC interface, the VSS interface and the VREF interface; the analog-to-digital conversion chip is respectively connected to the FPGA main control module through a CONVSTA / B interface, an RD interface, a CLK interface, a RESET interface, an OS interface, a CS interface and a STBY interface to respectively receive a conversion start signal, a conversion read signal, a clock signal, a reset signal, an oversampling selection signal, a chip selection signal and a standby mode signal from the FPGA main control module; the analog-to-digital conversion chip is respectively connected to an external control module through a RANGE interface and a PSB_SEL interface, the RANGE interface is used to obtain signal acquisition range setting information, and the PSB_SEL interface is used to obtain power selection instructions for the VIN interface, the VCC interface, the VSS interface and the VREF interface.

[0014] In one embodiment of the present application, optionally, both the first analog-to-digital conversion chip and the second analog-to-digital conversion chip are AD7606 chips, and the sampling rate of the AD7606 chip is 200kSPS.

[0015] In one embodiment of the present application, optionally, the system also includes: an offline synchronous dynamic random access memory, connected to the power supply module and the FPGA main control module, configured to collect data of the data acquisition module provided by the FPGA main control module, and upload the collected data to the computer via the FPGA main control module.

[0016] In one embodiment of the present application, optionally, the offline synchronous dynamic random access memory is configured to receive a clock signal, a clock enable signal, a chip select signal, an on-chip enable signal, a reset signal and a command input signal from the FPGA master control module via an input command interface; the offline synchronous dynamic random access memory is also configured to receive address input signals A[9:0], A11 and A13 from the FPGA master control module via an address input interface, and receive address input signals A[9:0], A11 and A13 from the FPGA master control module via an A10 interface, an A12 interface, a BA[2:0] interface, a DM interface, a TDQS / TDQ The S# interface, DQS / DQS# interface and DQ[15:0] interface respectively receive the automatic complement bit signal, burst mode execution signal, bank address input signal, input mask signal, data selection signal, read / write output signal and data input and output signal from the FPGA main control module; the offline synchronous dynamic random access memory is also configured to be connected to the power supply module via the VCC interface, VSS interface, VREF interface and VQ interface respectively, and to the external control module via the ZQ interface to receive the output drive external reference signal of the external control module.

[0017] In one embodiment of the present application, optionally, the FPGA main control module includes: a UART serial port receiving module, configured to receive a detection instruction from the computer, and send a completion signal of receiving the detection instruction to a data verification module; a data verification module, configured to detect whether the instruction data in the detection instruction is correct in response to the completion signal, and if correct, encapsulate the instruction data into a recognizable format for an analog-to-digital conversion chip driver module; a data conversion module, configured to convert the instruction data in the recognizable format into control data, and output the control data to the analog-to-digital conversion chip driver module; the analog-to-digital conversion chip driver module, configured to drive the data acquisition module to acquire the first magnetic signal and the second magnetic signal, and convert the first magnetic signal and the second magnetic signal into analog signals, and send the analog signals to a data processing module; the data processing module is configured to process the analog signals, and send the processing results to a FIFO interface conversion module; the FIFO interface conversion module The block is configured to convert the FIFO interface into the AXI interface of the memory IP core; the DDR3 interface conversion module is configured to perform the interface conversion between the FIFO interface conversion module and the offline synchronous dynamic random access memory; the FIFO write module is configured to store the processing result in the offline synchronous dynamic random access memory through the FIFO interface conversion module via the DDR3 interface conversion module; the FIFO read module is configured to read the processing result through the FIFO interface conversion module and send the read content to the UART serial port sending module; the UART serial port sending module is configured to feed back the read content to the computer; the general control module is configured to control the UART serial port receiving module, the data verification module, the data conversion module and the analog-to-digital conversion chip driving module to perform corresponding functions, and is connected to the leakage magnetic detection excitation coil and the eddy current detection excitation coil to control the power-on state of the leakage magnetic detection excitation coil and the eddy current detection excitation coil.

[0018] The above technical scheme aims to solve the technical problem that eddy current detection and magnetic flux leakage detection in related technologies are insufficient in detecting buried defects in ferromagnetic metal materials. The defect detection system provided in the embodiment of the present application combines eddy current detection and magnetic flux leakage detection methods, adopts a highly sensitive TMR sensor array and an efficient FPGA data processing system, and significantly improves the detection capability, spatial resolution and detection speed of buried defects in ferromagnetic metal materials, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a defect detection system for ferromagnetic metal devices according to an embodiment of the present application is shown; Figure 2 A physical diagram of a tunneling magnetoresistive sensor array according to an embodiment of the present application is shown; Figure 3 A schematic diagram showing the dimensions of a defect detection probe according to an embodiment of the present application is shown; Figure 4 A signal transmission block diagram of a defect detection system for ferromagnetic metal devices according to an embodiment of the present application is shown; Figure 5 A schematic diagram of a defect detection system for ferromagnetic metal devices according to another embodiment of the present application is shown; Figure 6 A schematic diagram of a signal processing circuit according to an embodiment of the present application is shown; Figure 7 Schematic diagrams showing carbon steel sample a and carbon steel sample b; Figure 8 A physical drawing schematic diagram of carbon steel sample a is shown; Fig. 9 A physical drawing schematic diagram of carbon steel sample b is shown; Fig.10 A physical diagram of a defect detection system for ferromagnetic metal devices according to an embodiment of the present application is shown; Fig.11 and Fig.12 The magnetic flux leakage test results and eddy current test results of carbon steel sample a are shown respectively; Fig.13 The magnetic flux leakage test results and eddy current test results of carbon steel sample b are shown; Fig.14 The magnetic flux leakage detection result and eddy current detection result of carbon steel sample a after threshold segmentation image processing are shown; Fig.15 The magnetic flux leakage detection results and eddy current detection results of the carbon steel sample b after threshold segmentation image processing are shown. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figure 1 A schematic diagram of a defect detection system for ferromagnetic metal devices according to an embodiment of the present application is shown.

[0023] like Figure 1 As shown, according to an embodiment of the present application, a defect detection system 100 for ferromagnetic metal devices significantly improves the detection capability of buried defects in ferromagnetic metal materials by combining eddy current detection and magnetic flux leakage detection and adopting a high-sensitivity tunneling magnetoresistance sensor (TMR) array.

[0024] Specifically, the defect detection system for ferromagnetic metal devices includes: a defect detection probe 12 , a plurality of signal processing circuits 14 , a data acquisition module 16 and an FPGA main control module 18 .

[0025] The defect detection probe 12 includes a magnetic flux leakage detection excitation coil 122 , an eddy current detection excitation coil 124 , a C-shaped magnetic core 126 , a printed circuit board 128 , an insulating shell 1210 and a tunneling effect magnetoresistive sensor array 1212 .

[0026] The magnetic flux leakage detection excitation coil 122 is wound around the C-shaped magnetic core 126 and is configured to apply a first magnetic field to the ferromagnetic metal device 200 to be tested via the C-shaped magnetic core 126 when it is powered on. The eddy current detection excitation coil 124 is wound around the insulating shell 1210 and is configured to apply a second magnetic field to the ferromagnetic metal device 200 to be tested when it is powered on.

[0027] The eddy current testing method detects defects by inducing the secondary magnetic field generated by eddy currents. The direction of the eddy currents is as follows: Figure 1 The magnetic flux leakage detection method detects magnetic flux leakage to identify defects. The magnetic flux leakage detection magnetic lines are as follows: Figure 1 It is shown that the combination of the two methods enables the system to detect defects in ferromagnetic materials more comprehensively, especially the detection capability of buried defects is significantly enhanced.

[0028] The eddy current testing method can increase the penetration depth of eddy current in ferromagnetic materials under low frequency excitation, while the magnetic flux leakage testing method can effectively detect surface and near-surface defects. The combination of the two enables the system to cover a wider range of defect types and depths.

[0029] The tunneling magnetoresistive sensor array 1212 includes a plurality of tunneling magnetoresistive sensors fixed on the printed circuit board 128 , and each tunneling magnetoresistive sensor is configured to collect a first magnetic signal under the action of a first magnetic field and collect a second magnetic signal under the action of a second magnetic field.

[0030] Alternatively, if Figure 2 As shown, a plurality of tunneling effect magnetoresistive sensors are arranged in a single row, and the directions of the sensitive axes are parallel to each other. The first end of each tunneling effect magnetoresistive sensor is grounded, and the second end of each tunneling effect magnetoresistive sensor is connected to the corresponding signal processing circuit 14 .

[0031] Optionally, the size of each tunneling magnetoresistive sensor is 0.45 mm 0.45mm, the center distance between adjacent sensors is 1mm.

[0032] The system uses a customized tunneling magnetoresistive sensor (TMR) array, with each sensor measuring only 0.45mm 0.45mm, and the sensitive axes are parallel to each other. This small-size, high-density sensor array significantly improves the spatial resolution of the system, and can more accurately locate and identify tiny defects. At the same time, the TMR sensor has high sensitivity in a wide frequency range (DC to 100kHz), and its sensitivity does not decrease with the decrease of the excitation frequency, overcoming the problem of the sensitivity decrease of traditional induction coil sensors under low-frequency excitation, thereby improving the signal-to-noise ratio and detection accuracy of the system.

[0033] Optionally, the number of the plurality of tunneling effect magnetoresistive sensors is 15. Figure 1 , Figure 2 The multiple tunneling effect magnetoresistive sensors are only exemplarily shown in the text. At the same time, any numerical value in the context is only an embodiment of the present application. In specific scenarios, these numerical values ​​can be set based on actual scenario requirements and are not limited to the examples given in the text.

[0034] Furthermore, combined with Figure 1 and Figure 3 As shown, the C-shaped magnetic core 126 includes a first portion 1261, a second portion 1262 parallel to the first portion 1261, and a middle portion 1263 connecting the first portion 1261 and the second portion 1262. Figure 1As shown, the first part 1261, the second part 1262, and the middle part 1263 are surrounded to form a C-shaped structure, and the leakage magnetic detection excitation coil 122 is wound around the middle part 1263; the insulating shell 1210 has a bottom supporting foot 12102, and the eddy current detection excitation coil 124 is wound on the bottom supporting foot 12102; the printed circuit board 128 is embedded in the recess surrounded by the first part 1261, the second part 1262 and the middle part 1263, the insulating shell 1210 is embedded in the recess and wraps the printed circuit board 128, and the first part 1261 and the second part 1262 are each on the same side of the bottom supporting foot 12102 with one end away from the middle part 1263; the direction of the magnetic field lines of the C-shaped magnetic core 126 in the ferromagnetic metal device 200 to be tested is from the first part 1261 to the second part 1262, which is perpendicular to the sensitive axis direction of each tunneling effect magnetoresistive sensor.

[0035] Optionally, the insulating shell 1210 has two bottom support legs 12102, the two bottom support legs 12102 are arranged opposite to each other, the first coil portion and the second coil portion of the eddy current detection excitation coil 124 are respectively wound on the two bottom support legs 12102, and the first coil portion and the second coil portion are connected in series. Eddy currents can be generated by energizing the two coil portions connected in series, and the eddy currents cover the detection area of ​​the ferromagnetic metal device to be tested, thereby realizing eddy current detection.

[0036] Reference Figure 3 For example, the leakage magnetic detection excitation coil 122 is made of 125 turns of enameled copper wire with a wire diameter of 0.3 mm, and has a width of 40 mm. The length of the middle part 1263 is 80 mm and the width is 40 mm. The height of the first part 1261 and the second part 1262 are both 80 mm, the width is 40 mm, and the length is 30 mm. The metal material of the C-shaped magnetic core 126 is ferrite.

[0037] The C-shaped magnetic core 126 is composed of a first portion 1261, a second portion 1262 and a middle portion 1263, and the magnetic flux leakage detection excitation coil 122 is wound around the middle portion 1263. This structural design enables the magnetic field to be evenly distributed at both ends of the C-shaped magnetic core 126 (i.e., the first portion 1261 and the second portion 1262), thereby generating a uniform magnetic field line distribution in the ferromagnetic metal device 200 to be tested. The direction of the magnetic field line points from the first portion 1261 to the second portion 1262, ensuring that the magnetic field of the magnetic flux leakage detection can effectively penetrate the material to be tested, thereby enhancing the ability to detect defects.

[0038] The direction of the magnetic lines of force is perpendicular to the sensitive axis of the tunneling magnetoresistive sensor (TMR), which avoids the saturation problem of the sensor caused by the consistency of the magnetic field direction with the sensitive axis direction, and ensures that the sensor can stably and accurately collect magnetic field signals.

[0039] The printed circuit board 128 is embedded in the recessed position surrounded by the first part 1261, the second part 1262 and the middle part 1263 of the C-shaped magnetic core 126, and the insulating shell 1210 wraps the printed circuit board 128 and is embedded in the recessed position. This compact design not only saves space, but also improves the structural stability of the probe, ensures that the relative positions of the components remain unchanged during the detection process, and reduces the measurement error caused by mechanical vibration or external interference.

[0040] The bottom support foot 12102 of the insulating shell 1210 is wound with an eddy current detection excitation coil 124. This design enables the excitation magnetic field of the eddy current detection to directly act on the surface of the material to be tested, thereby improving the sensitivity and accuracy of the eddy current detection.

[0041] The magnetic flux leakage detection excitation coil 122 is wound around the middle portion 1263 of the C-shaped magnetic core 126, and can generate a strong magnetic field in the material to be tested, so that the material reaches a magnetic saturation state, thereby effectively detecting magnetic flux leakage caused by defects.

[0042] The eddy current detection excitation coil 124 is wound around the bottom support leg 12102 of the insulating shell 1210, which can generate induced eddy currents in the material to be tested, and then collect the secondary magnetic field signal generated by the eddy currents through the TMR sensor. This design allows eddy current detection and magnetic flux leakage detection to be performed simultaneously, improving detection efficiency.

[0043] The insulating shell 1210 not only fixes and protects the printed circuit board 128, but also provides stable support for the eddy current detection excitation coil 124 through the bottom support feet 12102. This design enhances the mechanical stability of the probe, enabling it to work stably for a long time in a complex industrial environment.

[0044] The first part 1261 and the second part 1262 of the C-shaped magnetic core 126 are on the same side as the bottom support foot 12102, ensuring that the probe can maintain balance during the detection process and reducing measurement errors caused by probe tilt or vibration.

[0045] By embedding the printed circuit board 128 into the recess of the C-shaped magnetic core 126 and wrapping the printed circuit board 128 with the insulating shell 1210, the relative position between the sensor array and the excitation coil is ensured to be fixed, thereby reducing the measurement error caused by mechanical displacement.

[0046] The sensitive axis direction of the TMR sensor is perpendicular to the magnetic field line direction of the C-shaped magnetic core 126, which avoids the sensor saturation problem, ensures that the sensor can stably and accurately collect magnetic field signals, and improves the detection accuracy and reliability.

[0047] In summary, the structural design described in this paragraph significantly improves the detection accuracy, reliability and applicability of the ferromagnetic metal device defect detection system by optimizing the magnetic field distribution, compact probe layout, efficient magnetic field excitation and signal acquisition, and enhanced mechanical stability and durability.

[0048] The plurality of signal processing circuits 14 are respectively connected to the plurality of tunneling effect magnetoresistive sensors, and each signal processing circuit 14 is configured to receive the first magnetic signal and the second magnetic signal from the connected tunneling effect magnetoresistive sensor. Figure 1 The number of tunneling effect magnetoresistive sensors and the number of signal processing circuits are only given as examples. Optionally, the tunneling effect magnetoresistive sensor array 1212 may be configured to include 15 tunneling effect magnetoresistive sensors, and a dedicated signal processing circuit may be connected to each tunneling effect magnetoresistive sensor, that is, 15 signal processing circuits may be configured to serve as exclusive data processing and transmission channels for the 15 tunneling effect magnetoresistive sensors.

[0049] The input end of each signal processing circuit 14 is connected to the corresponding tunneling magnetoresistive sensor via a Wheatstone half bridge, and the output end of the signal processing circuit 14 is connected to the data acquisition module 16; the signal processing circuit 14 includes a differential amplifier circuit and a filter amplifier circuit connected in series, and the first magnetic signal and the second magnetic signal enter the signal processing circuit 14 respectively, and are amplified by the differential amplifier circuit and the filter amplifier circuit in sequence, and then enter the data acquisition module 16. In this way, the system is equipped with multiple signal processing circuits 14, each of which is connected to the TMR sensor via a Wheatstone half bridge, which can effectively amplify and filter the magnetic signal from the sensor and eliminate the system error caused by the difference in sensor units.

[0050] The data acquisition module 16 is connected to the plurality of signal processing circuits 14 and is configured to acquire the first magnetic signal and the second magnetic signal received by each signal processing circuit 14 .

[0051] The FPGA main control module 18 is connected to the data acquisition module 16 and the external computer 300, and is configured to drive the data acquisition module 16 to obtain the first magnetic signal and the second magnetic signal received by each signal processing circuit 14 in response to the detection instruction from the computer 300, and to determine the leakage magnetic detection result and the eddy current detection result respectively based on the first magnetic signal and the second magnetic signal received by all the signal processing circuits 14, and is also configured to feed back the leakage magnetic detection result and the eddy current detection result to the computer 300.

[0052] Alternatively, if Figure 4 As shown, the data acquisition module 16 uses two AD7606 analog-to-digital conversion chips, which can quickly and accurately collect signals from multiple sensors.

[0053] The FPGA main control module 18 processes multiple signals in real time through parallel computing capabilities, significantly improving the detection speed and data processing efficiency of the system. The FPGA main control module 18 is not only responsible for driving the data acquisition module 16, but also can respond to the detection instructions of the external computer 300, adjust the detection parameters (such as excitation frequency, sampling rate, etc.) in real time, and feed back the detection results to the computer 300 for further analysis and processing. The system is also equipped with an offline synchronous dynamic random access memory (SDRAM) for storing the collected data to ensure the integrity and reliability of the data during the detection process.

[0054] In summary, the defect detection system provided in the embodiment of the present application combines eddy current detection and magnetic flux leakage detection methods, adopts a high-sensitivity TMR sensor array and an efficient FPGA data processing system, and significantly improves the detection capability, spatial resolution and detection speed of buried defects in ferromagnetic metal materials, and has broad application prospects.

[0055] In one possible design, the data acquisition module 16 includes a first analog-to-digital conversion chip 162 and a second analog-to-digital conversion chip 164, and the multiple signal processing circuits 14 include a first group of signal processing circuits 14 and a second group of signal processing circuits 14. The multiple signal processing circuits 14 in the first group of signal processing circuits 14 are respectively connected to the multiple data acquisition channels provided by the first analog-to-digital conversion chip 162, and the multiple signal processing circuits 14 in the second group of signal processing circuits 14 are respectively connected to the multiple data acquisition channels provided by the second analog-to-digital conversion chip 164; the first analog-to-digital conversion chip 162 and the second analog-to-digital conversion chip 164 are respectively connected to a power supply module, which obtains an external input reference voltage, and are respectively connected to the FPGA main control module 18, which obtains FPGA control signals, and are respectively connected to an external control module, which obtains external control signals.

[0056] Optionally, the number of signal processing circuits in the first group of signal processing circuits 14 is 8, and the 8 signal processing circuits are connected to the 8 input interfaces of the first analog-to-digital conversion chip 162, and the number of signal processing circuits in the second group of signal processing circuits 14 is 7, and the 7 signal processing circuits are connected to the 7 input interfaces of the second analog-to-digital conversion chip 164. Of course, this connection method is only an exemplary connection structure of the embodiment in which 15 tunneling effect magnetoresistive sensors are provided, and the number of analog-to-digital conversion chips and the number of input interfaces provided by each analog-to-digital conversion chip can be set based on actual needs, and is not limited to the above example.

[0057] Optionally, the first analog-to-digital conversion chip 162 and the second analog-to-digital conversion chip 164 are both AD7606 chips, and the sampling rate of the AD7606 chip is 200 kSPS.

[0058] Combination Figure 4 As shown, for each analog-to-digital conversion chip in the first analog-to-digital conversion chip 162 and the second analog-to-digital conversion chip 164, the analog-to-digital conversion chip is respectively connected to the power supply module through the VIN interface, the VCC interface, the VSS interface and the VREF interface to obtain the external input reference voltage provided by the VIN interface, the VCC interface, the VSS interface and the VREF interface respectively; the analog-to-digital conversion chip is respectively connected to the FPGA main control module 18 through the CONVSTA / B interface, the RD interface, the CLK interface, the RESET interface, the OS interface, the CS interface and the STBY interface to respectively receive the conversion start signal, the conversion read signal, the clock signal, the reset signal, the oversampling selection signal, the chip selection signal and the standby mode signal from the FPGA main control module 18; the analog-to-digital conversion chip is respectively connected to the external control module through the RANGE interface and the PSB_SEL interface, the RANGE interface is used to obtain the signal acquisition range setting information, and the PSB_SEL interface is used to obtain the power selection instruction for the VIN interface, the VCC interface, the VSS interface and the VREF interface.

[0059] In addition, the system also includes an offline synchronous dynamic random access memory (SDRAM), which is connected to the power supply module and the FPGA main control module 18, and is configured to collect data of the data collection module 16 provided by the FPGA main control module 18, and upload the collected data to the computer 300 via the FPGA main control module 18. Optionally, the SDRAM is a DDR3 chip MT41K128M16JT.

[0060] The signal transmission block diagram between the tunneling magnetoresistive sensor array 1212, the signal processing circuit 14, the data acquisition module 16 controlled by the FPGA main control module 18, and the computer 300 is shown in FIG. Figure 4 As shown. The two analog-to-digital conversion chips used in the system are shown schematically as one chip, the model is AD7606, and the sampling rate of the chip is 200kSPS. The model of the FPGA chip used is XC7A35TFGG484-2 produced by Xilinx.

[0061] The FPGA main control module 18 generates a clock signal for controlling the operation of the AD7606 chip. After receiving the instructions of the FPGA main control module 18, the AD7606 chip starts to collect the probe reception signal processed by the buffer. The output signal of the AD7606 chip is stored in the offline synchronous dynamic random access memory through the FIFO, and is transmitted to the computer 300 under the control of the FPGA main control module 18. As the core controller of the entire acquisition module, the FPGA main control module 18 is responsible for coordinating the cooperation of each module, including receiving and processing the instructions of the computer 300, providing the control and configuration signals of the AD7606 chip, transmitting and storing the data transmitted by the AD7606 chip through the FIFO module, controlling the read and write data flow of DDR3, and performing serial transmission and data processing. During the data acquisition process, the command communication and data processing between the FPGA main control module 18 and the computer 300 are realized through the UART bus.

[0062] like Figure 4 As shown, the offline synchronous dynamic random access memory is configured to receive a clock signal, a clock enable signal, a chip select signal, an on-chip enable signal, a reset signal and a command input signal from the FPGA master control module 18 via an input command interface; the offline synchronous dynamic random access memory is also configured to receive address input signals A[9:0], A11 and A13 from the FPGA master control module 18 via an address input interface, and to receive an automatic complement bit signal, a burst mode execution signal, a bank address input signal, an input mask signal, a data selection signal, a read / write output signal and a data input and output signal from the FPGA master control module 18 via an A1 interface, an A12 interface, a BA[2:0] interface, a DM interface, a TDQS / TDQS# interface, a DQS / DQS# interface and a DQ[15:0] interface respectively; the offline synchronous dynamic random access memory is also configured to be connected to the power supply module via a VCC interface, a VSS interface, a VREF interface and a VQ interface respectively, and to be connected to an external control module via a ZQ interface, and to receive an output drive external reference signal from the external control module.

[0063] The REF_SEL interface is kept at a logic high level, that is, the internal reference voltage is used, and the RANGE interface is connected to a logic low level, at which time the input range is ±5V; the PSB_SEL interface is connected to a logic low level to select the parallel interface. When the CONVSTA signal and the CONVSTB signal rise, the AD7606 chip acquisition signal starts to convert, and the BUSY interface outputs a high level at this time. When the BUSY signal falls, the data conversion is completed and latched into the register. When the chip select signal CS rises, the converted data is transferred to the bus. When the chip select signal CS and the read signal RD are both high, the bus is enabled and data begins to be transmitted through the bus. When the data conversion result of the acquisition channel ADIN1 is output through the bus, FRSTDATA converts to a high level to indicate that the output result is ready.

[0064] The SDRAM used in the system is a DDR3 chip MT41K128M16JT manufactured by Micron. FPGA provides input command signals to DDR3, including clock signal (CK), clock enable signal (CKE), chip select signal (CS), on-chip enable signal (ODT), reset signal (RESET), command input signal (RAS#, CAS#, WE#). Address signals include address input signals (A[9:0], A11, A13), automatic complement bit signal (A1), burst mode execution signal (A12), and bank address input signal (BA[2:0]). Control signals include input mask signal (DM), data selection signal (TDQS / TDQS#), read / write output signal (DQS / DQS#). External input signals include power supply (VCC, VSS), data reference voltage signal (VREF), output drive external reference signal (ZQ), data input and output signals (DQ[15:0] interface). Among them, the power supply voltage VCC is +1.5V, VSS is grounded, VREF is 0.75V, VQ is the isolation voltage, which is 1.5V, and ZQ is the external reference for output driver calibration, connected to a 240Ω resistor and grounded. The clock signal and clock enable signal are provided by the FPGA, and the on-chip enable signal ODT is kept low to match the transmission line impedance.

[0065] In addition, if Figure 5As shown, the FPGA main control module 18 includes: a UART serial port receiving module (UART_receive_byte), a data verification module (UART_cmd), a data conversion module (CTRL_cmd), an analog-to-digital conversion chip driver module (AD7606_driver), a data processing module (DATA_process), a FIFO interface conversion module (FIFO2mig_axi), a DDR3 interface conversion module (MIG_7series), a FIFO write module (write_ddr3_fifo), a FIFO read module (read_ddr3_fifo), a UART serial port sending module (UART_transmit_byte) and a general control module (STATE_ctrl).

[0066] The UART serial port receiving module is configured to receive a detection instruction from the computer 300, and send a completion signal of receiving the detection instruction to the data verification module; the data verification module is configured to detect whether the instruction data in the instruction is correct in response to the completion signal, and if correct, encapsulate the instruction data into a recognizable format for the analog-to-digital conversion chip driver module; the data conversion module is configured to convert the instruction data in the recognizable format into control data, and output the control data to the analog-to-digital conversion chip driver module; the analog-to-digital conversion chip driver module is configured to drive the data acquisition module 16 to collect the first magnetic signal and the second magnetic signal, and convert the first magnetic signal and the second magnetic signal into analog signals, and send the analog signals to the data processing module; the data processing module is configured to process the analog signal and send the processing result to the FIFO interface conversion module; the FIFO interface conversion module is configured to convert the FIFO interface into the AXI interface of the memory IP core; the DDR3 interface The conversion module is configured to perform interface conversion between the FIFO interface conversion module and the offline synchronous dynamic random access memory (SDRAM_DDR3); the FIFO write module is configured to store the processing result in the offline synchronous dynamic random access memory via the DDR3 interface conversion module via the FIFO interface conversion module; the FIFO read module is configured to read the processing result via the FIFO interface conversion module and send the read content to the UART serial port sending module; the UART serial port sending module is configured to feed back the read content to the computer 300; the general control module is configured to control the UART serial port receiving module, the data verification module, the data conversion module and the analog-to-digital conversion chip driving module to perform corresponding functions, and is connected to the leakage magnetic detection excitation coil 122 and the eddy current detection excitation coil 124, and is used to control the power-on state of the leakage magnetic detection excitation coil 122 and the eddy current detection excitation coil 124.

[0067] The FPGA is controlled by the general control module and receives commands from the computer 300 through the UART serial port receiving module. After receiving the data, the module will output a receiving completion signal to the data verification module. The data verification module determines whether the data is correct during execution and encapsulates the data received from the serial port into a format that can be recognized by the analog-to-digital conversion chip driver module. The data conversion module converts the data into corresponding control data and transmits it to the analog-to-digital conversion chip driver module, which receives data from the AD7606 chip, which is the most important data in the eddy current detection and magnetic flux leakage detection signal acquisition system. The analog-to-digital conversion chip driver module collects analog signals from the AD7606 chip and can modify the sampling frequency according to the host computer command. After the signal conversion is completed, the data is transmitted to the data processing module. After data processing, the signal is sent to the FIFO write module, and the FIFO write module completes the data writing. The FIFO interface conversion module is mainly used for interface conversion, that is, converting the FIFO interface into the AXI interface of the memory (MIG) IP core.

[0068] In addition, if Figure 6 As shown, the signal processing circuit 14 of the defect detection probe 12 is as shown in FIG. Figure 6 As shown, S1 to S15 are input signals connected to the FPGA main control module 18. The tunneling magnetoresistive sensor in the defect detection probe 12 receives the magnetic field signal and is connected to the circuit through the Wheatstone half bridge. The output signal of the bridge is differentially amplified by the instrumentation amplifier, filtered and amplified by the operational amplifier, and then output to the FPGA main control module 18.

[0069] Among them, resistors R1-R3 are calibration resistors with a resistance of 8.2kΩ, Rg is the gain setting resistor of the instrument amplifier, C0, C1, R4, and R7 are filter capacitors and resistors, and R5 and R6 are amplification resistors of the input signal connected to the FPGA main control module 18. The upper and lower cutoff frequencies of the filter are 200kHz and 50Hz respectively, and the amplification gain of the circuit is 40dB.

[0070] In actual scenarios, in order to test the ability of the defect detection probe 12 to detect buried defects in ferromagnetic metal devices, the following Figure 7 (a) and Figure 7 The carbon steel sample shown in (b) of the figure, the physical drawings of the two samples are shown in Figure 8 and Fig. 9 .

[0071] Figure 8The carbon steel sample a shown has a thickness of 3 mm, and the defect detection probe 12 scans along the long side from the back of the carbon steel sample a. Groove defects of different depths are artificially etched on the carbon steel sample a, with a length of 5 mm, a width of 1 mm, and a depth of 2.5 mm (#1), 2 mm (#2), 1.5 mm (#3), and 1 mm (#4).

[0072] Fig. 9 The carbon steel plate shown has a thickness of 1 mm. A groove defect (#5) and a flat-bottom hole defect (#6) are artificially etched on the carbon steel sample b, where the dimensions of defect #5 are 2 mm long, 1 mm wide, and 8 mm deep, and the dimensions of defect #6 are 1 mm in diameter, 1 mm long, and 8 mm deep.

[0073] When testing the two samples, the lifting distance between the defect detection probe 12 and the sample is about 0.5 mm. The amplitude of the excitation voltage used in eddy current testing is 12V, the frequency of the excitation voltage is 75Hz, and the current in the leakage magnetic detection excitation coil 122 is 0.5A, and the frequency is 10Hz.

[0074] A physical diagram of a defect detection system for ferromagnetic metal devices according to an embodiment of the present application is shown in FIG. Figure 1 As shown, a DC power supply supplies power to each part, a computer 300 serves as a host computer to control the FPGA control circuit, the FPGA control circuit controls the signal processing circuit 14, the signal processing circuit 14 is connected to a detection probe, and the detection probe is used to detect ferromagnetic material samples.

[0075] The data acquisition module 16 receives eddy current detection signals and magnetic flux leakage detection signals from the tunneling effect magnetoresistive sensor array 1212. The excitation signals used in eddy current detection and magnetic flux leakage detection have different frequencies, which can be separated by a digital phase-locked amplifier in the system.

[0076] The results of the magnetic flux leakage detection experiment using the defect detection probe 12 to detect buried defects in a 3mm thick carbon steel plate are shown in the figure. Fig.11 As shown in Figure 1, the probe can detect defects #1 and #2 on the carbon steel plate. The eddy current testing test results of the probe detecting buried defects in a 3mm thick carbon steel plate are shown in Figure 1. Fig.12 As shown, the experimental results show that the probe can detect defects with a buried depth of 2 mm in a carbon steel sample with a thickness of 3 mm.

[0077] The results of eddy current detection and magnetic flux leakage detection experiments on buried defects in carbon steel plates with a thickness of 1 mm using defect detection probe 12 are shown in the figure. Fig.13 The test results show that the defect detection probe 12 can detect defect #5 and defect #6. The experimental results verify the feasibility of the defect detection probe 12 and the data acquisition system. The test results of magnetic flux leakage detection can supplement the results of eddy current detection in practical applications.

[0078] The experimental results in the embodiment are subjected to threshold segmentation image processing, and the images of the magnetic flux leakage detection results and eddy current detection results of the carbon steel sample a after the processing are as follows: Fig.14 As shown in the figure, the images of the magnetic flux leakage test results and eddy current test results of the treated carbon steel sample b are as follows Fig.15 As shown, the result after image processing shows that the indication of defects in the processed image is more obvious than that in the original image.

[0079] The above technical solution of the present application is described in detail in combination with the accompanying drawings. Through the technical solution of the present application, by combining eddy current detection and magnetic flux leakage detection methods, adopting a high-sensitivity TMR sensor array and an efficient FPGA data processing system, the detection capability, spatial resolution and detection speed of buried defects in ferromagnetic metal materials are significantly improved, and it has broad application prospects.

[0080] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0081] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0082] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0083] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A defect detection system for ferromagnetic metal devices, characterized in that: include: The defect detection probe includes a magnetic flux leakage detection excitation coil, an eddy current detection excitation coil, a C-shaped magnetic core, a printed circuit board, an insulating shell and a tunneling effect magnetoresistive sensor array. The magnetic flux leakage detection excitation coil is wound around the C-shaped magnetic core and is configured to apply a first magnetic field to the ferromagnetic metal device to be tested through the C-shaped magnetic core when it is powered on. The eddy current detection excitation coil is wound around the insulating shell and is configured to apply a second magnetic field to the ferromagnetic metal device to be tested when it is powered on. The tunneling effect magnetoresistive sensor array includes a plurality of tunneling effect magnetoresistive sensors fixed on the printed circuit board, each of the tunneling effect magnetoresistive sensors being configured to collect a first magnetic signal under the action of the first magnetic field and to collect a second magnetic signal under the action of the second magnetic field; a plurality of signal processing circuits, connected to the plurality of tunneling magnetoresistive sensors respectively, each of the signal processing circuits being configured to receive the first magnetic signal and the second magnetic signal from the connected tunneling magnetoresistive sensor; a data acquisition module, connected to the plurality of signal processing circuits, and configured to acquire the first magnetic signal and the second magnetic signal received by each of the signal processing circuits; The FPGA main control module is connected to the data acquisition module and an external computer, and is configured to drive the data acquisition module to acquire the first magnetic signal and the second magnetic signal received by each of the signal processing circuits in response to a detection instruction from the computer, and to respectively determine a magnetic leakage detection result and an eddy current detection result based on the first magnetic signal and the second magnetic signal received by all of the signal processing circuits, and is also configured to feed back the magnetic leakage detection result and the eddy current detection result to the computer.

2. The system according to claim 1, characterized in that The plurality of tunneling effect magnetoresistive sensors are arranged in a single row with their sensitive axes parallel to each other. The first end of each tunneling effect magnetoresistive sensor is grounded, and the second end of each tunneling effect magnetoresistive sensor is connected to the corresponding signal processing circuit.

3. The system according to claim 1, characterized in that The C-shaped magnetic core comprises a first portion, a second portion parallel to the first portion, and a middle portion connecting the first portion and the second portion, the first portion, the second portion, and the middle portion are surrounded to form a C-shaped structure, and the leakage magnetic detection excitation coil is wound around the middle portion; The insulating shell has a bottom supporting foot, and the eddy current detection excitation coil is wound around the bottom supporting foot; The printed circuit board is embedded in a recess formed by the first part, the second part and the middle part, the insulating shell is embedded in the recess and wraps the printed circuit board, and one end of each of the first part and the second part away from the middle part is on the same side as the bottom supporting foot; The direction of the magnetic lines of force of the C-shaped magnetic core in the ferromagnetic metal device to be tested is from the first part to the second part, which is perpendicular to the sensitive axis direction of each of the tunneling effect magnetoresistive sensors.

4. The system according to claim 3, characterized in that The insulating shell has two bottom supporting feet, which are arranged opposite to each other. The first coil part and the second coil part of the eddy current detection excitation coil are respectively wound around the two bottom supporting feet, and the first coil part and the second coil part are connected in series.

5. The system according to any one of claims 1 to 4, characterized in that For each of the plurality of signal processing circuits, The input end of the signal processing circuit is connected to the corresponding tunneling magnetoresistive sensor via a Wheatstone half bridge, and the output end of the signal processing circuit is connected to the data acquisition module; The signal processing circuit includes a differential amplifier circuit and a filter amplifier circuit connected in series. After the first magnetic signal and the second magnetic signal enter the signal processing circuit respectively, they are amplified by the differential amplifier circuit and the filter amplifier circuit in sequence and then enter the data acquisition module.

6. The system according to claim 5, characterized in that The data acquisition module includes a first analog-to-digital conversion chip and a second analog-to-digital conversion chip. The plurality of signal processing circuits include a first group of signal processing circuits and a second group of signal processing circuits, wherein the plurality of signal processing circuits in the first group of signal processing circuits are respectively connected to the plurality of data acquisition channels provided by the first analog-to-digital conversion chip, and the plurality of signal processing circuits in the second group of signal processing circuits are respectively connected to the plurality of data acquisition channels provided by the second analog-to-digital conversion chip; The first analog-to-digital conversion chip and the second analog-to-digital conversion chip are respectively connected to a power supply module, which obtains an external input reference voltage, and are respectively connected to the FPGA main control module, which obtains an FPGA control signal, and are respectively connected to an external control module, which obtains an external control signal.

7. The system according to claim 6, characterized in that For each of the first analog-to-digital conversion chip and the second analog-to-digital conversion chip, The analog-to-digital conversion chip is respectively connected to the power supply module through the VIN interface, the VCC interface, the VSS interface and the VREF interface to obtain the external input reference voltage provided by the VIN interface, the VCC interface, the VSS interface and the VREF interface respectively; The analog-to-digital conversion chip is respectively connected to the FPGA main control module through the CONVSTA / B interface, the RD interface, the CLK interface, the RESET interface, the OS interface, the CS interface and the STBY interface to respectively receive a conversion start signal, a conversion read signal, a clock signal, a reset signal, an oversampling selection signal, a chip selection signal and a standby mode signal from the FPGA main control module; The analog-to-digital conversion chip is connected to an external control module via a RANGE interface and a PSB_SEL interface, respectively. The RANGE interface is used to obtain signal acquisition range setting information, and the PSB_SEL interface is used to obtain power selection instructions for the VIN interface, the VCC interface, the VSS interface, and the VREF interface.

8. The system according to claim 6, characterized in that Also includes: The offline synchronous dynamic random access memory is connected to the power supply module and the FPGA main control module, and is configured to collect the data of the data acquisition module provided by the FPGA main control module, and upload the collected data to the computer via the FPGA main control module.

9. The system according to claim 8, characterized in that The offline synchronous dynamic random access memory is configured to receive a clock signal, a clock enable signal, a chip select signal, an on-chip enable signal, a reset signal and a command input signal from the FPGA master control module via an input command interface; The offline synchronous dynamic random access memory is also configured to receive address input signals A[9:0], A11 and A13 from the FPGA master control module via the address input interface, and to receive automatic complement bit signals, burst mode execution signals, bank address input signals, input mask signals, data selection signals, read / write output signals and data input and output signals from the FPGA master control module via the A10 interface, the A12 interface, the BA[2:0] interface, the DM interface, the TDQS / TDQS# interface, the DQS / DQS# interface and the DQ[15:0] interface, respectively; The offline synchronous dynamic random access memory is also configured to be connected to the power supply module via the VCC interface, the VSS interface, the VREF interface, and the VQ interface respectively, and to be connected to the external control module via the ZQ interface to receive the output drive external reference signal of the external control module.

10. The system according to claim 8, characterized in that The FPGA master control module includes: A UART serial port receiving module is configured to receive a detection instruction from the computer and send a completion signal of receiving the detection instruction to the data verification module; a data verification module, configured to detect whether the instruction data in the detection instruction is correct in response to the completion signal, and if correct, encapsulate the instruction data into a recognizable format for the analog-to-digital conversion chip driver module; A data conversion module, configured to convert the instruction data in the recognizable format into control data, and output the control data to the analog-to-digital conversion chip driving module; The analog-to-digital conversion chip driving module is configured to drive the data acquisition module to acquire the first magnetic signal and the second magnetic signal, convert the first magnetic signal and the second magnetic signal into analog signals, and send the analog signals to the data processing module; A data processing module is configured to process the analog signal and send the processing result to the FIFO interface conversion module; A FIFO interface conversion module, configured to convert the FIFO interface into an AXI interface of the memory IP core; A DDR3 interface conversion module, configured to perform interface conversion between the FIFO interface conversion module and the offline synchronous dynamic random access memory; A FIFO writing module is configured to store the processing result into the offline synchronous dynamic random access memory via the FIFO interface conversion module and the DDR3 interface conversion module; A FIFO reading module is configured to read the processing result through the FIFO interface conversion module and send the read content to the UART serial port sending module; A UART serial port sending module is configured to feed back the read content to the computer; The universal control module is configured to control the UART serial port receiving module, the data verification module, the data conversion module and the analog-to-digital conversion chip driver module to perform corresponding functions, and is connected to the leakage magnetic detection excitation coil and the eddy current detection excitation coil to control the power-on state of the leakage magnetic detection excitation coil and the eddy current detection excitation coil.

Images