Ethernet synchronous communication method and device based on FPGA and dynamic phase shift

Abstract

The invention discloses an Ethernet synchronous communication method and device based on an FPGA (Field Programmable Gate Array) and dynamic phase shift. Data to be transmitted, which is received by a sending end, is subjected to subpackage processing, a plurality of data packets are compressed and packaged, a dynamic phase shift algorithm is controlled by the FPGA, a clock signal of each packaged data packet is subjected to phase encoding, and a clock synchronous frame is generated. And the signals are transmitted to a receiving end in parallel through a multi-channel Ethernet. And the receiving end carries out phase error estimation according to the synchronization header information of each coded data packet, and carries out dynamic phase compensation on the clock signals of the coded data packets according to an estimation result. And based on the synchronization header information after dynamic phase compensation, analyzing and recombining the plurality of coded data packets, and recovering the coded data packets into the original transmission data. According to the method, synchronization delay possibly occurring in high-speed data transmission is reduced through dynamic phase compensation, network communication resources are reasonably distributed and utilized through multi-channel parallel transmission, and resource waste and occupation of a large number of resources are effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet communication, and in particular to an Ethernet synchronous communication method and device based on FPGA and dynamic phase shift. Background Art

[0002] As a widely used local area network technology, Ethernet occupies a vital position in the field of modern communications. With the rapid development of information technology, the application scenarios of Ethernet have been continuously expanded, covering many fields such as data centers, industrial automation, intelligent transportation, aerospace, etc. In these application scenarios, higher and higher requirements are placed on the speed, reliability and synchronization of Ethernet communication. For example, in data centers, high-speed and stable data transmission is required between a large number of servers to achieve efficient cloud computing and big data processing; in industrial automation production lines, precise synchronous communication between devices is crucial to ensure the stability of the production process and product quality.

[0003] Traditional Ethernet synchronization technologies are mainly based on time stamp protocols (such as NTP and PTP) to achieve clock synchronization. However, these technologies have certain limitations in some cases. On the one hand, the time stamp protocol relies on the time server in the network. When the network is congested, delayed or faulty, the accuracy of clock synchronization will be affected. On the other hand, as the Ethernet communication rate continues to increase, traditional synchronization technology may increase synchronization delay when processing high-speed data transmission, which is not suitable for some application scenarios with extremely high synchronization accuracy requirements.

[0004] At the same time, the resources for network communication are limited. However, in the face of the current situation of high-speed transmission of massive amounts of data, it is difficult to reasonably allocate and utilize network communication resources, which easily leads to waste of resources and large-scale resource occupation. Summary of the invention

[0005] In view of this, the present invention provides an Ethernet synchronous communication method and device based on FPGA and dynamic phase shift, which solves the technical problems that traditional synchronization technology may have increased synchronization delay when processing high-speed data transmission, and it is difficult to reasonably allocate and utilize network communication resources, which easily causes resource waste and large-scale resource occupation.

[0006] A first aspect of the present invention provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, comprising: The data to be transmitted received by the sending end is divided into packets to obtain multiple data packets; Compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; the encapsulated data packets include synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; Phase encoding is performed on the clock signal of each encapsulated data packet by controlling a dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain multiple encoded data packets; Transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The receiving end parses and reassembles a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restores the coded data to the originally transmitted data.

[0007] Preferably, compressing the plurality of data packets and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets comprises: Clustering the plurality of data packets to obtain a plurality of clusters; each of the clusters includes a cluster center data packet and other data packets except the cluster center data packet; Constructing a feature hyperplane according to the cluster center data packets, and projecting other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain an orthogonal projection matrix of the other data packets; Performing topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix; Preprocessing other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of the other data packets; Performing a projection compression operation on the matrix of the other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet; Each of the cluster center data packets and compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet are encapsulated to obtain a plurality of encapsulated data packets.

[0008] Preferably, the method further comprises: Packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet; The key-value mapping data packet is transmitted to the virtual container of the target device to obtain a container image, and the container image is used to respond to the request information of the receiving end and forward the key-value mapping data packet corresponding to the key specified in the request information to the receiving end.

[0009] Preferably, the clock signal of each encapsulated data packet is phase-encoded by controlling a dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain a plurality of encoded data packets, including: For each of the encapsulated data packets, extracting data feature information of the encapsulated data packet; According to the data feature information, a clock signal of the encapsulated data packet is multi-dimensionally phase-space encoded by controlling a dynamic phase shift algorithm through an FPGA to obtain a four-dimensional phase encoding matrix; wherein the dimensions of the four-dimensional phase encoding matrix include a phase, an accumulated phase adjustment amount, a phase weighted average amount, and a phase temperature drift amount; Performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain the clock synchronization frame; The clock synchronization frame is embedded in the synchronization header information, and during the embedding process, a phase synchronization header is inserted into the synchronization header information to obtain the encoded data packet; wherein the phase synchronization header is used to predict the phase of the next encoded data packet.

[0010] Preferably, the transmitting of the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet comprises: For each of the encoded data packets, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features; For each channel in the Ethernet, extract the multidimensional channel features of the channel, and construct a channel tensor of the channel according to the multidimensional channel features; Based on the data packet tensor and the channel tensor, the coded data packets are routed by a deep learning algorithm to obtain a transmission channel corresponding to each coded data packet.

[0011] Determine a transmission characteristic tensor according to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein the transmission characteristic tensor is used to characterize the transmission coefficient of each encoded data packet on the transmission channel; Determine, according to the transmission characteristic tensor, the transmission power and transmission time slot of each of the encoded data packets on the transmission channel corresponding to the encoded data packet; According to the transmission power and the transmission time slot, a plurality of the encoded data packets are transmitted to the receiving end through their corresponding transmission channels.

[0012] Preferably, the receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result, including: The receiving end extracts a four-dimensional phase coding matrix from the synchronization header information of each of the coded data packets; Determining a phase error between a phase in the four-dimensional phase encoding matrix and a preset reference phase by a time-to-digital converter; Inputting the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and outputting the phase temperature drift compensation amount; Compensating the phase temperature drift amount by using the phase temperature drift compensation amount; The phase, the accumulated phase adjustment amount and the phase weighted average amount in the four-dimensional phase encoding matrix are compensated according to the compensated phase temperature drift amount and the phase error.

[0013] Preferably, the receiving end parses and reassembles a plurality of the encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation to restore the data to the originally transmitted data, including: The receiving end extracts the synchronization header information of the coded data packet after dynamic phase compensation to perform phase synchronization; Determining a sequence number of the encoded data packet according to the phase-synchronized encoded data packet; generating the request information according to the serial number of the encoded data packet, and sending the request information to the target device; The target device responds to the request information and searches for a key-value mapping data packet corresponding to the serial number in the virtual container according to the serial number of the encoded data packet included in the request information; Forwarding the key-value mapping data packet to the receiving end through the container image; The receiving end performs a reverse projection operation on the corresponding coded data packet through the key-value mapping data packet to obtain the original transmitted data of the coded data packet; The originally transmitted data of each of the encoded data packets are reordered according to the sequence number of each of the encoded data packets to obtain the originally transmitted data.

[0014] In a second aspect, the present invention provides an Ethernet synchronous communication device based on FPGA and dynamic phase shift, comprising: A data packetization module is used to packetize the data to be transmitted received by the sending end to obtain multiple data packets; A data encapsulation module, used for compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; A phase encoding module, used to perform phase encoding on the clock signal of each encapsulated data packet through FPGA control of a dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets; A data transmission module, used for transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; A phase compensation module, used for the receiving end to estimate the phase error according to the synchronization header information of each of the encoded data packets, and to perform dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The data reassembly module is used for the receiving end to parse and reassemble a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restore them to the originally transmitted data.

[0015] In a third aspect, the present invention provides an electronic device, characterized in that the electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in the first aspect.

[0016] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed, the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in the first aspect are implemented.

[0017] It can be seen from the above technical solutions that the present invention improves the transmission rate by subpacketizing the data to be transmitted received by the transmitting end, compressing and encapsulating multiple data packets. The dynamic phase shift algorithm is controlled by FPGA, and the clock signal of each encapsulated data packet is phase-encoded to generate a clock synchronization frame. Subsequently, it is transmitted to the receiving end in parallel via multi-channel Ethernet. The receiving end estimates the phase error based on the synchronization header information of each encoded data packet, and performs dynamic phase compensation on the clock signals of multiple encoded data packets based on the estimation results. Based on the synchronization header information after dynamic phase compensation, multiple encoded data packets are parsed and reorganized to restore the original transmission data. This method not only reduces the synchronization delay that may occur in high-speed data transmission through dynamic phase compensation, but also reasonably allocates and utilizes network communication resources through multi-channel parallel transmission, effectively avoiding resource waste and large-scale resource occupation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A process of an Ethernet synchronous communication method based on FPGA and dynamic phase shift provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of an Ethernet synchronous communication device based on FPGA and dynamic phase shift provided by an embodiment of the present invention; Figure 3 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] An embodiment of the present application provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, which can be applicable to Ethernet synchronous communication. The method can be executed by an Ethernet synchronous communication device, which can be implemented in the form of hardware and / or software, and the Ethernet synchronous communication device can be configured in a computer device.

[0022] like Figure 1 As shown, the embodiment of the present application provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, including the following steps S1 to S6. Among them: Step S1, packetizing the data to be transmitted received by the sending end to obtain multiple data packets.

[0023] The packetization rules for packetizing the data to be transmitted received by the sender can be set according to factors such as data type, size, priority, and transmission requirements. Through reasonable packetization rules, large amounts of data can be split into multiple smaller data packets to facilitate subsequent compression processing and encapsulation operations, and also help improve the flexibility and efficiency of data transmission.

[0024] Step S2, compressing the multiple data packets, and encapsulating the compressed multiple data packets to obtain multiple encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end.

[0025] It can be understood that compressing multiple data packets can reduce the size of the data packets, reduce the bandwidth occupied by data transmission, and improve transmission efficiency.

[0026] The synchronization header information refers to the key information used for data synchronization at the receiving end, which contains a specific identifier or sequence for clock synchronization. The synchronization header information is embedded in the encapsulated data packet, so that when the receiving end receives the data packet, it can accurately synchronize the clock based on the synchronization header information to ensure the correct parsing and reassembly of the data.

[0027] When encapsulating a data packet, in addition to including the synchronization header information, other necessary metadata can be added according to actual needs, such as the data packet's sequence number, checksum information, etc., so that the receiving end can process and verify the data packet more efficiently.

[0028] Step S3: Phase-encode the clock signal of each encapsulated data packet by controlling the dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets.

[0029] Among them, FPGA (field programmable gate array) as a hardware accelerator can process data streams in real time, while the dynamic phase shift algorithm achieves precise synchronization between data packets by finely adjusting the phase of the clock signal.

[0030] In this step, the clock signal of each encapsulated data packet is processed by the dynamic phase shift algorithm controlled by the FPGA and converted into a clock synchronization frame containing phase information. This clock synchronization frame is then embedded in the synchronization header information and together with the rest of the encapsulated data packet, it forms a coded data packet. In this way, each coded data packet not only contains the data to be transmitted, but also comes with key information for clock synchronization at the receiving end, ensuring the accuracy and reliability of data transmission.

[0031] Step S4: Transmit the multiple encoded data packets in parallel to the receiving end via a multi-channel Ethernet.

[0032] Among them, the multi-channel Ethernet transmission method is to distribute the coded data packets to multiple parallel channels for transmission, which can make full use of network bandwidth resources and improve the throughput of data transmission. In this step, each coded data packet is assigned to a specific channel for transmission, which is usually determined by factors such as the priority, size and channel load of the data packet. Through parallel transmission, not only can the data transmission speed be accelerated, but also the data pressure of a single channel can be reduced, and the stability and reliability of the entire transmission system can be improved.

[0033] Step S5: The receiving end estimates the phase error according to the synchronization header information of each coded data packet, and performs dynamic phase compensation on the clock signals of the multiple coded data packets according to the phase error estimation result.

[0034] It can be understood that the phase error estimation based on the synchronization header information of each coded data packet can ensure that the receiving end can accurately identify and correct the phase deviation that may occur during the transmission of the data packet. Through the clock synchronization frame embedded in the synchronization header information, the phase error is calculated by comparing the local clock of the receiving end with the clock synchronization frame in the data packet, and the impact of environmental perception on the phase is considered. Based on this, dynamic phase compensation is performed on the data packet to eliminate the phase deviation and ensure accurate reception and analysis of the data.

[0035] Step S6: The receiving end parses and reassembles the multiple coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation to restore them to the originally transmitted data.

[0036] The receiving end can sort and verify the coded data packets according to the metadata such as the sequence number and check information in the synchronization header information to ensure the integrity and correctness of the data packets. During the parsing process, the receiving end will extract the data part of the coded data packet and reorganize it according to the sequence of the data to restore the original transmitted data, that is, the data to be transmitted received by the sending end.

[0037] It should be noted that the embodiment of the present application performs packet processing on the data to be transmitted received by the transmitting end, compresses and encapsulates multiple data packets to improve the transmission rate. The dynamic phase shift algorithm is controlled by FPGA, and the clock signal of each encapsulated data packet is phase-encoded to generate a clock synchronization frame. Subsequently, it is transmitted to the receiving end in parallel via multi-channel Ethernet. The receiving end estimates the phase error based on the synchronization header information of each coded data packet, and performs dynamic phase compensation on the clock signals of multiple coded data packets based on the estimation results. Based on the synchronization header information after dynamic phase compensation, multiple coded data packets are parsed and reorganized to restore the original transmission data. This method not only reduces the synchronization delay that may occur in high-speed data transmission through dynamic phase compensation, but also reasonably allocates and utilizes network communication resources through multi-channel parallel transmission, effectively avoiding resource waste and large-scale resource occupation.

[0038] In some embodiments, compressing multiple data packets and encapsulating the compressed data packets to obtain multiple encapsulated data packets includes: Step S201: cluster multiple data packets to obtain multiple clusters; each cluster includes a cluster center data packet and other data packets except the cluster center data packet.

[0039] Among them, clustering can divide similar data packets into the same cluster according to the characteristics of the data packets, such as size, type or content. Each cluster contains a cluster center data packet and other data packets except the cluster center data packet. The cluster center data packet usually represents the main characteristics or attributes of the cluster and can be used as the representative of the cluster. By clustering the data packets, the compression and encapsulation process of the data packets can be further optimized, and the efficiency and quality of data transmission can be improved.

[0040] The clustering algorithm may be a K-means algorithm, a hierarchical clustering algorithm or a DBSCAN algorithm.

[0041] Step S202: construct a feature hyperplane based on the cluster center data packets, and project other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain the orthogonal projection matrix of other data packets.

[0042] Among them, the cluster center data packet C and other data packets are subjected to singular value decomposition respectively to obtain a set of orthogonal bases of the column space of the cluster center data packet C. The orthogonal bases are used to construct the feature hyperplane, and the matrix obtained by the singular value decomposition of each data packet is projected to the orthogonal complement space of the hyperplane: In the formula, is the orthogonal projection matrix of the ith data packet, is the ith data packet, , R is the space, L is the packet length, M is the feature dimension, is a diagonal matrix (the diagonal elements are the singular values ​​of the data packets).

[0043] Among them, the projection ensures that the original data can be reversibly restored: In the formula, is the coefficient vector.

[0044] Step S203: Perform topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix.

[0045] Among them, the operation of topological weighted coding is expressed as: Where A is the element after non-zero element encoding, The element before the non-zero element encoding, Based on topology information The function of It can be understood as a probability distribution or weight function of the element under given topological information, which is used to measure its topological importance. For the elements The relevant topological features include the position of the element in the tensor, the relationship with the adjacent elements, and the local structure. The topological information can be determined by calculating the neighborhood relationship between pixels, edge detection, etc., which will not be described here. is a hyperparameter greater than 0, used to adjust the influence of the exponential term in the weight. For elements The norm of .

[0046] Step S204: pre-process other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of other data packets.

[0047] Among them, the other data packets corresponding to the orthogonal projection coding matrix are converted into matrix form, that is, , whose dimension and structure correspond to the orthogonal projection coding matrix to facilitate subsequent data processing.

[0048] Step S205: Perform a projection compression operation on matrices of other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet.

[0049] Among them, the matrix of other data packets corresponding to the orthogonal projection coding matrix is ​​projected through the orthogonal projection coding matrix, that is: Where Y is the matrix of the data packet after projection, is the transpose of the orthogonal projection encoding matrix.

[0050] It can be understood that by performing projection compression operations on matrices of other data packets corresponding to the orthogonal projection coding matrix through the orthogonal projection coding matrix, the data packets are converted into a new space defined by the orthogonal projection coding matrix, achieving data dimensionality reduction, occupying less storage space, and thus achieving data compression. When the original data is needed, the data can be restored by the inverse operation.

[0051] Step S206: Encapsulate each cluster center data packet and the compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet to obtain a plurality of encapsulated data packets.

[0052] It can be understood that the embodiment of the present application performs data compression on data packets of different clusters, and the cluster center data packet of each cluster represents the main features of the cluster. Therefore, in the encapsulation process, the cluster center data packet is encapsulated together with its corresponding compressed data packet, which can retain the main information of the data packet and reduce data redundancy. In this way, after receiving the encapsulated data packet, the receiving end can quickly understand the main content and features of the data packet based on the cluster center data packet, thereby improving the efficiency of data parsing and reorganization.

[0053] In some embodiments, the method further comprises: Step S21, packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet; Wherein, each orthogonal projection coding matrix and its corresponding data packet (in the form before or after compression) are combined to form a data packet unit.

[0054] Then, a unique serial number is assigned to each such data packet unit, which is derived from the original data packet, ensuring the traceability between the data packet unit and the original data. This serial number is used as a key and together with the data packet unit, it forms a key-value pair. All such key-value pairs are collected together to form a key-value mapping data packet.

[0055] Mapping data packets with key values ​​facilitates data storage and management, and also facilitates subsequent data retrieval and processing. When a specific data packet needs to be accessed or processed, the corresponding data packet can be quickly located based on the sequence number (i.e., key), greatly improving the efficiency of data processing.

[0056] Step S22: The key-value mapping data packet is transmitted to the virtual container of the target device to obtain a container image. The container image is used to respond to the request information of the receiving end and forward the key-value mapping data packet corresponding to the key specified in the request information to the receiving end.

[0057] A container image is a lightweight, executable software package that contains the code, runtime, system tools, system libraries, and other resources required to run an application. By placing the key-value mapping data package in the container image, the consistency and portability of the data package in different environments can be ensured.

[0058] When building a container image, you first need to package the key-value mapping data package and related dependencies and configuration files together to form a complete image file. This image file can then be deployed to any target device that supports container technology without having to worry about the differences in the underlying operating system, thus achieving cross-platform data sharing and processing.

[0059] Among them, the key-value mapping data packet is encapsulated into a container image to achieve flexible deployment and efficient transmission of data. When the receiving end needs to access a specific data packet, it sends a request message to the target device, specifying the key to be obtained (that is, the serial number of the data packet). After receiving the request, the target device will quickly locate the corresponding key-value mapping data packet based on the mapping relationship in the container image and forward it to the receiving end. This process not only improves the efficiency of data access, but also ensures the security and integrity of the data.

[0060] In addition, container images also have version control functions, which can easily manage and update key-value mapping data packages. Whenever the data package changes, a new container image version can be created and deployed and updated when necessary, thus achieving continuous integration and continuous delivery of data.

[0061] Therefore, the embodiment of the present application can greatly improve the flexibility and portability of data by transmitting the key-value mapping data packet to the virtual container of the target device and obtaining the container image.

[0062] In some embodiments, the clock signal of each encapsulated data packet is phase-encoded by controlling the dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain multiple encoded data packets, including: Step S301: For each encapsulated data packet, extract data feature information of the encapsulated data packet.

[0063] The data characteristic information of the encapsulated data packet includes the size of the data packet, the data priority, the generation time of the data packet and the source of the data packet.

[0064] Step S302: Based on the data feature information, the clock signal of the encapsulated data packet is multi-dimensionally phase-space encoded by controlling the dynamic phase shift algorithm through the FPGA to obtain a four-dimensional phase encoding matrix; wherein the dimensions of the four-dimensional phase encoding matrix include phase, cumulative phase adjustment amount, phase weighted average amount and phase temperature drift amount.

[0065] Specifically, the clock signal of the encapsulated data packet is adjusted according to the data feature information through the phase modulator integrated inside the FPGA. For example, a high-priority data packet can be given a larger phase offset to ensure that it is processed first. The larger the data packet, the larger the phase offset can be given to ensure that it is processed first. The more important the source of the data packet, the larger the phase offset can be given to ensure that it is processed first.

[0066] By mapping the clock signal of the encapsulated data packet into a multi-dimensional phase space, each dimension represents different phase information.

[0067] The phase dimension records the basic phase information of the clock signal; The cumulative phase adjustment dimension is used to record the phase deviation that may be accumulated during the transmission of the data packet; the cumulative phase adjustment is calculated taking into account the generation time and size of the data packet. For example, if the data packet is generated later or the data packet is larger, the cumulative phase adjustment can be appropriately increased.

[0068] Among them, the accumulated phase adjustment amount = +a1×packet size+a2×packet generation time, where a1 and a2 are weights, For phase.

[0069] The phase weighted average dimension smoothes the phase information to reduce the impact of noise and interference; data packets from different sources can be given different weights to reflect their importance.

[0070] Among them, the phase weighted average is: In the formula, is the phase weighted average, s is the number of data feature dimensions, is the weight, For phase.

[0071] The dimension of phase temperature drift is that the internal temperature of the FPGA may affect the phase of the clock signal. The internal temperature of the FPGA can be monitored in real time through a temperature sensor, and adjustments can be made based on the relationship between temperature and phase drift to ensure the stability of the clock signal.

[0072] The phase temperature drift is: Phase temperature drift = In the formula, is the temperature drift coefficient, is the current ambient temperature, Stable for reference.

[0073] Step S303: perform initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain a clock synchronization frame.

[0074] Among them, by monitoring the phase deviation change rate of the encapsulated data packet during transmission, the four-dimensional phase coding matrix is ​​dynamically adjusted using the phase compensation module inside the FPGA. The phase deviation change rate reflects the trend of the phase offset of the data packet during transmission. By predicting this trend, the phase coding can be compensated in advance to reduce synchronization errors.

[0075] Specifically, the operation of performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate is expressed as: In the formula, is the four-dimensional phase encoding matrix after pre-compensation, is the original four-dimensional phase encoding matrix, is the compensation coefficient, is the phase deviation, For time.

[0076] Step S304: embed the clock synchronization frame into the synchronization header information, and during the embedding process, insert the phase synchronization header into the synchronization header information to obtain a coded data packet; wherein the phase synchronization header is used to predict the phase of the next coded data packet.

[0077] Among them, a phase synchronization header is inserted during data packet encapsulation. The phase synchronization header is used to predict the phase of the next encoded data packet to ensure the clock synchronization of the data packet during transmission. The phase synchronization header contains important information about the phase of the clock signal. The receiving end can adjust the phase of the received data packet based on this information to match the clock signal of the sending end, thereby achieving accurate clock synchronization. By embedding the clock synchronization frame and phase synchronization header, the clock synchronization of the data packet during transmission is ensured, improving the reliability and stability of data transmission.

[0078] The expression of the phase synchronization header is: In the formula, is the phase synchronization header code, is the preamble, is a cyclic redundancy check code, is the absolute phase mark of the current data packet, is the next packet phase prediction value based on LSTM.

[0079] Among them, LSTM (Long Short-Term Memory Network) can process time series data and capture long-term dependencies. Here, by training on relevant data such as the phase information of previous packets, LSTM can predict the phase change value of the next packet. The receiving end can use this predicted value to adjust the clock in advance, improve the accuracy and timeliness of clock synchronization, and reduce the impact of phase error on data transmission.

[0080] In some embodiments, transmitting multiple encoded data packets in parallel to a receiving end via a multi-channel Ethernet includes: Step S401: for each encoded data packet, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features.

[0081] Among them, multi-dimensional data packet features of the encoded data packet are extracted, including the size of the data packet, the transmission priority of the data packet, the generation timestamp of the data packet, the source address and destination address of the data packet, the checksum of the data packet, and the protocol type to which the data packet belongs.

[0082] The characteristic information of the encoded data packet is integrated into a multidimensional array, namely the data packet tensor. Each dimension of the data packet tensor represents a different characteristic of the data packet, which together constitute a complete description of the data packet during transmission. The data packet tensor of the encoded data packet is represented as: In the formula, is the packet tensor, is the length of the encoded data packet, is the dimension of the multi-dimensional data packet feature.

[0083] Step S402: for each channel in the Ethernet, extract the multi-dimensional channel features of the channel, and construct a channel tensor of the channel according to the multi-dimensional channel features.

[0084] The transmission characteristics of each channel are modeled and the multi-dimensional channel features of the channel are extracted, including the channel bandwidth, delay, jitter, packet loss rate and channel availability, etc. These features reflect the performance of the channel during data transmission.

[0085] The characteristic information of the channel is integrated into a multidimensional array, namely the channel tensor. Each dimension of the channel tensor represents a different characteristic of the channel, which together constitute a complete description of the channel during data transmission. The tensor representation of the channel in Ethernet is: In the formula, is the channel tensor, is the number of channels, is the dimension of the multi-dimensional channel feature.

[0086] Step S403: Based on the data packet tensor and the channel tensor, the coded data packet is routed by a deep learning algorithm to obtain a transmission channel corresponding to each coded data packet. Specifically, the data packet tensor and the channel tensor are used as training data sets for the deep learning model. The deep learning model can find the best matching relationship between the data packet tensor and the channel tensor by training the training data set.

[0087] During the training phase, the model receives a large number of packets and channel samples marked with the correct routing, and continuously adjusts the model parameters through the back-propagation algorithm to minimize the prediction error. Once the model is trained, it can quickly route the newly encoded packets.

[0088] The deep learning model contains multiple hidden layers, which gradually extract high-level features of data packets and channels through complex nonlinear transformations. These high-level features are used in the output layer of the model to make routing decisions, that is, to determine which channel each encoded data packet should be transmitted through.

[0089] After the deep learning model training is completed, the channel tensor corresponding to the data packet and the channel label corresponding to the channel tensor can be output by inputting the data packet tensor of the data packet.

[0090] It is understandable that deep learning algorithms can intelligently select the optimal transmission channel based on the current network conditions and data packet characteristics, thereby maximizing the efficiency and reliability of data transmission. This data-driven routing selection method has stronger adaptability and higher performance than traditional rule-based or heuristic methods.

[0091] Step S404, determining a transmission characteristic tensor according to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein the transmission characteristic tensor is used to characterize the transmission coefficient of each encoded data packet on the transmission channel.

[0092] Among them, the transmission characteristic tensor is calculated by comprehensively considering the information of the data packet tensor and the channel tensor. The transmission characteristic tensor is a multidimensional array, each element of which represents the transmission coefficient of the corresponding encoded data packet on the corresponding transmission channel. The transmission coefficient is expressed as: In the formula, is the transmission coefficient between the u-th data packet and the g-th transmission channel, is the weight, is the mth feature of the uth data packet, is the d-th feature of the g-th transmission channel.

[0093] Step S405: Determine the transmission power and transmission time slot of each coded data packet on the transmission channel corresponding to the coded data packet according to the transmission characteristic tensor.

[0094] The goal of adjusting the transmission power is to minimize power consumption while ensuring the correct transmission of data packets, so as to improve the transmission utilization rate. The power can be adjusted based on the transmission coefficient in the transmission characteristic tensor, combined with the relationship between the bit error rate and the signal-to-noise ratio (SNR). Assume that the initial power of the u-th data packet on the g-th channel is , the power adjusted according to the transmission coefficient is , the transmission power can be determined using the following formula: Where g() is the adjusted linear function, is the target bit error rate, is the current bit error rate.

[0095] The goal of adjusting the transmission time slot is to reasonably allocate channel resources, avoid conflicts and interference between data packets, and improve transmission efficiency. The transmission time slot can be adjusted based on the transmission coefficient in the transmission characteristic tensor, combined with the priority of the data packet and the bandwidth of the channel.

[0096] The data packets are sorted according to the transmission coefficient, and the data packets with large transmission coefficients are transmitted first. Then, according to the bandwidth of the channel and the length of the data packet, the transmission time slot required for each data packet is calculated. For example, the transmission time slot required for the u-th data packet on the g-th channel is: In the formula, is the transmission time slot required for the u-th data packet on the g-th channel, is the length of the data packet, is the bandwidth of the g-th transmission channel.

[0097] Step S406: transmit the plurality of encoded data packets to the receiving end through their corresponding transmission channels according to the transmission power and the transmission time slot.

[0098] Among them, according to the transmission power and transmission time slot, the coded data packets and their corresponding transmission channels are allocated, and the coded data packets can be placed in the queue according to the order of their transmission time slots. When a certain time slot is reached, the coded data packet corresponding to the time slot is sent out through its corresponding transmission channel. At the same time, the transmission power of the transmitter is adjusted according to the transmission power to ensure that the data packet can be correctly transmitted to the receiving end.

[0099] In some embodiments, the receiving end estimates the phase error according to the synchronization header information of each coded data packet, and performs dynamic phase compensation on the clock signals of the multiple coded data packets according to the phase error estimation result, including: Step S501: The receiving end extracts the four-dimensional phase coding matrix in the synchronization header information of each coded data packet.

[0100] Step S502: Determine a phase error between a phase in a four-dimensional phase encoding matrix and a preset reference phase by using a time-to-digital converter.

[0101] The receiving end needs to accurately measure the phase error between the received signal and the reference signal. The time-to-digital converter (TDC) can accurately measure the phase error between the rising edges of two signals, specifically: In the formula, is the phase error, is the clock frequency, () is the actual phase of the received signal Phase with reference The time difference between.

[0102] Step S503: input the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and output a phase temperature drift compensation amount.

[0103] Among them, since the aforementioned four-dimensional phase coding matrix contains the current phase temperature drift compensation amount predicted by LSTM, the phase temperature drift compensation amount in the four-dimensional phase coding matrix is ​​input into the pre-trained LSTM phase temperature drift prediction model to output the phase temperature drift compensation amount at the receiving end.

[0104] Step S504: Compensate the phase temperature drift amount by using the phase temperature drift compensation amount.

[0105] The phase temperature drift actually measured at the receiving end is added to the phase temperature drift compensation to obtain the compensated phase temperature drift, thereby reducing the phase error caused by temperature drift and further improving the accuracy and stability of clock synchronization.

[0106] Step S505 , compensating the phase, the accumulated phase adjustment amount and the phase weighted average amount in the four-dimensional phase encoding matrix according to the compensated phase temperature drift amount and the phase error.

[0107] The phase temperature drift after compensation obtained in the above steps is used to adjust the phase in the four-dimensional phase encoding matrix accordingly. The compensation operation can be expressed as: In the formula, is the phase after compensation, is the original phase, is the phase temperature drift compensation; and are weights, is a constant that controls the degree of attenuation. is the order, It can be set based on experience, and is generally taken as an integer greater than 2, to characterize the nonlinear relationship between phase and temperature.

[0108] The accumulated phase adjustment amount and the phase weighted average amount are adjusted using the compensated phase to ensure the overall phase synchronization accuracy.

[0109] It is understandable that through phase compensation measures, the receiving end can accurately and dynamically compensate the clock signal of the received coded data packet, thereby effectively reducing the phase error caused by various interference factors (such as temperature drift, phase deviation change, etc.) during the transmission process. This not only improves the clock synchronization accuracy of data transmission, but also enhances the stability and reliability of data transmission, and provides a strong guarantee for the performance of the Ethernet synchronous communication method and device based on FPGA and dynamic phase shift in practical applications.

[0110] In some embodiments, the receiving end parses and reassembles multiple coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation to restore the data to the original transmitted data, including: Step S601: The receiving end extracts the synchronization header information of the coded data packet after dynamic phase compensation to perform phase synchronization.

[0111] The receiving end first parses the phase synchronization header in the synchronization header information, and uses the phase information therein to adjust the phase of the received data packet to ensure that the data packet is synchronized with the clock signal of the sending end. The phase synchronization process involves comparing and adjusting the phase of the received data packet with the predicted phase of the sending end. Through precise phase control, data transmission errors caused by phase deviation can be significantly reduced.

[0112] Step S602: Determine the sequence number of the coded data packet according to the phase-synchronized coded data packet.

[0113] Among them, by parsing the sequence number field in the synchronization header information, the receiving end can identify the order of each data packet. The sequence number ensures the order of the data packet during transmission. Even if the data packet is lost or out of order during transmission, the receiving end can reorder it according to the sequence number and restore the original order of the data.

[0114] Step S603: Generate request information according to the serial number of the encoded data packet, and send the request information to the target device.

[0115] Step S604, the target device responds to the request information, and according to the serial number of the encoded data packet contained in the request information, finds the key-value mapping data packet corresponding to the serial number in the virtual container. After receiving the request information, the target device will parse the serial number in the request information and find the key-value mapping data packet corresponding to the serial number in the virtual container it maintains. The virtual container is a logical data structure used to store and manage data packets and related information, such as serial numbers, data packet contents, checksums, etc.

[0116] It is understandable that, through the key-value mapping method, the target device can quickly locate the required data packet, thereby improving the efficiency of data retrieval.

[0117] Step S605: forward the key-value mapping data packet to the receiving end through the container image. Step S606: The receiving end performs a reverse projection operation on the corresponding coded data packet through the key-value mapping data packet to obtain the original transmitted data of the coded data packet.

[0118] Among them, due to the aforementioned compression processing of multiple data packets, the data packets are projected, and at the same time, this projection operation is reversible. Therefore, the receiving end uses the information in the received key-value mapping data packet to perform reverse projection processing on the previously received encoded data packet, and gradually restores the original data of the encoded data packet before transmission.

[0119] Before the reverse projection process, the receiving end will also use information such as checksums to verify the integrity of the data packet to ensure that no errors occurred during the data transmission process. If an error is detected, the receiving end will attempt to correct the error or request the sending end to resend the erroneous data packet. Finally, after the reverse projection operation, the receiving end can successfully restore the original transmitted data and complete the entire data transmission process. This process not only ensures the reliability of data transmission, but also improves the efficiency of data transmission.

[0120] Step S607: reorder the originally transmitted data of each encoded data packet according to the sequence number of each encoded data packet to obtain the originally transmitted data.

[0121] After the receiving end successfully recovers the original transmission data of all the coded data packets, it will reorder the data according to the sequence number of the coded data packets. The sequence number, as a key identifier of the data packet, ensures the orderliness of the data packet during transmission and reception. Through the reordering operation, the receiving end can restore the data to their original order at the sending end, thereby ensuring the integrity and consistency of the data.

[0122] During the reordering process, the receiver checks the sequence number of each data packet and sorts them according to the size of the sequence number. If the sequence number is discontinuous or repeated, the receiver will take corresponding measures, such as requesting the sender to resend the missing or repeated data packets to ensure the integrity and accuracy of the data.

[0123] After the reordering is completed, the receiving end can obtain the originally transmitted data.

[0124] Based on the same inventive concept, an embodiment of the present application further provides an Ethernet synchronous communication device based on FPGA and dynamic phase shift for implementing the above-mentioned Ethernet synchronous communication method based on FPGA and dynamic phase shift.

[0125] The implementation solution to the problem provided by the device is similar to the implementation solution recorded in the above method. Therefore, the specific limitations in one or more embodiments of the Ethernet synchronous communication device based on FPGA and dynamic phase shift provided below can be found in the above limitations on the Ethernet synchronous communication method based on FPGA and dynamic phase shift, and will not be repeated here.

[0126] like Figure 2 As shown, the embodiment of the present application provides an Ethernet synchronous communication device based on FPGA and dynamic phase shift, including: The data packetization module 100 is used to packetize the data to be transmitted received by the transmitting end to obtain multiple data packets; The data encapsulation module 200 is used to compress multiple data packets and encapsulate the compressed data packets to obtain multiple encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; The phase encoding module 300 is used to perform phase encoding on the clock signal of each encapsulated data packet through FPGA control of a dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into synchronization header information to obtain multiple encoded data packets; The data transmission module 400 is used to transmit multiple encoded data packets in parallel to a receiving end via a multi-channel Ethernet; The phase compensation module 500 is used for the receiving end to estimate the phase error according to the synchronization header information of each coded data packet, and to perform dynamic phase compensation on the clock signals of multiple coded data packets according to the phase error estimation result; The data reassembly module 600 is used at the receiving end to parse and reassemble multiple coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restore them to the originally transmitted data.

[0127] In some embodiments, the data encapsulation module 200 is used to: Clustering multiple data packets to obtain multiple clusters; each cluster includes a cluster center data packet and other data packets except the cluster center data packet; Construct a feature hyperplane based on the cluster center data packets, and project other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain the orthogonal projection matrix of other data packets; Perform topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix; Preprocessing other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of other data packets; Performing a projection compression operation on matrices of other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet; Each cluster center data packet and compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet are encapsulated to obtain a plurality of encapsulated data packets.

[0128] In some embodiments, the device further includes: a data mirroring module, configured to: Packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet; The key-value mapping data packet is transmitted to the virtual container of the target device to obtain a container image, and the container image is used to respond to the request information of the receiving end and forward the key-value mapping data packet corresponding to the key specified in the request information to the receiving end.

[0129] In some embodiments, the phase encoding module 300 is used to: For each encapsulated data packet, extract data feature information of the encapsulated data packet; According to the data feature information, the clock signal of the encapsulated data packet is multi-dimensionally phase-space encoded through the FPGA-controlled dynamic phase shift algorithm to obtain a four-dimensional phase encoding matrix; wherein the dimensions of the four-dimensional phase encoding matrix include phase, cumulative phase adjustment amount, phase weighted average amount and phase temperature drift amount; Performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain a clock synchronization frame; The clock synchronization frame is embedded in the synchronization header information, and during the embedding process, the phase synchronization header is inserted into the synchronization header information to obtain a coded data packet; wherein the phase synchronization header is used to predict the phase of the next coded data packet.

[0130] In some embodiments, the data transmission module 400 is used to: For each encoded data packet, extract a multi-dimensional data packet feature of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet feature; For each channel in the Ethernet, the multi-dimensional channel features of the channel are extracted, and the channel tensor of the channel is constructed according to the multi-dimensional channel features; Based on the data packet tensor and channel tensor, the coded data packets are routed through a deep learning algorithm to obtain the transmission channel corresponding to each coded data packet.

[0131] Determine a transmission characteristic tensor according to a data packet tensor of the coded data packet and a channel tensor of a transmission channel corresponding to the coded data packet; wherein the transmission characteristic tensor is used to characterize a transmission coefficient of each coded data packet on the transmission channel; Determine the transmission power and transmission time slot of each coded data packet on the transmission channel corresponding to the coded data packet according to the transmission characteristic tensor; According to the transmission power and the transmission time slot, a plurality of coded data packets are transmitted to the receiving end through their corresponding transmission channels.

[0132] In some embodiments, the phase compensation module 500 is used to: The receiving end extracts the four-dimensional phase coding matrix in the synchronization header information of each coded data packet; Determine the phase error between the phase in the four-dimensional phase encoding matrix and a preset reference phase by a time-to-digital converter; The phase temperature drift amount in the four-dimensional phase encoding matrix is ​​input into the pre-trained LSTM phase temperature drift prediction model, and the phase temperature drift compensation amount is output; The phase temperature drift amount is compensated by the phase temperature drift compensation amount; The phase, the accumulated phase adjustment amount and the phase weighted average amount in the four-dimensional phase encoding matrix are compensated according to the compensated phase temperature drift amount and the phase error.

[0133] In some embodiments, the data reassembly module 600 is used to: The receiving end extracts the synchronization header information of the coded data packet after dynamic phase compensation to perform phase synchronization; Determine the sequence number of the coded data packet according to the phase-synchronized coded data packet; Generate a request message according to the sequence number of the encoded data packet, and send the request message to the target device; The target device responds to the request information and searches for a key-value mapping data packet corresponding to the serial number in the virtual container according to the serial number of the encoded data packet contained in the request information; Forward the key-value mapping data packet to the receiving end through the container image; The receiving end performs a reverse projection operation on the corresponding coded data packet through the key-value mapping data packet to obtain the original transmitted data of the coded data packet; The originally transmitted data of each encoded data packet is reordered according to the sequence number of each encoded data packet to obtain the originally transmitted data.

[0134] like Figure 3 As shown, an embodiment of the present application provides an electronic device, the electronic device 10 includes a memory 20 and a processor 30, the memory 20 stores a computer program, and when the computer program is executed by the processor 30, the processor 30 executes the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift in the above embodiment.

[0135] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed, the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in the above embodiment are implemented.

[0136] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, electronic device and computer storage medium can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0137] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatus.

[0138] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0139] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, electronic devices, computer storage media and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0140] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0141] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0142] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for executing all or part of the steps of the method described in each embodiment of the present invention through a computer device (which can be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (full name in English: Read-Only Memory, English abbreviation: ROM), random access memory (full name in English: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program codes.

[0143] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An Ethernet synchronous communication method based on FPGA and dynamic phase shift, characterized in that: include: The data to be transmitted received by the sending end is divided into packets to obtain multiple data packets; Compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; the encapsulated data packets include synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; Phase encoding is performed on the clock signal of each encapsulated data packet by controlling a dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain multiple encoded data packets; Transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The receiving end parses and reassembles a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restores the coded data to the originally transmitted data.

2. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: The step of compressing the plurality of data packets and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets comprises: Clustering the plurality of data packets to obtain a plurality of clusters; each of the clusters includes a cluster center data packet and other data packets except the cluster center data packet; Constructing a feature hyperplane according to the cluster center data packets, and projecting other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain an orthogonal projection matrix of the other data packets; Performing topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix; Preprocessing other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of the other data packets; Performing a projection compression operation on the matrix of the other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet; Each of the cluster center data packets and compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet are encapsulated to obtain a plurality of encapsulated data packets.

3. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 2, characterized in that: Also includes: Packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet; The key-value mapping data packet is transmitted to the virtual container of the target device to obtain a container image, and the container image is used to respond to the request information of the receiving end and forward the key-value mapping data packet corresponding to the key specified in the request information to the receiving end.

4. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: The method controls the dynamic phase shift algorithm through FPGA to perform phase encoding on the clock signal of each encapsulated data packet to obtain a clock synchronization frame, and embeds the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets, including: For each of the encapsulated data packets, extracting data feature information of the encapsulated data packet; According to the data feature information, a clock signal of the encapsulated data packet is multi-dimensionally phase-space encoded by controlling a dynamic phase shift algorithm through an FPGA to obtain a four-dimensional phase encoding matrix; wherein the dimensions of the four-dimensional phase encoding matrix include a phase, an accumulated phase adjustment amount, a phase weighted average amount, and a phase temperature drift amount; Performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain the clock synchronization frame; The clock synchronization frame is embedded in the synchronization header information, and during the embedding process, a phase synchronization header is inserted into the synchronization header information to obtain the encoded data packet; wherein the phase synchronization header is used to predict the phase of the next encoded data packet.

5. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: The step of transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet comprises: For each of the encoded data packets, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features; For each channel in the Ethernet, extract the multidimensional channel features of the channel, and construct a channel tensor of the channel according to the multidimensional channel features; Based on the data packet tensor and the channel tensor, routing the encoded data packets is performed by a deep learning algorithm to obtain a transmission channel corresponding to each encoded data packet; Determine a transmission characteristic tensor according to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein the transmission characteristic tensor is used to characterize the transmission coefficient of each encoded data packet on the transmission channel; Determine, according to the transmission characteristic tensor, the transmission power and transmission time slot of each of the encoded data packets on the transmission channel corresponding to the encoded data packet; According to the transmission power and the transmission time slot, a plurality of the encoded data packets are transmitted to the receiving end through their corresponding transmission channels.

6. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 4, characterized in that: The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result, including: The receiving end extracts a four-dimensional phase coding matrix from the synchronization header information of each of the coded data packets; Determining a phase error between a phase in the four-dimensional phase encoding matrix and a preset reference phase by a time-to-digital converter; Inputting the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and outputting the phase temperature drift compensation amount; Compensating the phase temperature drift amount by using the phase temperature drift compensation amount; The phase, the accumulated phase adjustment amount and the phase weighted average amount in the four-dimensional phase encoding matrix are compensated according to the compensated phase temperature drift amount and the phase error.

7. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 3, characterized in that: The receiving end parses and reassembles a plurality of the encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation to restore the data to the original transmitted data, including: The receiving end extracts the synchronization header information of the coded data packet after dynamic phase compensation to perform phase synchronization; Determining a sequence number of the encoded data packet according to the phase-synchronized encoded data packet; generating the request information according to the serial number of the encoded data packet, and sending the request information to the target device; The target device responds to the request information and searches for a key-value mapping data packet corresponding to the serial number in the virtual container according to the serial number of the encoded data packet included in the request information; Forwarding the key-value mapping data packet to the receiving end through the container image; The receiving end performs a reverse projection operation on the corresponding coded data packet through the key-value mapping data packet to obtain the original transmitted data of the coded data packet; The originally transmitted data of each of the encoded data packets are reordered according to the sequence number of each of the encoded data packets to obtain the originally transmitted data.

8. An Ethernet synchronous communication device based on FPGA and dynamic phase shift, characterized in that: include: A data packetization module is used to packetize the data to be transmitted received by the sending end to obtain multiple data packets; A data encapsulation module, used for compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; A phase encoding module, used to perform phase encoding on the clock signal of each encapsulated data packet through FPGA control of a dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets; A data transmission module, used for transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; A phase compensation module, used for the receiving end to estimate the phase error according to the synchronization header information of each of the encoded data packets, and to perform dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The data reassembly module is used for the receiving end to parse and reassemble a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restore them to the originally transmitted data.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in any one of claims 1 to 7 are implemented.

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