Micro-LED chip, preparation method thereof and display equipment

Abstract

The invention provides a Micro-LED chip, a preparation method thereof and display equipment, and relates to the technical field of semiconductors. When the laser irradiation treatment is carried out, the multi-quantum well layer below the area which is not covered by the patterned dielectric layer is modified by laser and loses the light-emitting characteristic, and the light-emitting characteristic of the multi-quantum well layer below the area which is covered by the patterned dielectric layer is not influenced, so that the preparation of the Micro-LED chip is realized. In other words, the Micro-LED chips are directly defined by adopting a method of processing the wafer through laser irradiation to form the Micro-LED chip array, the technical scheme avoids ICP etching damage in a mesa manufacturing process, the size of a single Micro-LED chip does not need to be defined, a side wall passivation process is not needed, the cost can be effectively reduced, and the production efficiency is improved. The method is expected to play a key role in multiple applications such as future ultimate display, visible light communication and optical interconnection-based memories.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a Micro-LED chip, a preparation method thereof, and a display device. Background Art

[0002] Micro-LED refers to a semiconductor light-emitting device with a light-emitting size less than 100μm. It has significant advantages such as high brightness, low power consumption, long life, and nanosecond response rate. It has great potential in display and 6G visible light communication.

[0003] The extremely small size of Micro-LED chips is limited by many factors. First, the process technology. The size of traditional semiconductor optoelectronic devices is in the hundreds of microns, and the traditional process technology line cannot meet the micron or even sub-micron process requirements of Micro-LED chips. Second, Micro-LED chips face serious size effects and low luminous efficiency. The size effect comes from the defect damage or dangling bonds introduced at the exposed sidewalls during mesa etching by inductively coupled plasma (ICP). These defect damage or dangling bonds can serve as non-radiative recombination centers, reducing the internal quantum efficiency of Micro-LED chips. The smaller the size, the higher the sidewall etching damage density, and the more serious the decline in the efficiency of Micro-LED chips.

[0004] Therefore, how to develop new Micro-LED chip preparation technology to promote the development and application of Micro-LED chips is a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] In view of the above problems, the present application provides a Micro-LED chip and a method for manufacturing the same, and a display device, to achieve the purpose of optimizing the Micro-LED chip manufacturing technology. The specific solution is as follows:

[0006] In a first aspect, the present application provides a method for preparing a Micro-LED chip, the method for preparing a Micro-LED chip comprising:

[0007] providing a substrate;

[0008] forming an epitaxial structure on one side of the substrate, the epitaxial structure comprising an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer stacked in sequence;

[0009] forming a groove at least penetrating the P-type semiconductor layer and the multi-quantum well layer to expose a portion of the surface of the N-type semiconductor layer;

[0010] A patterned dielectric layer is formed on a side of the epitaxial structure away from the substrate, the patterned dielectric layer covers the exposed surface of the N-type semiconductor layer and a portion of the surface of the P-type semiconductor layer away from the substrate; the patterned dielectric layer has a plurality of first grooves, the first grooves expose another portion of the surface of the P-type semiconductor layer away from the substrate;

[0011] Performing laser irradiation treatment on a side where the patterned dielectric layer is provided, so that a region of the multi-quantum well layer corresponding to a region where the first groove is located in a first direction loses its luminescence property; the first direction is perpendicular to a plane where the substrate is located;

[0012] The patterned dielectric layer is removed, and an N electrode and a P electrode are formed; the N electrode is connected to the N-type semiconductor layer, and the P electrode is connected to the P-type semiconductor layer.

[0013] Preferably, in the above-mentioned method for preparing the Micro-LED chip, the laser irradiation treatment is performed on the side where the patterned dielectric layer is provided, comprising:

[0014] An X-ray laser is used to perform laser irradiation treatment on the side where the patterned medium layer is disposed.

[0015] Preferably, in the above-mentioned method for preparing a Micro-LED chip, the patterned dielectric layer comprises a stacked silicon oxide film layer and a lead layer;

[0016] The step of forming a patterned dielectric layer on a side of the epitaxial structure away from the substrate comprises:

[0017] forming the silicon oxide film layer on a side of the epitaxial structure away from the substrate;

[0018] The lead layer is formed on a side of the silicon oxide film layer facing away from the substrate.

[0019] Preferably, in the above-mentioned method for preparing the Micro-LED chip, the patterned dielectric layer comprises a stacked silicon oxide film layer and a tungsten layer;

[0020] The step of forming a patterned dielectric layer on a side of the epitaxial structure away from the substrate comprises:

[0021] forming the silicon oxide film layer on a side of the epitaxial structure away from the substrate;

[0022] The tungsten layer is formed on a side of the silicon oxide film layer facing away from the substrate.

[0023] Preferably, in the above-mentioned method for preparing the Micro-LED chip, the P electrode comprises a Ni layer and an Ag layer which are stacked.

[0024] Preferably, in the above-mentioned method for preparing the Micro-LED chip, the N electrode comprises a stacked Ti layer, an Al layer, a Ni layer and an Au layer.

[0025] Preferably, in the above-mentioned method for preparing the Micro-LED chip, when laser irradiation treatment is performed on the side provided with the patterned dielectric layer, the longitudinal dimension of the laser spot is at least greater than the total thickness of the multi-quantum well layer and the P-type semiconductor layer.

[0026] Preferably, in the above-mentioned method for preparing a Micro-LED chip, the method for preparing a Micro-LED chip further comprises:

[0027] The P electrode and the N electrode are subjected to an annealing process.

[0028] A second aspect of the present application provides a Micro-LED chip, characterized in that the Micro-LED chip is obtained by any of the above-mentioned methods for preparing a Micro-LED chip.

[0029] A third aspect of the present application provides a display device, which includes the Micro-LED chip described above.

[0030] By means of the above technical solution, the present application provides a Micro-LED chip and a method for preparing the same, and a display device. After exposing a portion of the surface of the N-type semiconductor layer, a patterned dielectric layer is formed on the side of the epitaxial structure away from the substrate to cover the surface exposed to the N-type semiconductor layer and a portion of the surface of the P-type semiconductor layer away from the substrate. Since the patterned dielectric layer has a plurality of first grooves, the first grooves expose another portion of the surface of the P-type semiconductor layer away from the substrate. When laser irradiation is performed, the multi-quantum well layer below the area not covered by the patterned dielectric layer will be modified by the laser and lose its luminescence characteristics, while the luminescence characteristics of the multi-quantum well layer below the area covered by the patterned dielectric layer will not be affected, thereby realizing the preparation of the Micro-LED chip. In other words, the Micro-LED chip is directly defined by using the method of laser irradiation to process the wafer to form a Micro-LED chip array, which is also called a pixel array. This technical solution avoids ICP etching damage in the mesa manufacturing process, and there is no need to define the size of a single Micro-LED chip, that is, there is no need to define the size of a single pixel, and there is no need for sidewall passivation process, which can effectively reduce costs. It is expected to play a key role in many applications in the future, such as ultimate display, visible light communication, and memory based on optical interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0032] Figure 1 A schematic diagram of a process for preparing a Micro-LED chip provided in an embodiment of the present invention;

[0033] Figure 2-Figure 8 for Figure 1 Schematic diagram of the partial structure corresponding to the preparation method shown. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation mode of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0035] It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation to the present application.

[0036] During the invention of this application, it was found that some existing technologies currently use inductively coupled plasma etching to define the active area table, and then use chemical reagents to remove the damaged areas of the GaN semiconductor layer and multi-quantum well layer of the Micro-LED chip, and then deposit an inorganic dielectric layer (such as SiN layer, SiO2 layer) to passivate side wall defects and dangling bonds, and repair etching damage by chemical treatment combined with dielectric passivation to improve the luminous efficiency of the Micro-LED chip. Some existing technologies can directly obtain discrete devices by local selective epitaxy, without the need for table etching, avoiding defect damage introduced during ICP etching.

[0037] At present, plasma bombardment in PECVD (Plasma Enhanced Chemical Vapor Deposition) will inevitably cause secondary contamination damage to the sidewalls, and the performance optimization effect of Micro-LED chips is very limited. In addition, although the selective epitaxy method can effectively avoid the sidewall effect, its epitaxy is extremely difficult and the process yield is low, which increases the manufacturing cost of Micro-LED chips.

[0038] Based on this, the embodiment of the present application provides a Micro-LED chip and its preparation method, and a display device, which directly defines the Micro-LED chip by laser irradiation processing wafers to form a Micro-LED chip array, also known as a pixel array. This technical solution avoids ICP etching damage in the table manufacturing process, and does not need to define the size of a single Micro-LED chip, that is, there is no need to define the size of a single pixel, and there is no need for sidewall passivation process, which can effectively reduce costs and is expected to play a key role in many applications such as ultimate display, visible light communication, and optical interconnect-based memory in the future.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] refer to Figure 1 , Figure 1 A schematic diagram of a process for preparing a Micro-LED chip provided in an embodiment of the present invention. The process for preparing a Micro-LED chip provided in an embodiment of the present invention comprises:

[0041] S101: Figure 2 As shown, a substrate 11 is provided.

[0042] S102: Figure 3 As shown, an epitaxial structure is formed on one side of the substrate 11 , and the epitaxial structure includes an N-type semiconductor layer 12 , a multi-quantum well layer 13 , and a P-type semiconductor layer 14 which are stacked in sequence.

[0043] Specifically, in the embodiment of the present invention, the N-type semiconductor layer 12 is an N-type doped semiconductor layer, and the P-type semiconductor layer 14 is a P-type doped semiconductor layer. For example, the N-type semiconductor layer 12 may be an N-type doped GaN layer, and the P-type semiconductor layer 14 may be a P-type doped GaN layer. It should be noted that in the embodiment of the present invention, only the GaN layer is used as an example of the semiconductor layer for description, and it is obvious that the semiconductor layer may also be a semiconductor layer of other semiconductor materials.

[0044] Among them, the core structure of the Micro-LED chip is a PN junction. When a forward bias is applied to the PN junction, electrons flow from the N-type region to the P-type region, and holes flow from the P-type region to the N-type region. These carriers recombine near the PN junction, release energy and generate photons to emit light. The multi-quantum well layer 13 is a key structure in the Micro-LED chip, and its function is to improve the recombination efficiency and luminescence efficiency of carriers. The multi-quantum well layer 13 is composed of multiple quantum wells (Quantum Well, referred to as QW) and quantum barriers (Quantum Barrier, referred to as QB) alternating. Usually, the band gap width of the quantum well is smaller than the band gap width of the quantum barrier, which causes electrons and holes to be confined in the quantum well under the action of an external electric field, thereby increasing the recombination probability of electrons and holes, and thus improving the luminescence efficiency.

[0045] It should be noted that the epitaxial structure provided in the embodiment of the present invention may further include other functional film layers, for example, a buffer layer located between the substrate 11 and the N-type semiconductor layer 12 .

[0046] S103: Figure 4 As shown, a groove 15 is formed at least penetrating the P-type semiconductor layer 14 and the multi-quantum well layer 13 to expose a portion of the surface of the N-type semiconductor layer 12 .

[0047] Specifically, in the embodiment of the present invention, it includes but is not limited to performing organic cleaning and inorganic cleaning on the structure formed in step S102. The organic cleaning can be placing the structure formed in step S102 in acetone for ultrasonic treatment for about 5 minutes, and then immediately placing it in ethanol for ultrasonic treatment for about 5 minutes after taking it out, and then placing it in deionized water for ultrasonic treatment for about 5 minutes; the inorganic cleaning can be placing the structure formed in step S102 in a solution of H2SO4:H2O2 in a ratio of 7:3 heated on a hot plate at about 105°C for about 20 minutes, and then placing it in deionized water for rinsing after taking it out, and blowing it dry with hot nitrogen.

[0048] After cleaning is completed, the surface of the N-type semiconductor layer 12 to be exposed is defined by using a positive photoresist, including but not limited to the following:

[0049] Place the cleaned structure on a hot plate at about 95°C and bake for 5-10 minutes.

[0050] The cooled structure is placed on a glue spreader for glue coating and glue spread. For example, the glue is coated at a speed of about 800 r / min for about 12 seconds, and the glue is spread at a speed of about 3000 r / min for about 40 seconds. Then, it is placed on a hot plate at about 95°C for soft baking for 4-5 minutes.

[0051] The cooled structure is subjected to an exposure process including but not limited to an exposure process for about 10 seconds using a contact photolithography machine.

[0052] The exposed structure is placed in a developer for 45s-55s, then rinsed in deionized water and dried with nitrogen.

[0053] The structure with the photoresist mask is placed in an ICP chamber and evacuated to below 1E-5 Pa. The main process parameters are: ICP power of about 200 W, RF power of about 100 W, Cl2 / Br2 flow rate of 20 / 20 sccm, chamber pressure of about 10 mTorr, single etching time of 5 min-6 min, and a groove 15 that at least penetrates the P-type semiconductor layer 14 and the multi-quantum well layer 13 is formed. It should be noted that, if Figure 4 As shown, part of the N-type semiconductor layer 12 is also etched in this process.

[0054] Finally, organic cleaning is performed to remove the photoresist to expose a portion of the surface of the N-type semiconductor layer 12 .

[0055] S104: Figure 5 As shown, a patterned dielectric layer 16 is formed on the side of the epitaxial structure away from the substrate 11, and the patterned dielectric layer 16 covers the exposed surface of the N-type semiconductor layer 12 and a portion of the surface of the P-type semiconductor layer 14 away from the substrate 11; the patterned dielectric layer 16 has a plurality of first grooves 17, and the first grooves 17 expose another portion of the surface of the P-type semiconductor layer 14 away from the substrate 11.

[0056] Specifically, in the embodiment of the present invention, it includes but is not limited to using negative photoresist to define the area where the Micro-LED chip needs to be formed and the area of ​​the surface exposed by the N-type semiconductor layer 12. In other words, it includes but is not limited to using negative photoresist to define the pixel area to be formed and the area of ​​the surface exposed by the N-type semiconductor layer 12. That is to say, in the embodiment of the present invention, the area of ​​a Micro-LED chip can be understood as a pixel area, specifically as follows:

[0057] The structure obtained in step S103 is placed on a hot plate at about 100° C. and baked for 5 min-10 min.

[0058] The cooled structure is placed on a glue spreader for glue coating and glue leveling. For example, the glue is coated at a speed of about 600 r / min for about 6 seconds, and the glue is leveled at a speed of about 4000 r / min for about 30 seconds. Then, it is placed on a hot plate at about 100°C for soft baking for 2-3 minutes.

[0059] The cooled structure is subjected to an exposure process including but not limited to an exposure process for about 3 seconds using a contact photolithography machine.

[0060] Then bake it on a hot plate at about 100°C for about 100 seconds. After the structure cools down, use a photolithography machine to expose it for about 40 seconds. Then, put it in a developer for 45s-55s, rinse it in deionized water, and blow it dry with nitrogen.

[0061] The photolithographic structure is placed in an oxygen plasma cleaning machine and oxidized with a bias voltage of about 80W for about 10 minutes to completely oxidize the residual developed glue, and then the oxide is removed with a solution of HCl:H2O in a ratio of 1:5.

[0062] The above structure is placed in a PECVD chamber to deposit a 30nm-50nm silicon oxide film layer; after the deposition is completed, it is placed in a metal evaporator to evaporate a 500nm-1000nm lead layer or tungsten layer on the silicon oxide film layer. In other words, the patterned dielectric layer 16 includes a stacked silicon oxide film layer and a lead layer; the formation of the patterned dielectric layer 16 on the side of the epitaxial structure away from the substrate 11 includes: forming the silicon oxide film layer on the side of the epitaxial structure away from the substrate 11; forming the lead layer on the side of the silicon oxide film layer away from the substrate 11. Or, the patterned dielectric layer 16 includes a stacked silicon oxide film layer and a tungsten layer; the formation of the patterned dielectric layer 16 on the side of the epitaxial structure away from the substrate 11 includes: forming the silicon oxide film layer on the side of the epitaxial structure away from the substrate 11; forming the tungsten layer on the side of the silicon oxide film layer away from the substrate 11.

[0063] The above structure is placed in NMP degumming solution heated to about 85° C. on a hot plate and soaked for about 15-20 minutes to peel off the photoresist and the patterned dielectric layer on the photoresist, and then rinsed with deionized water and blown dry with nitrogen to obtain a structure in which the patterned dielectric layer 16 defines the pixel mesa.

[0064] It should be noted that the design of the high-density metal layer such as the lead layer or the tungsten layer is to prevent the laser from penetrating the silicon oxide film layer and damaging the epitaxial structure of the pixel area in the subsequent process. The epitaxial area corresponding to the P-type semiconductor layer 14 covered by the patterned dielectric layer 16 can be understood as the pixel area mentioned in this article.

[0065] S105: Figure 6 As shown, laser irradiation treatment is performed on one side where the patterned dielectric layer 16 is provided, so that the region of the multi-quantum well layer 13 corresponding to the region where the first groove 17 is located in the first direction loses its luminescence property; the first direction is perpendicular to the plane where the substrate 11 is located.

[0066] Specifically, in the embodiment of the present invention, the structure obtained in step S104 is fixed on a displacement stage so that the laser evenly irradiates the surface of the structure to achieve the definition of the pixel area; then, the pixel area and the patterned dielectric layer 16 on the exposed surface of the N-type semiconductor layer 12 are removed using a BOE solution but is not limited to.

[0067] Exemplarily, the construction of the laser irradiation system in the embodiment of the present invention may include the construction of the laser optical path and the construction of the displacement stage. Among them, the construction of the displacement stage includes assembling the sample stage with the stepping displacement stage for X and Z biaxial movement, the displacement stage is controlled by a microcomputer, the displacement rate is set to about 10mm / s, and the displacement is set to about 100mm; the construction of the laser optical path includes the laser emitted by the laser passing through the collimating beam expander, the beam homogenizer, the cylindrical mirror, the shaping aperture and other optical elements, and then shaping into a longitudinal laser spot, and the longitudinal size of the laser spot is at least greater than the total thickness of the multi-quantum well layer 13 and the P-type semiconductor layer 14. The laser irradiation system constructed is used to perform laser irradiation treatment on the above structure to destroy the multi-quantum well layer 13 outside the defined pixel area. That is to say, when the laser irradiation treatment is performed, the multi-quantum well layer 13 below the area not covered by the patterned dielectric layer 16 will be modified by the laser and lose the luminescence characteristics, while the luminescence characteristics of the multi-quantum well layer 13 below the area covered by the patterned dielectric layer 16 will not be affected, thereby realizing the preparation of the Micro-LED chip. In other words, the laser irradiation wafer processing method is used to directly define the Micro-LED chip to form a Micro-LED chip array, also known as a pixel array. This technical solution avoids the ICP etching damage in the table manufacturing process, and does not need to define the size of a single Micro-LED chip, that is, there is no need to define the size of a single pixel, and there is no need for sidewall passivation process, which can effectively reduce costs and is expected to play a key role in many applications such as ultimate display, visible light communication and optical interconnect-based memory in the future.

[0068] It should be noted that the embodiment of the present invention includes but is not limited to using a high-penetration, high-energy short-wave laser such as an X-ray laser to perform laser irradiation treatment on the side where the patterned dielectric layer 16 is disposed.

[0069] S106: Figure 7 and Figure 8 As shown, the patterned dielectric layer 16 is removed, and an N-electrode 18 and a P-electrode 19 are formed; the N-electrode 18 is connected to the N-type semiconductor layer 12 , and the P-electrode 19 is connected to the P-type semiconductor layer 14 .

[0070] Specifically, in the embodiment of the present invention, the N-electrode 18 is connected to the exposed N-type semiconductor layer 12 , and the P-electrode 19 is connected to the P-type semiconductor layer 14 corresponding to the pixel region.

[0071] The N electrode 18 includes a stacked Ti layer, an Al layer, a Ni layer and an Au layer, wherein the thickness of the Ti layer is about 20nm-40nm, the thickness of the Al layer is about 100nm-300nm, the thickness of the Ni layer is about 10nm-50nm, and the thickness of the Au layer is about 50nm-200nm.

[0072] The P electrode 19 includes a stacked Ni layer and an Ag layer. The thickness of the Ni layer is about 20nm-30nm, and the thickness of the Ag layer is about 50nm-200nm. The P electrode 19 is made of a highly reflective metal, which can effectively improve the light extraction efficiency of the Micro-LED chip.

[0073] In an optional embodiment of the present invention, after the N electrode 18 and the P electrode 19 are prepared, the P electrode 19 and the N electrode 18 may be annealed to improve electrode stability.

[0074] From the above description, it can be seen that the preparation method of the Micro-LED chip provided in the embodiment of the present application does not need to use the traditional ICP table etching process, which prevents the introduction of sidewall etching damage and avoids the size effect. Thanks to the planar configuration of the chip without a "table", it is more conducive to the monolithic integration of the Micro-LED chip and the transistor. In addition, the method of laser irradiation processing of the wafer is used to directly define the Micro-LED chip to form a Micro-LED chip array. The process is simple and can realize the preparation of sub-micron-level devices of Micro-LED chips.

[0075] Based on the above embodiment of the present invention, another embodiment of the present invention further provides a Micro-LED chip, which is obtained by the preparation method of the Micro-LED chip described in the above embodiment. The size of the Micro-LED chip ranges from about 2 μm to 20 μm.

[0076] Based on the above embodiments of the present invention, a display device is provided in another embodiment of the present invention. The display device includes the Micro-LED chip described in the above embodiments.

[0077] The above is a detailed introduction to a Micro-LED chip and its preparation method and display device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0078] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0079] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0080] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a Micro-LED chip, characterized in that: The method for preparing the Micro-LED chip includes: providing a substrate; forming an epitaxial structure on one side of the substrate, the epitaxial structure comprising an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer stacked in sequence; forming a groove at least penetrating the P-type semiconductor layer and the multi-quantum well layer to expose a portion of the surface of the N-type semiconductor layer; A patterned dielectric layer is formed on a side of the epitaxial structure away from the substrate, the patterned dielectric layer covers the exposed surface of the N-type semiconductor layer and a portion of the surface of the P-type semiconductor layer away from the substrate; the patterned dielectric layer has a plurality of first grooves, the first grooves expose another portion of the surface of the P-type semiconductor layer away from the substrate; Performing laser irradiation treatment on a side where the patterned dielectric layer is provided, so that a region of the multi-quantum well layer corresponding to a region where the first groove is located in a first direction loses its luminescence property; the first direction is perpendicular to a plane where the substrate is located; The patterned dielectric layer is removed, and an N electrode and a P electrode are formed; the N electrode is connected to the N-type semiconductor layer, and the P electrode is connected to the P-type semiconductor layer.

2. The method for preparing a Micro-LED chip according to claim 1, characterized in that: The laser irradiation treatment is performed on the side where the patterned dielectric layer is provided, comprising: An X-ray laser is used to perform laser irradiation treatment on the side where the patterned medium layer is disposed.

3. The method for preparing a Micro-LED chip according to claim 1, characterized in that: The patterned dielectric layer includes a stacked silicon oxide film layer and a lead layer; The step of forming a patterned dielectric layer on a side of the epitaxial structure away from the substrate comprises: forming the silicon oxide film layer on a side of the epitaxial structure away from the substrate; The lead layer is formed on a side of the silicon oxide film layer facing away from the substrate.

4. The method for preparing a Micro-LED chip according to claim 1, characterized in that: The patterned dielectric layer includes a stacked silicon oxide film layer and a tungsten layer; The step of forming a patterned dielectric layer on a side of the epitaxial structure away from the substrate comprises: forming the silicon oxide film layer on a side of the epitaxial structure away from the substrate; The tungsten layer is formed on a side of the silicon oxide film layer facing away from the substrate.

5. The method for preparing a Micro-LED chip according to claim 1, characterized in that: The P electrode includes a Ni layer and an Ag layer stacked together.

6. The method for preparing a Micro-LED chip according to claim 1, characterized in that: The N electrode includes a Ti layer, an Al layer, a Ni layer, and an Au layer which are stacked.

7. The method for preparing a Micro-LED chip according to any one of claims 1 to 6, characterized in that: When laser irradiation is performed on the side where the patterned dielectric layer is disposed, the longitudinal dimension of the laser spot is at least greater than the total thickness of the multi-quantum well layer and the P-type semiconductor layer.

8. The method for preparing a Micro-LED chip according to any one of claims 1 to 6, characterized in that: The method for preparing the Micro-LED chip further includes: The P electrode and the N electrode are subjected to an annealing process.

9. A Micro-LED chip, characterized in that: The Micro-LED chip is obtained by the method for preparing a Micro-LED chip according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the Micro-LED chip of claim 9.

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