Channel selection circuit, driving chip, display device and electronic equipment

Abstract

The invention discloses a channel selection circuit, a driving chip, a display device and electronic equipment, the channel selection circuit is formed by cascading at least one two-channel selection module, and the two-channel selection module comprises a decoding unit for receiving a closing signal and a selection signal and generating a first control signal to a third control signal; and the selection unit is connected with the decoding unit and is used for selectively outputting one of the first input signal and the second input signal received by the selection unit according to the first control signal, the second control signal and the third control signal. According to the channel selection circuit provided by the invention, under the condition that only one-bit control register resource (N + 1 bits) is added, the problem that a 2N channel selection circuit cannot be closed during application is solved, the register resource overhead is saved, and the layout wiring density is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a channel selection circuit, a driving chip, a display device, and an electronic device. Background Art

[0002] In digital circuit design, a multiplexer (abbreviated as MUX) is a common logic circuit used to select one signal from multiple input signals and transmit it to an output terminal. Such a circuit plays an important role in data transmission, signal routing, and various digital systems.

[0003] Traditional 2 N channel selection circuits are a specific type of multiplexer that can select one output from 2 N input signals. Such selectors are usually formed by cascading multiple 2-channel selection modules, and each 2-channel selection module is responsible for selecting one from two input signals. In this design, each 2-channel selection module is controlled by a 2-bit selection register and a 1-bit enable register, as Figure 2 shown.

[0004] The selection register is used to determine which input signal is selected. For example, as Figure 2 shown, if the value of the selection register is "10", the first input signal is selected; if the value is "01", the second input signal is selected. The enable register is used to control whether the selection unit 120 operates. When the enable bit (disable signal) is "0", the selection unit 120 allows the signal to pass; when the enable bit is "1", the selection unit 120 does not operate, and no signal will be output at the output terminal.

[0005] In traditional designs, to implement 2 N channel selection, multiple 2-channel selection modules need to be cascaded. For a 2 Figure 1 channel selection circuit composed of traditional 2-channel selection modules without enable as N shown, a total of N-bit selection registers are required; while for a 2 Figure 2 channel selection circuit composed of existing 2-channel selection modules with enable as N shown, a total of 2×N + 1 bits of registers are required (2×N bits for the selection register and 1 bit for the enable register). Therefore, for a 2 N channel selection circuit, a total of N bits of registers or 2×N + 1 bits of registers are required.

[0006] However, for a 2 Figure 1 channel selection circuit composed of traditional 2-channel selection modules without enable as N shown, there are 2 NThe problem that the channel selection circuit cannot be turned off during application; and for the existing 2-channel selection circuit composed of 2-channel selection modules with enable as shown in Figure 2 Although the problem of being unable to be turned off during application is solved, there are still problems of large register resource overhead and dense layout routing. N For the 2-channel selection circuit composed of the existing 2-channel selection modules with enable as shown in SUMMARY OF THE INVENTION

[0007] In view of the above problems, an object of the present invention is to provide a channel selection circuit, a driving chip, a display device and an electronic device. A control register and a selection register are used in the 2-channel selection module, so that in the 2 N channel selection circuit, not only the problem of being unable to be turned off during application can be solved, but also the register resource overhead after large-scale cascading is saved and the layout routing density is reduced.

[0008] According to an aspect of the present invention, a channel selection circuit is provided, which is composed of at least one cascaded 2-channel selection module. The 2-channel selection module includes: a decoding unit that receives a shutdown signal and a selection signal and generates a first control signal to a third control signal; a selection unit connected to the decoding unit, and selectively outputs a first input signal and a second input signal received by the selection unit according to the first control signal to the third control signal.

[0009] Optionally, the decoding unit includes: a first inverter, the input end of the first inverter receives the shutdown signal; a second inverter, the input end of the second inverter receives the selection signal; a first AND gate, the first input end of the first AND gate is connected to the output end of the first inverter, the second input end is connected to the input end of the second inverter to receive the selection signal, and the output end outputs the first control signal; an OR gate, the first input end of the OR gate is connected to the input end of the first inverter to receive the shutdown signal, the second input end is connected to the input end of the second inverter to receive the selection signal, and the output end outputs the second control signal; a second AND gate, the first input end of the second AND gate is connected to the output end of the first inverter, the second input end is connected to the output end of the second inverter, and the output end outputs the third control signal.

[0010] Optionally, the selection unit includes: a third inverter, the input end of the third inverter receives a first input signal, and the control end is connected to the output end of the first AND gate; a fourth inverter, the input end of the fourth inverter is connected to the output end of the third inverter; a fifth inverter, the input end of the fifth inverter is connected to the output end of the fourth inverter, and the control end is connected to the output end of the OR gate; a sixth inverter, the input end of the sixth inverter receives a second input signal, the control end is connected to the output end of the second AND gate, and the output end is connected to the output end of the fifth inverter; a seventh inverter, the input end of the seventh inverter is connected to the output end of the fifth inverter.

[0011] Optionally, the third inverter is turned on or off according to the first control signal, and the third inverter outputs a fixed value when it is turned off.

[0012] Optionally, when the shutdown signal is at a high level, the output signal of the 2-channel selection module is a fixed value, and the fixed value is independent of the first input signal and the second input signal.

[0013] Optionally, in multiple cascaded 2-channel selection modules, the first-level multiple 2-channel selection modules respectively receive the first input signal to the 2 N input signals, and the input signal receiving ends of the multiple 2-channel selection modules in the subsequent level are connected to the output ends of two 2-channel selection modules in the previous level.

[0014] Optionally, multiple cascaded 2-channel selection modules share the shutdown signal and the selection signal.

[0015] According to another aspect of the present invention, a driving chip is provided, which includes the channel selection circuit as described above.

[0016] According to still another aspect of the present invention, a display device is provided, which includes a display panel and the driving chip as described above.

[0017] Optionally, the display panel includes: an LCD display panel, an LED display panel, an OLED display panel, an AMOLED display panel, a Micro OLED display panel, a Micro LED display panel, a Mini LED display panel.

[0018] According to yet another aspect of the present invention, an electronic device is provided, which includes the display device as described above.

[0019] The channel selection circuit, driving chip, display device, and electronic device provided by the present invention have a basic 2-channel selection module composed of multiple inverters. This 2-channel selection module selects between two input signals according to the output signal of the decoder unit. Compared with the traditional 2-channel selection module that only includes a selection register, since a control register is added, the problem that the output signal must be one of the input signals is avoided, thus solving the problem that it cannot be turned off during application. Compared with the traditional 2-channel selection module that includes two selection registers and one control register, one selection register is reduced. Therefore, in the 2-channel selection circuit after large-scale cascading, the register resource overhead is greatly reduced and the layout routing density is decreased. N In the channel selection circuit, the register resource overhead is greatly reduced and the layout routing density is decreased. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings: Figure 1 FIG. 10 shows a structural diagram of a 2-channel selection module according to the prior art; Figure 2 FIG. 13 shows a structural diagram of another 2-channel selection module according to the prior art; Figure 3 FIG. 16 shows a structural diagram of a 2-channel selection module according to an embodiment of the present invention; Figure 4 FIG. 19 shows a 2-channel selection circuit according to an embodiment of the present invention; N FIG. 21 shows a structural diagram of the 2-channel selection circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0022] The following will further describe in detail the specific embodiments of the present invention in conjunction with the drawings and embodiments.

[0023] Figure 1 FIG. 33 shows a structural diagram of a 2-channel selection module according to the prior art; Figure 2 FIG. 35 shows a structural diagram of another 2-channel selection module according to the prior art.

[0024] Reference Figure 1, a traditional 2-channel selection module without an enable function includes an eighth inverter INV8, a ninth inverter INV9, and a tenth inverter INV10. The control terminal of the eighth inverter INV8 is connected to the input terminal of the first selection signal SEL, and the input terminal receives the first input signal IN_A; the control terminal of the ninth inverter INV9 is connected to the input terminal of the second selection signal SELB, the input terminal receives the first input signal IN_A, and the output terminal is connected to the output terminal of the eighth inverter INV8; the input terminal of the tenth inverter INV10 is connected to the output terminal of the eighth inverter INV8, and the output terminal is the output terminal of the 2-channel selection module. Among them, the first selection signal SEL and the second selection signal SELB are reverse signals to each other.

[0025] In this circuit, since only one of the two input signals can be selected for output at the output terminal during operation, there is a problem that the circuit cannot be turned off.

[0026] Reference Figure 2 , another traditional 2-channel selection module 100 with an enable bit includes a decoding unit 110 and a selection unit 120 connected to the decoding unit 110.

[0027] Among them, the decoding unit 110 includes an eleventh inverter INV11, a third AND gate AND3, and a fourth AND gate AND4. Specifically, the input terminal of the eleventh inverter INV11 receives the shutdown signal PD; the first input terminal of the third AND gate AND3 is connected to the first selection signal SEL_A, and the second input terminal is connected to the output terminal of the eleventh inverter INV11; the first input terminal of the fourth AND gate AND4 is connected to the output terminal of the eleventh inverter INV11, and the second input terminal is connected to the second selection signal SEL_B.

[0028] The selection unit 120 includes a transistor M1, a twelfth inverter INV12, a thirteenth inverter INV13, and a fourteenth inverter INV14. The first terminal of the transistor M1 is connected to the ground terminal GND or the power supply voltage VCC, and the control terminal is connected to the output terminal of the eleventh inverter INV11 in the decoding unit 110; the control terminal of the twelfth inverter INV12 is connected to the output terminal of the third AND gate AND3, the input terminal receives the first input signal IN_A, and the output terminal is connected to the second terminal of the transistor M1; the control terminal of the thirteenth inverter INV13 is connected to the output terminal of the fourth AND gate AND4, the input terminal receives the second input signal IN_B, and the output terminal is connected to the output terminal of the twelfth inverter INV12; the input terminal of the fourteenth inverter INV14 is connected to the output terminal of the twelfth inverter INV12, and its output terminal is the output terminal of the 2-channel selection module 100.

[0029] Among them, this Figure 2In the shown 2-channel selection module 100, it includes an enable register and two selection registers. Therefore, in the 2-channel selection circuit composed of large-scale cascading of the 2-channel selection module 100, there are problems of large register resource overhead and dense layout routing. N In the 2-channel selection circuit, there are problems of large register resource overhead and dense layout routing.

[0030] Figure 3 The structure diagram of the 2-channel selection module according to an embodiment of the present invention is shown.

[0031] Reference Figure 3 , the 2-channel selection module 200 of the present application includes a decoding unit 210 and a selection unit 220 connected to the decoding unit 210.

[0032] Among them, the decoding unit 210 includes: a first inverter INV1, a second inverter INV2, a first AND gate AND1, an OR gate OR, and a second AND gate AND2. The input end of the first inverter INV1 receives the shutdown signal PD; the input end of the second inverter INV2 receives the selection signal SEL; the first input end of the first AND gate AND1 is connected to the output end of the first inverter INV1, and the second input end is connected to the input end of the second inverter INV2 to receive the selection signal SEL; the first input end of the OR gate is connected to the input end of the first inverter INV1 to receive the shutdown signal PD, and the second input end is connected to the input end of the second inverter INV2 to receive the selection signal SEL; the first input end of the second AND gate AND2 is connected to the output end of the first inverter INV1, and the second input end is connected to the output end of the second inverter INV2.

[0033] The selection unit 220 includes a third inverter INV3_PD, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7. The input end of the third inverter INV3_PD receives the first input signal IN_A, and the control end is connected to the output end of the first AND gate AND1 in the decoding unit 210; the input end of the fourth inverter INV4 is connected to the output end of the third inverter INV3_PD; the input end of the fifth inverter INV5 is connected to the output end of the fourth inverter INV4, and the control end is connected to the output end of the OR gate OR in the decoding unit 210; the input end of the sixth inverter INV6 receives the second input signal IN_B, the control end is connected to the output end of the second AND gate AND2 in the decoding unit 210, and the output end is connected to the output end of the fifth inverter INV5; the input end of the seventh inverter INV7 is connected to the output end of the fifth inverter INV5.

[0034] In this embodiment, among the three control signals output by the decoding unit 210 according to the shutdown signal PD and the selection signal SEL, the first AND gate AND1 outputs a first control signal EN_A, which is used to control the signal output from the input end of the third inverter INV3_PD to be the first input signal IN_A or a fixed value (for example, 1 or 0); the OR gate OR outputs a second control signal SEL_A, which is used to control the signal received by the input end of the fifth inverter INV5 to reach the output end and be output; the second AND gate AND2 outputs a third control signal SEL_B, which is used to control the signal received by the input end of the fifth inverter INV5 to reach the output end and be output.

[0035] Among them, the third inverter INV3_PD is a special inverter. The difference from the fifth inverter INV5 and the sixth inverter INV6 is that when the first control signal EN_A received by the control end of the third inverter INV3_PD is at a low level and the third inverter INV3_PD is turned off, the third inverter INV3_PD outputs a fixed value (for example, 1 or 0); and when the second control signal SEL_A or the third control signal SEL_B received by the control end of the fifth inverter INV5 or the sixth inverter INV6 is at a low level, the output end of the fifth inverter INV5 or the sixth inverter INV6 is in a high impedance state.

[0036] Specifically, the decoding logic of the decoding unit 210 is shown in the following table.

[0037] Table 1: Decoding Logic of the Decoding Unit Internal logic PD = 1; SEL = x PD = 0; SEL = 1 PD = 0; SEL = 0 EN_A 0 1 0 SEL_A 1 1 0 SEL_B 0 0 1

[0038] Referring to the above table and Figure 3 , in one embodiment, when the shutdown signal PD at the shutdown end of the 2-channel selection module 200 is at a high level, both the first control signal EN_A output by the first AND gate AND1 and the third control signal SEL_B output by the second AND gate AND2 are at a low level. At this time, the sixth inverter INV6 does not work, and the third inverter INV3_PD outputs a fixed value of low level, so that the output end of the 2-channel selection module 200 is not affected by the selection signal SEL, and the output signal remains at a high level and is not related to the first input signal IN_A and the second input signal IN_B.

[0039] When the shutdown signal PD is at a low level, if the selection signal SEL is at a high level, then the first control signal EN_A and the second control signal SEL_A are at a high level, the third control signal SEL_B is at a low level, the third inverter INV3_PD and the fifth inverter INV5 are turned on, and the sixth inverter INV6 is turned off. Thus, the output end of the 2-channel selection module 200 is the first input signal IN_A.

[0040] When the shutdown signal PD is at a low level, if the selection signal SEL is at a low level, the first control signal EN_A and the second control signal SEL_A are at low levels, the third control signal SEL_B is at a high level, the third inverter INV3_PD outputs a fixed value, the fifth inverter INV5 is turned off, and the sixth inverter INV6 is turned on, so that the output terminal of the 2-channel selection module 200 is the second input signal IN_B.

[0041] Furthermore, Figure 4 shows the structural diagram of the 2 N -channel selection circuit according to an embodiment of the present invention. Among them, the 2 N -channel selection circuit is composed of a plurality of cascaded 2-channel selection modules 200.

[0042] Refer to Figure 4 , in the 2 N -channel selection circuit, among the multiple cascaded 2-channel selection modules 200, each 2-channel selection module 200 is regarded as a whole, so that each 2-channel selection module 200 includes four inputs and one output. The first input terminal receives the shutdown signal PD, the second input terminal receives the selection signal SEL, the third input terminal receives the first input signal IN_A, and the fourth input terminal receives the second input signal IN_B.

[0043] For the 2 N -channel selection circuit, multiple 2-channel selection modules 200 share the shutdown signal PD and the selection signal SEL, and the multiple 2-channel selection modules 200 at the first stage respectively receive the first input signal to the 2 N -th input signal. The first input signal terminals and the second input signal terminals of the multiple 2-channel selection modules 200 at the second stage are connected to the output terminals of two 2-channel selection modules 200 at the first stage for re-selection among the first-stage output signals. The multiple 2-channel selection modules 200 at the third stage select from the output signals of the second-stage 2-channel selection modules 200, and so on for each stage until the last stage only includes one 2-channel selection module 200.

[0044] In one embodiment, for example, N = 2, it is a 4-channel selection circuit, which is composed of three cascaded 2-channel selection modules 200. The first stage includes the first 2-channel selection module and the second 2-channel selection module, the second stage includes the third 2-channel selection module, and the three 2-channel selection modules share the shutdown signal PD and the selection signal SEL. The first 2-channel selection module also receives the first input signal IN_1 and the second input signal IN_2, the second 2-channel selection module also receives the third input signal IN_3 and the fourth input signal IN_4, and the third 2-channel selection module is connected to the output terminals of the first 2-channel selection module and the second 2-channel selection module.

[0045] When the close signal PD is at a low level and the select signal SEL is "11", the signal received by the third input terminal is output by a single 2-channel selection module. Then, the first 2-channel selection module outputs the first input signal IN_1, the second 2-channel selection module outputs the third input signal IN_3, and the third 2-channel selection module outputs the first input signal IN_1 among the first input signal IN_1 and the third input signal IN_3, thus achieving the purpose of selecting one output from four input channels.

[0046] For the 2 N channel selection circuit (N>2), its principle is the same as that of the 4-channel selection circuit, and it can achieve the purpose of selecting one output from 2 N (N>2) input channels.

[0047] Furthermore, the present application also provides a driving chip, which includes the channel selection circuit as described above.

[0048] Furthermore, the present application also provides a display device, which includes a display panel and the driving chip as described above. The display panel includes: LCD display panel, LED display panel, OLED display panel, AMOLED display panel, Micro OLED display panel, Micro LED display panel, Mini LED display panel, etc.

[0049] Furthermore, the present application also provides an electronic device, which includes the display device as described above.

[0050] The channel selection circuit, driving chip, display device, and electronic device provided by the present invention have the most basic 2-channel selection module composed of multiple inverters. This 2-channel selection module selects between two input signals according to the output signal of the decoder unit. Compared with the traditional 2-channel selection module that only includes a selection register, since a control register is added, the problem that the signal at the output terminal must be one of the input signals is avoided, thus solving the problem that it cannot be turned off during application. Compared with the traditional 2-channel selection module that includes two selection registers and one control register, one selection register is reduced. Therefore, in the 2 N channel selection circuit after large-scale cascading, the register resource overhead is greatly reduced and the layout wiring density is reduced.

[0051] As described above with reference to the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A channel selection circuit, comprising at least one cascade of two channel selection modules, wherein: 2-channel selection module includes: A decoding unit, receiving a shutdown signal and a selection signal and generating a first control signal to a third control signal; The selection unit is connected to the decoding unit, and selects and outputs one of the first input signal and the second input signal received by the selection unit according to the first control signal to the third control signal.

2. The channel selection circuit according to claim 1, wherein: The decoding unit comprises: A first inverter, an input terminal of which receives a shutdown signal; a second inverter, wherein an input terminal of the second inverter receives a selection signal; A first AND gate, wherein a first input terminal of the first AND gate is connected to the output terminal of the first inverter, a second input terminal of the first AND gate is connected to the input terminal of the second inverter to receive the selection signal, and an output terminal of the first AND gate outputs a first control signal; An OR gate, wherein a first input terminal of the OR gate is connected to an input terminal of the first inverter to receive the shutdown signal, a second input terminal of the OR gate is connected to an input terminal of the second inverter to receive the selection signal, and an output terminal of the OR gate outputs a second control signal; A second AND gate, wherein a first input terminal of the second AND gate is connected to the output terminal of the first inverter, a second input terminal is connected to the output terminal of the second inverter, and an output terminal outputs a third control signal.

3. The channel selection circuit according to claim 2, wherein: The selection unit comprises: A third inverter, wherein an input terminal of the third inverter receives a first input signal, and a control terminal of the third inverter is connected to an output terminal of the first AND gate; a fourth inverter, wherein an input terminal of the fourth inverter is connected to an output terminal of the third inverter; a fifth inverter, wherein an input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, and a control terminal of the fifth inverter is connected to the output terminal of the OR gate; a sixth inverter, wherein an input terminal of the sixth inverter receives a second input signal, a control terminal is connected to an output terminal of the second AND gate, and an output terminal is connected to an output terminal of the fifth inverter; A seventh inverter, wherein an input terminal of the seventh inverter is connected to an output terminal of the fifth inverter.

4. The channel selection circuit according to claim 3, wherein: The third inverter is turned on or off according to the first control signal, and the third inverter outputs a fixed value when turned off.

5. The channel selection circuit according to claim 4, wherein: When the shutdown signal is at a high level, the output signal of the 2-channel selection module is a fixed value, and the fixed value is independent of the first input signal and the second input signal.

6. The channel selection circuit according to claim 1, wherein: In the plurality of cascaded 2-channel selection modules, the plurality of 2-channel selection modules in the first stage receive the first input signal to the second N The input signal receiving ends of the multiple 2-channel selection modules of the next stage are connected to the output ends of the two 2-channel selection modules of the previous stage, and so on for each stage.

7. The channel selection circuit according to claim 6, wherein: A plurality of cascaded 2-channel selection modules share the shutdown signal and the selection signal.

8. A driver chip, wherein: The method comprises the channel selection circuit as claimed in any one of claims 1 to 7.

9. A display device, wherein: The device comprises a display panel and a driving chip as claimed in claim 8.

10. The display device according to claim 9, wherein: The display panels include: LCD display panel, LED display panel, OLED display panel, AMOLED display panel, Micro OLED display panel, Micro LED display panel, and MiniLED display panel.

11. An electronic device, wherein: Comprising the display device as claimed in claim 9 or 10.

Images