Video processing method and device, equipment, storage medium and program product

Abstract

The invention relates to a video processing method applied to a processor of computer equipment. The computer equipment further comprises an acquisition unit, a memory unit, a blocking unit and a coding unit; the memory unit comprises a pre-allocated cache space; the method comprises the following steps: under the condition that an acquisition unit circularly fills acquired source video data into a cache space in a row filling manner, receiving a row interruption instruction which is triggered and generated after the acquisition unit finishes filling the cache space; in response to the row interrupt instruction, updating a first cache address of the cache space to a blocking unit; and after the blocking unit receives the data reading request sent by the coding unit and judges that the data reading request is released based on the first cache address and a second cache address carried by the data reading request, reading the source video data from the cache space based on the first cache address, and coding the read source video data through the coding unit. By adopting the method, the memory occupation and the coding delay can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a video processing method, apparatus, device, storage medium, and program product. Background Art

[0002] In application scenarios such as security monitoring or consumer cameras, a collection device receives video images from a camera and stores them in memory, and then an encoding device reads the video images from the memory for video encoding. The encoded video is transmitted to a cloud or a terminal such as a mobile phone for viewing or storage through a networking method such as WIFI or Ethernet. In traditional video processing solutions, the processing method for video data transfer between the collection device and the encoding device mainly uses a frame buffer method for interaction. That is, after the collection device stores a complete frame of image in the video in the memory, the encoding device starts to read and encode the frame of image. While the encoding device is encoding, the collection device stores the next frame of image in another space of the memory. The collection device and the encoding device achieve the collection and encoding processing of the video stream through the ping-pong operation of two frame buffer spaces.

[0003] However, although the software and hardware interaction control and implementation method of the traditional video processing method are simple, this video processing method requires at least two frame buffer memory spaces, resulting in a large memory occupation. In addition, the video encoding of this video processing method needs to be performed at the granularity of each frame of image, resulting in a large delay in video encoding. Summary of the Invention

[0004] Based on this, it is necessary to provide a video processing method, apparatus, device, storage medium, and program product that can reduce memory occupation and encoding delay for the above technical problems.

[0005] In a first aspect, this application provides a video processing method, which is applied to a processor of a computer device; the computer device further includes a collection unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes a pre-allocated cache space; the method includes:

[0006] When the collection unit fills the cache space in a cyclic manner with the collected source video data in a row-by-row filling manner, receiving a row interrupt instruction generated by the collection unit each time after the cache space is filled;

[0007] In response to the row interrupt instruction, updating a first cache address of the cache space to the blocking unit;

[0008] After the blocking unit receives the data reading request sent by the encoding unit, and determines to release the data reading request based on the first cache address and the second cache address carried in the data reading request, it reads the source video data from the cache space based on the first cache address, and encodes the read source video data through the encoding unit.

[0009] In a second aspect, the present application provides a video processing device, which is applied to a processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes a pre-allocated cache space; the device includes:

[0010] A receiving module, configured to receive a line interruption instruction generated by the acquisition unit each time after the acquisition unit fills the cache space in a row-by-row filling manner with the acquired source video data.

[0011] An updating module, configured to update the first cache address of the cache space to the blocking unit in response to the line interruption instruction.

[0012] A reading module, configured to, after the blocking unit receives the data reading request sent by the encoding unit, and determines to release the data reading request based on the first cache address and the second cache address carried in the data reading request, read the source video data from the cache space based on the first cache address, and encode the read source video data through the encoding unit.

[0013] In a third aspect, the present application provides a video processing system, the system includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes a pre-allocated cache space;

[0014] The acquisition unit is configured to fill the cache space with the acquired source video data in a row-by-row filling manner, and trigger a line interruption instruction each time after the cache space is filled.

[0015] The processor is configured to receive the line interruption instruction, and in response to the line interruption instruction, update the first cache address of the cache space to the blocking unit.

[0016] The blocking unit is configured to receive the data reading request sent by the encoding unit, and determine whether to release the data reading request based on the first cache address and the second cache address carried in the data reading request.

[0017] The processor is further configured to read the source video data from the cache space based on the first cache address.

[0018] The encoding unit is used to encode the read source video data.

[0019] In a fourth aspect, the present application provides a computer device, including a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit; a cache space is pre-allocated in the memory unit; a computer program is stored in the memory unit, and when the processor executes the computer program, the steps in the method embodiments of the present application are implemented.

[0020] In a fifth aspect, the present application provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in the method embodiments of the present application are implemented.

[0021] In a sixth aspect, the present application provides a computer program product including a computer program, and when the computer program is executed by a processor, the steps in the method embodiments of the present application are implemented.

[0022] For the above video processing method, device, equipment, storage medium, and program product, the computer device includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. When the acquisition unit fills the cache space in a cyclic manner by row filling the acquired source video data, the processor receives a row interruption instruction generated by the acquisition unit each time after the cache space is filled; in response to the row interruption instruction, the processor updates the first cache address of the cache space to the blocking unit; after the blocking unit receives a data reading request sent by the encoding unit and determines to release the data reading request based on the first cache address and the second cache address carried in the data reading request, the processor reads the source video data from the cache space based on the first cache address and encodes the read source video data through the encoding unit. Compared with the traditional video processing method, in the present application, the acquisition unit fills the cache space in a cyclic manner by row filling the acquired source video data, and the acquisition unit generates a row interruption instruction each time after the cache space is filled, so that the amount of source video data cached in the cache space can be less than the amount of data of one frame of image. Furthermore, the processor updates the first cache address of the cache space with the prepared source video data to the blocking unit, so that the blocking unit determines whether to release the data reading request based on the first cache address and the second cache address carried in the data reading request sent by the encoding unit. After determining to release the data reading request, the source video data can be read from the cache space and the read source video data can be encoded through the encoding unit, which can reduce the memory occupation in the video processing process, reduce the encoding delay of the video, and improve the video processing efficiency and real-time performance. Description of the Drawings

[0023] Figure 1 It is a schematic flowchart of a video processing method in an embodiment;

[0024] Figure 2 Schematic diagram of the working principle of the blocking unit in an embodiment;

[0025] Figure 3 Cyclic schematic diagram of cache spaces with different quantities and capacities in an embodiment;

[0026] Figure 4 Cyclic schematic diagram of two cache spaces with different capacities in an embodiment;

[0027] Figure 5 Schematic structural diagram of a video processing system in an embodiment;

[0028] Figure 6 Block diagram of the structure of a video processing device in an embodiment;

[0029] Figure 7 Internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0031] In an embodiment, as Figure 1 shown, a video processing method is provided, which is applied to the processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit and an encoding unit; the memory unit includes pre-allocated cache spaces; the method includes the following steps:

[0032] Step 102, when the acquisition unit fills the cache space cyclically in a row filling manner with the acquired source video data, receive the row interruption instruction generated by the acquisition unit each time after the filling of the cache space is completed.

[0033] Among them, the source video data contains multiple frames of images, and each frame of image contains multiple rows of image data, that is, multiple rows of pixel data. For example, a frame of image with a resolution of 1920×1080 in the source video data contains 1920 rows of image data. Filling the cache space cyclically in a row-by-row manner for the source video data means filling the cache space cyclically for each frame of image in the source video data with the row image data as the granularity. It can be understood that the cache capacity of the cache space is smaller than the cache capacity occupied by one frame of image. Cyclically filling the cache space means that after the cache space is filled, the source video data is cyclically filled into the cache space again, and the source video data filled in each cycle can directly overwrite the source video data filled in the previous cycle. The row interruption instruction is a computer instruction used to indicate that the cache space currently being written by the acquisition unit is full and temporarily stop writing the source video data to this cache space continuously.

[0034] In one embodiment, the computer device further includes a camera, and the acquisition unit can receive the source video data sent by the camera in real time and fill the cache space cyclically in a row-by-row manner for the acquired source video data. Whenever the acquisition unit finishes filling a cache space, it can trigger the generation of a row interruption instruction and send the row interruption instruction to the processor, and the processor can receive this row interruption instruction.

[0035] In one embodiment, the memory unit includes at least one pre-allocated cache space. When the acquisition unit fills these cache spaces cyclically in a row-by-row manner for the acquired source video data, for each cache space, the processor can receive the row interruption instruction generated by the acquisition unit for this cache space whenever it finishes filling this cache space.

[0036] In one embodiment, the processor, acquisition unit, memory unit, blocking unit, and encoding unit in the computer device are all hardware devices. The processor can be a central processing unit, the acquisition unit can be a video collector, the memory unit can be an internal memory, the blocking unit can be a hardware logic circuit, and the encoding unit can be a video encoder.

[0037] Step 104, in response to the row interruption instruction, update the first cache address of the cache space to the blocking unit.

[0038] Among them, the first cache address of the cache space is the physical address of the cache space in the memory unit.

[0039] Specifically, in response to a line interruption instruction, the processor may update the first cache address of the cache space to the blocking unit, and the blocking unit may record the first cache address. It can be understood that if the first cache address of the cache space is recorded in the blocking unit, it indicates that the cache space is full, the data writing of the acquisition unit for this cache space has been interrupted, and the source video data to be encoded has been prepared in this cache space.

[0040] Step 106, after the blocking unit receives the data reading request sent by the encoding unit, and based on the first cache address and the second cache address carried in the data reading request, determines to release the data reading request, reads the source video data from the cache space based on the first cache address, and encodes the read source video data through the encoding unit.

[0041] Specifically, the blocking unit may receive the data reading request sent by the encoding unit in real time, where the second cache address corresponding to the source video data to be encoded is carried in the data reading request. The blocking unit may determine whether to release the data reading request based on the first cache address recorded in the blocking unit and the second cache address carried in the data reading request. After the blocking unit determines to release the data reading request, the processor may read the source video data from the cache space indicated by the first cache address, and encode the read source video data through the encoding unit.

[0042] In one embodiment, the encoding unit sequentially reads the source video data in the memory unit in a frame cache manner. Therefore, the encoding unit first generates the frame cache address corresponding to the source video data to be encoded, that is, the virtual address of the cache space. The encoding unit then converts the virtual address of the cache space into the real physical address of the cache space in the memory unit, and attaches the real physical address of the cache space to the data reading request corresponding to the source video data to be encoded. It can be understood that in this embodiment, the function of address conversion is implemented by the encoding unit. Furthermore, the blocking unit can directly perform a consistency comparison between the first cache address recorded in the blocking unit and the second cache address (i.e., the real physical address of the cache space) carried in the data reading request. If the second cache address is consistent with the first cache address, the blocking unit may determine to release the data reading request. If the second cache address is inconsistent with the first cache address, the blocking unit may determine to block the data reading request.

[0043] In the above video processing method, the computer device includes a processor, a collection unit, a memory unit, a blocking unit, and an encoding unit. When the collection unit fills the cache space in a cyclic manner with the collected source video data in a line-by-line filling manner, the processor receives a line interruption instruction generated by the collection unit each time after the cache space is filled; in response to the line interruption instruction, the processor updates the first cache address of the cache space to the blocking unit; after the blocking unit receives a data reading request sent by the encoding unit and determines to release the data reading request based on the first cache address and the second cache address carried in the data reading request, the processor reads the source video data from the cache space based on the first cache address and encodes the read source video data through the encoding unit. Compared with the traditional video processing method, in this application, the collection unit fills the cache space in a cyclic manner with the collected source video data in a line-by-line filling manner, and the collection unit generates a line interruption instruction each time after the cache space is filled, so that the amount of source video data cached in the cache space can be less than the amount of data of one frame of image. Then, the processor updates the first cache address of the cache space with the prepared source video data to the blocking unit, so that the blocking unit determines whether to release the data reading request based on the first cache address and the second cache address carried in the data reading request sent by the encoding unit. After determining to release the data reading request, the source video data can be read from the cache space, and the read source video data is encoded through the encoding unit, which can reduce the memory occupation in the video processing process, reduce the encoding delay of the video, and improve the video processing efficiency and real-time performance.

[0044] In addition, compared with the traditional hardware processing logic of using a hardware device, i.e., the blocking unit, to calculate the cache addresses of the collection unit and the encoding unit accessing the circular cache space and then perform the empty / full judgment processing of the cache space, in this application, the processor updates the cache address of the cache space with the prepared source video data to the blocking unit in a software management manner to perform the empty / full judgment of the cache space. By replacing the traditional way of controlling the cache address update through the hardware processing logic in the blocking unit with this software management method, the hardware structure design of the blocking unit can be simplified, and the control logic of the cache address update can be simplified.

[0045] In one embodiment, the second cache address is the virtual address for the encoding unit to sequentially read the source video data in a frame caching manner; the step of the blocking unit determining to release the data reading request based on the first cache address and the second cache address carried in the data reading request includes: the blocking unit performs address conversion on the second cache address carried in the data reading request to obtain a third cache address, and if the first cache address is the same as the third cache address, it determines to release the data reading request.

[0046] Among them, the second cache address is the virtual address for the coding unit to sequentially read the source video data in the frame cache manner. It can be understood that the second cache address is not the actual physical address of the cache space in the memory unit.

[0047] In one embodiment, the coding unit sequentially reads the source video data in the memory unit in the frame cache manner. Therefore, the coding unit generates a frame cache address corresponding to the source video data to be encoded, that is, the virtual address of the cache space, which is also the second cache address. The coding unit can attach the second cache address to the data read request corresponding to the source video data to be encoded. It can be understood that in this embodiment, the function of address conversion is implemented by the blocking unit. Furthermore, as Figure 2 shown, the blocking unit can perform address conversion on the second cache address carried in the data read request to obtain a third cache address. It can be understood that the third cache address obtained after address conversion is the actual physical address of the cache space in the memory unit. The blocking unit can compare the first cache address updated to the blocking unit by the processor with the third cache address obtained after address conversion. If the first cache address and the third cache address are the same, it is determined to release the data read request. If the first cache address and the third cache address are different, it is determined to block the data read request.

[0048] In the above embodiment, compared with the traditional method of performing address conversion in the coding unit, in this embodiment, the function of address conversion is transferred to the blocking unit, so that the coding unit can directly read the source video data in the original frame cache manner without modifying the hardware structure and hardware processing logic, simplifying the design of the coding unit, thereby improving the video coding performance.

[0049] In one embodiment, the blocking unit contains cache allocation information corresponding to the cache space; the cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address; the step of the blocking unit performing address conversion on the second cache address carried in the data read request to obtain a third cache address includes: the blocking unit performing address conversion on the second cache address carried in the data read request based on the cache allocation information to obtain a third cache address.

[0050] Specifically, when the processor allocates cache space in the memory unit, it can generate cache allocation information corresponding to the cache space. The cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address. The processor can pre-configure the cache allocation information to the acquisition unit and the blocking unit, and both the acquisition unit and the blocking unit contain the cache allocation information corresponding to the cache space. It can be understood that the acquisition unit can cyclically fill the source video data into the cache space corresponding to the memory unit based on the cache allocation information. The blocking unit can perform address mapping based on the cache allocation information, that is, convert the virtual second cache address carried in the data read request to obtain the real third cache address of the cache space.

[0051] In the above embodiment, by the blocking unit performing address conversion on the second cache address carried in the data read request based on the cache allocation information to obtain the third cache address, the accuracy of address conversion can be improved, thereby improving the video encoding efficiency.

[0052] In one embodiment, the number of cache spaces included in the memory unit is multiple; the cache capacity of each cache space is obtained by custom configuration; when the acquisition unit cyclically fills the acquired source video data into the cache space in a row-by-row filling manner, receiving the row interruption instruction generated by the acquisition unit each time after the filling of the cache space is completed, includes: when the acquisition unit cyclically fills the acquired source video data into multiple cache spaces one by one in a row-by-row filling manner, for each cache space, receiving the row interruption instruction for the cache space generated by the acquisition unit each time after the filling of the cache space is completed.

[0053] Specifically, the memory unit contains multiple pre-allocated cache spaces, and the cache capacity of each cache space is obtained by custom configuration, that is, the size (i.e., cache capacity) and number of cache spaces support flexible configuration. When the acquisition unit cyclically fills the acquired source video data into multiple cache spaces one by one in a row-by-row filling manner, for each cache space, the processor can receive the row interruption instruction for the cache space generated by the acquisition unit each time after the filling of the cache space is completed. In response to the row interruption instruction, the processor can update the first cache address of the cache space to the blocking unit. After the blocking unit receives the data read request sent by the encoding unit and determines to release the data read request based on the first cache address and the second cache address carried in the data read request, the processor can read the source video data from the cache space based on the first cache address and encode the read source video data through the encoding unit.

[0054] In one embodiment, the size (i.e., cache capacity) and number of cache spaces in the memory unit support flexible configuration. For example, Figure 3As shown in the figure, two cache spaces 1 and 2 with different cache capacities can be set in the memory unit, or three cache spaces 1, 2, and 3 with different cache capacities can be set, or four cache spaces 1, 2, 3, and 4 with different cache capacities can be set. It should be noted that the cache capacities of multiple cache spaces set in the memory unit can be the same or different.

[0055] In one embodiment, as Figure 4 shown, a cache space 1 with a cache capacity of N1 and a cache space 2 with a cache capacity of N2 can be set in the memory unit. It can be understood that the cache space 1 can store N1 rows of source video data, and the cache space 2 can store N2 rows of source video data. Then, when the acquisition unit uploads N1 rows of source video data (the 1st row to the N1th row) to the cache space 1, a line interrupt instruction can be triggered to be generated. When N2 rows of source video data (the (N1 + 1)th row to the (N1 + N2)th row) are uploaded to the cache space 2, a line interrupt instruction can be triggered to be generated. The next N1 rows are uploaded to the cache space 1 and a line interrupt instruction is triggered to be generated. The access process of these two cache spaces proceeds in such a cycle.

[0056] In the above embodiment, by flexibly configuring multiple cache spaces with the same or different cache capacities in the memory unit, the size and quantity of the cache spaces support flexible configuration. The processor can manage the cache spaces more flexibly through software management, and the fragmented storage space in the memory unit can also be utilized more reasonably, thereby improving the memory utilization rate.

[0057] In one embodiment, the computer device further includes a camera; the step of the acquisition unit circularly filling the cache space with the acquired source video data in a line-by-line manner includes:

[0058] The acquisition unit receives the original source video data sent by the camera in real time, optimizes the original source video data to obtain the source video data, and circularly fills the cache space with the source video data in a line-by-line manner.

[0059] Specifically, the computer device includes a processor, a camera, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. Among them, the memory unit contains a pre-allocated cache space. The acquisition unit can receive the original source video data sent by the camera in real time, perform video quality optimization processing on the original source video data to obtain the source video data, and circularly fill the optimized source video data into the cache space in a row filling manner. Whenever the acquisition unit finishes filling the cache space, it can trigger the generation of a line interrupt instruction. The processor can receive the line interrupt instruction and, in response to the line interrupt instruction, update the first cache address of the cache space to the blocking unit. After the blocking unit receives the data reading request sent by the encoding unit and determines to release the data reading request based on the first cache address and the second cache address carried in the data reading request, the processor can read the source video data from the cache space based on the first cache address and encode the read source video data through the encoding unit.

[0060] In the above embodiment, before writing the video data into the cache space, the acquisition unit can first optimize the image quality of the video data, so as to improve the quality of the subsequent encoded video.

[0061] It should be understood that although the steps in the flowcharts of the above embodiments are shown in sequence, these steps are not necessarily executed in sequence. Unless there is a clear description in this article, the execution of these steps has no strict sequence limit, and these steps can be executed in other sequences. Moreover, at least a part of the steps in the above embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0062] In one embodiment, as Figure 5 shown, a video processing system is provided. The system includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit contains a pre-allocated cache space;

[0063] An acquisition unit, configured to circularly fill the acquired source video data into the cache space in a row filling manner, and trigger the generation of a line interrupt instruction whenever the cache space is filled;

[0064] A processor, configured to receive the line interrupt instruction and, in response to the line interrupt instruction, update the first cache address of the cache space to the blocking unit;

[0065] A blocking unit, configured to receive a data reading request sent by an encoding unit, and determine whether to allow the data reading request based on a first cache address and a second cache address carried in the data reading request;

[0066] The processor is further configured to read source video data from the cache space based on the first cache address;

[0067] An encoding unit, configured to encode the read source video data.

[0068] In one embodiment, continue to refer to Figure 5 , in addition to a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit, the video processing system may further include a camera. Specifically, the acquisition unit can receive the source video data acquired by the camera in real time. And, after encoding the read source video data, the encoding unit can store the encoded video data in the memory unit.

[0069] In one embodiment, as Figure 6 shown, a video processing device 600 is provided, which is applied to a processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes a pre-allocated cache space; the device specifically includes:

[0070] A receiving module 602, configured to receive a line interrupt instruction generated by the acquisition unit each time after completing the filling of the cache space when the acquisition unit fills the cache space in a row filling manner with the acquired source video data;

[0071] An updating module 604, configured to update the first cache address of the cache space to the blocking unit in response to the line interrupt instruction;

[0072] A reading module 606, configured to, after the blocking unit receives a data reading request sent by the encoding unit and determines to allow the data reading request based on the first cache address and the second cache address carried in the data reading request, read the source video data from the cache space based on the first cache address, and encode the read source video data through the encoding unit.

[0073] In one embodiment, the second cache address is a virtual address for the encoding unit to sequentially read the source video data in a frame cache manner; the blocking unit performs address conversion on the second cache address carried in the data reading request to obtain a third cache address, and if the first cache address is the same as the third cache address, it is determined to allow the data reading request.

[0074] In one embodiment, the blocking unit includes cache allocation information corresponding to the cache space; the cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address; based on the cache allocation information, the blocking unit performs address conversion on the second cache address carried in the data read request to obtain a third cache address.

[0075] In one embodiment, the number of cache spaces included in the memory unit is multiple; the cache capacity of each cache space is obtained through custom configuration; the receiving module 602 is further configured to, when the acquisition unit circularly fills the multiple cache spaces one by one in a line-by-line filling manner with the acquired source video data, for each cache space, receive a line interruption instruction for the cache space generated by the acquisition unit each time after the filling of the cache space is completed.

[0076] In one embodiment, the computer device further includes a camera; the acquisition unit receives the original source video data sent by the camera in real time, performs optimization processing on the original source video data to obtain the source video data, and circularly fills the source video data into the cache space in a line-by-line filling manner.

[0077] For the above video processing device, the computer device includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. When the acquisition unit circularly fills the cache space with the acquired source video data in a line-by-line filling manner, the processor receives a line interruption instruction generated by the acquisition unit each time after the filling of the cache space is completed; in response to the line interruption instruction, the processor updates the first cache address of the cache space to the blocking unit; after the blocking unit receives a data read request sent by the encoding unit and determines to release the data read request based on the first cache address and the second cache address carried in the data read request, the processor reads the source video data from the cache space based on the first cache address and encodes the read source video data through the encoding unit. Compared with the traditional video processing method, in this application, the acquisition unit circularly fills the cache space with the acquired source video data in a line-by-line filling manner, and the acquisition unit generates a line interruption instruction each time after the filling of the cache space is completed, so that the amount of source video data cached in the cache space can be less than the amount of data of one frame of image. Furthermore, the processor updates the first cache address of the cache space with the prepared source video data to the blocking unit, so that the blocking unit determines whether to release the data read request based on the first cache address and the second cache address carried in the data read request sent by the encoding unit. After determining to release the data read request, the source video data can be read from the cache space and the read source video data can be encoded through the encoding unit, which can reduce the memory occupation during the video processing, reduce the encoding delay of the video, and improve the video processing efficiency and real-time performance.

[0078] Each module in the above video processing device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of the computer device in hardware form or independent thereof, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0079] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as Figure 7 shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. The computer program, when executed by the processor, implements a video processing method. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen may be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device may be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0080] Those skilled in the art can understand that Figure 7 the structure shown in

[0081] is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0082] In one embodiment, a computer-readable storage medium is provided, storing a computer program, which when executed by a processor, implements the steps in the above-mentioned method embodiments.

[0083] In one embodiment, a computer program product is provided, including a computer program, which when executed by a processor, implements the steps in the above-mentioned method embodiments.

[0084] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions.

[0085] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0086] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0087] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A video processing method, characterized in that: A processor applied to a computer device; the computer device further comprises an acquisition unit, a memory unit, a blocking unit and an encoding unit; The memory unit includes a pre-allocated cache space; the method comprises: In a case where the acquisition unit cyclically fills the acquired source video data into the cache space in a line filling manner, receiving a line interrupt instruction generated by the acquisition unit each time after the acquisition unit completes filling of the cache space; In response to the line interrupt instruction, updating a first cache address of the cache space to the blocking unit; After the blocking unit receives the data read request sent by the encoding unit and determines to release the data read request based on the first cache address and the second cache address carried by the data read request, the source video data is read from the cache space based on the first cache address, and the read source video data is encoded by the encoding unit.

2. The method according to claim 1, characterized in that The second cache address is a virtual address at which the encoding unit sequentially reads the source video data in a frame cache manner; The blocking unit determines, based on the first cache address and the second cache address carried by the data read request, a step of releasing the data read request, comprising: The blocking unit performs address conversion on the second cache address carried by the data read request to obtain a third cache address, and if the first cache address is consistent with the third cache address, determines to release the data read request.

3. The method according to claim 2, characterized in that The blocking unit includes cache allocation information corresponding to the cache space; the cache allocation information includes the number of the cache spaces, the cache capacity of each of the cache spaces, and the cache address; The blocking unit performs address conversion on the second cache address carried by the data read request to obtain a third cache address, comprising: The blocking unit performs address conversion on the second cache address carried by the data read request based on the cache allocation information to obtain a third cache address.

4. The method according to claim 1, characterized in that: The number of cache spaces contained in the memory unit is multiple; the cache capacity of each cache space is obtained by custom configuration; In the case where the acquisition unit cyclically fills the acquired source video data into the cache space in a line filling manner, receiving a line interrupt instruction triggered and generated by the acquisition unit each time after the cache space is filled, comprises: In the case where the acquisition unit cyclically fills the acquired source video data into the multiple cache spaces one by one in a line filling manner, for each of the cache spaces, a line interrupt instruction for the cache space is received, which is triggered and generated by the acquisition unit each time the filling of the cache space is completed.

5. The method according to claim 1, characterized in that The computer device further comprises a camera; the step of the acquisition unit filling the acquired source video data into the cache space in a row filling manner cyclically comprises: The acquisition unit receives the original source video data sent by the camera in real time, optimizes the original source video data to obtain source video data, and cyclically fills the source video data into the cache space in a row filling manner.

6. A video processing device, characterized in that: A processor applied to a computer device; the computer device further comprises a collection unit, a memory unit, a blocking unit and an encoding unit; the memory unit comprises a pre-allocated cache space; the device comprises: A receiving module, configured to receive a line interrupt instruction triggered and generated by the acquisition unit each time after the acquisition unit completes filling of the cache space, when the acquisition unit cyclically fills the acquired source video data into the cache space in a line filling manner; an updating module, configured to update the first cache address of the cache space to the blocking unit in response to the line interrupt instruction; A reading module is used to, after the blocking unit receives a data reading request sent by the encoding unit, determine to release the data reading request based on the first cache address and the second cache address carried by the data reading request, read the source video data from the cache space based on the first cache address, and encode the read source video data through the encoding unit.

7. A video processing system, characterized in that: The system comprises a processor, an acquisition unit, a memory unit, a blocking unit and an encoding unit; the memory unit comprises a pre-allocated cache space; The acquisition unit is used to cyclically fill the acquired source video data into the cache space in a line filling manner, and trigger the generation of a line interrupt instruction every time the cache space is filled; The processor is configured to receive the line interruption instruction, and in response to the line interruption instruction, update the first cache address of the cache space to the blocking unit; The blocking unit is configured to receive a data read request sent by the encoding unit, and determine whether to release the data read request based on the first cache address and a second cache address carried by the data read request; The processor is further configured to read the source video data from the cache space based on the first cache address; The encoding unit is used to encode the read source video data.

8. A computer device, characterized in that: It comprises a processor, an acquisition unit, a memory unit, a blocking unit and an encoding unit; the memory unit comprises a pre-allocated cache space; the memory unit stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the method described in any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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