Solar cell and manufacturing method thereof

Abstract

The invention discloses a solar cell and a manufacturing method thereof, relates to the technical field of photovoltaic, and aims to increase the conductivity and effective doping concentration of a first part, covering at least part of the top of a pyramid-like pyramid, of a first semiconductor layer and facilitate reduction of transmission loss of carriers collected in the first semiconductor layer transmitted to a conductive material. The solar cell includes a semiconductor substrate and a first semiconductor layer. The semiconductor substrate comprises a first surface and a second surface which are opposite. At least one of the first surface and the second surface is a target surface. The surface of at least partial area of the target surface is a suede, and a plurality of similar pyramids are formed on the suede. The plurality of pyramids comprise a plurality of first pyramids, the first semiconductor layer is arranged on the textured surface, and the material of the first semiconductor layer comprises amorphous silicon and / or nano-crystalline silicon. The first semiconductor layer comprises a first part covering the top of the first-type pyramid and a second part covering the base of the first-type pyramid, and the crystallization degree of the first part is larger than that of the second part.

Description

[0001] This application claims the priority of a Chinese patent with an application number of 202411131776.7 and an invention title of "A Solar Cell and Its Manufacturing Method" filed with the China National Intellectual Property Administration on August 16, 2024. The entire content thereof is incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of photovoltaic technology, and in particular, to a solar cell and its manufacturing method. Background Art

[0003] A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated. Among them, amorphous silicon and nanocrystalline silicon materials contain hydrogen, which can hydrogenate the dangling bonds on the surface of the semiconductor substrate, reduce surface defects, and thus have a high passivation effect on the semiconductor substrate. Therefore, when the material of the semiconductor layer in the solar cell includes amorphous silicon and / or nanocrystalline silicon, it is beneficial to reduce the carrier recombination rate.

[0004] However, in existing solar cells, the contact resistance between the semiconductor layer whose material includes amorphous silicon and / or nanocrystalline silicon and the conductive material (transparent conductive layer or electrode) is relatively large, and the transmission loss is relatively high, which is not conducive to improving the working efficiency of the solar cell. Summary of the Invention

[0005] The purpose of the present invention is to provide a solar cell and its manufacturing method, which are used to increase the conductivity and effective doping concentration of the first part of the first semiconductor layer covering the top of the first type of pyramid, reduce the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and further facilitate reducing the transmission loss of the carriers collected in the first semiconductor layer to the conductive material, thereby improving the working efficiency of the solar cell.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a solar cell, which includes: a semiconductor substrate and a first semiconductor layer. The semiconductor substrate includes opposite first and second surfaces. At least one of the first surface and the second surface is a target surface. At least a partial area of the surface of the target surface is a matte surface, and a plurality of pyramid-like structures are formed on the matte surface. The plurality of pyramid-like structures include a plurality of first type of pyramid-like structures, and the first semiconductor layer is disposed on the matte surface. The material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer covers the first part of the top of the first type of pyramid-like structure and the second part covering the base of the first type of pyramid-like structure. The crystallization degree of the first part is greater than that of the second part.

[0007] In the case of adopting the above technical solution, compared with the situation where the surface of the first semiconductor layer facing away from the semiconductor substrate is a flat surface, when the first semiconductor layer is disposed on the textured surface, the surface of the first semiconductor layer facing away from the semiconductor substrate has a rough morphology substantially the same as that of the textured surface. At this time, the first semiconductor layer has a larger specific surface area, which can increase the contact area between the first semiconductor layer and the conductive material (such as a transparent conductive layer or an electrode), and reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. Additionally, it can be understood that, under the condition that other factors are the same, when the crystallization degree of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even present the disorder of amorphous silicon material. And the smaller the grains in the semiconductor layer, the more interfaces there are between the grains in the semiconductor layer, so the resistance of the grain interfaces will be relatively large. Moreover, in the actual manufacturing process, the semiconductor layer is generally crystallized at a relatively high temperature to improve the crystallization degree of the semiconductor layer; and the semiconductor layer with smaller grains is more sensitive to temperature, and the effective doping concentration of the semiconductor layer obtained at a relatively low doping temperature is also relatively low. Therefore, compared with the situation where the crystallization degree of the part of the first semiconductor layer covering the top of the pseudo-pyramid and the crystallization degree of the part of the first semiconductor layer covering the base of the pseudo-pyramid are both relatively low, when in the solar cell provided by the present invention, the crystallization degree of the first part of the first semiconductor layer covering the top of the first pseudo-pyramid is greater than the crystallization degree of the second part of the first semiconductor layer covering the base of the first pseudo-pyramid, it is beneficial to reduce the number of interfaces between the grains in the first part of the first semiconductor layer covering the top of the first pseudo-pyramid, and reduce the transmission resistance of the above first part; and at this time, the first part included in the first semiconductor layer can be crystallized at a relatively high temperature, which can enable more dopants to be doped into the first part included in the first semiconductor layer, thereby being beneficial to increasing the effective doping concentration of the first part included in the first semiconductor layer, improving the conductivity of the first part included in the first semiconductor layer, reducing the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and further being beneficial to reducing the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, in the first semiconductor layer, at least the second part of the first semiconductor layer covering the base of the first pseudo-pyramid has a smaller crystallization degree. In the case of crystallization treatment at a reduced temperature, at least the above second part has a relatively high hydrogen content, so that at least the second part has a relatively high passivation effect on the textured surface, reduces the number of defects on the textured surface, and improves the working efficiency of the solar cell. In short, forming a first part with a larger crystallization degree at the top of the first pseudo-pyramid can ensure reducing the contact resistance between the conductive material and the first semiconductor layer. However, at the same time, the first part with a larger crystallization degree cannot be too large, that is, the second part at the base of the first pseudo-pyramid has a lower crystallization degree, which can ensure the passivation effect of the first semiconductor layer, that is, the balance between the contact resistance and the passivation effect is taken into account.

[0008] As a possible implementation, in the first semiconductor layer, the material of the first part includes nanocrystalline silicon; the material of the second part includes amorphous silicon.

[0009] In the case of adopting the above technical solution, under the condition that other factors are the same, compared with nanocrystalline silicon, the crystallization degree of the amorphous silicon material is lower, and the amorphous silicon material is less affected by heat during the crystallization process, so that the hydrogen content in the amorphous silicon material is relatively high. Based on this, when the material of the second part in the first semiconductor layer includes amorphous silicon, it is beneficial to make the second part contain more hydrogen, which is beneficial to hydrogenate the dangling bonds on the surface of the semiconductor substrate, reduce surface defects, and thus have a high passivation effect on the semiconductor substrate. When the material of the first part in the first semiconductor layer includes nanocrystalline silicon, it is beneficial to make the first part with at least a larger crystallization degree in the first semiconductor layer have high conductivity and effective doping concentration, reduce the contact resistance between the first part in the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and further facilitate reducing the transmission loss of the carriers collected in the first semiconductor layer to the conductive material.

[0010] As a possible implementation, the first part of the above first semiconductor layer contains crystal grains, and the maximum size of the crystal grains is less than the thickness of the first part.

[0011] In the case of adopting the above technical solution, during the actual manufacturing process, the larger the crystal grain size in the first part of the first semiconductor layer, the higher the temperature during the crystallization treatment of the first part of the first semiconductor layer. And the higher the treatment temperature, the greater the amount of hydrogen escaping from the first part of the first semiconductor layer, resulting in a reduction in the passivation effect of the first part of the first semiconductor layer on the semiconductor substrate. Therefore, compared with the case where the maximum size of the crystal grains in the first part of the first semiconductor layer is equal to the thickness of the first part, when the maximum size of the crystal grains in the first part of the first semiconductor layer is less than the thickness of the first part, the corresponding crystallization temperature of the first semiconductor layer is lower, which is beneficial to making the first part of the first semiconductor layer have high conductivity and effective doping concentration, reducing the transmission loss between the first part of the first semiconductor layer and the conductive material, while making the part of the first semiconductor layer where no crystal grains grow have a relatively high passivation effect on the semiconductor substrate, which is beneficial to making the corresponding passivation effect and transmission loss of the first semiconductor layer reach a balance, and further improving the working performance of the solar cell.

[0012] As a possible implementation, the crystallization depth of the first part of the above first semiconductor layer is less than the thickness of the first part. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect that the maximum size of the crystal grains in the first part of the first semiconductor layer is less than the thickness of the first part described above, and will not be elaborated here.

[0013] As a possible implementation, the crystallization depth of the first part of the first semiconductor layer gradually decreases along the inclined direction of the side surface of the quasi-pyramid and towards the base of the quasi-pyramid. In this case, when crystallizing at least part of the first semiconductor layer, the processing temperature of each part of the first semiconductor layer covering the quasi-pyramid gradually decreases along the inclined direction of the side surface of the quasi-pyramid and towards the base of the quasi-pyramid. While enabling the first part of the first semiconductor layer to have high conductivity and effective doping concentration, it helps to reduce the impact of the high temperature during the crystallization process on the remaining part of the first semiconductor layer, ensuring that the remaining part of the first semiconductor layer has a high hydrogen content, thereby enabling the remaining part of the first semiconductor layer to have a high passivation effect on the semiconductor substrate.

[0014] As a possible implementation, along the inclined direction of the side surface of the quasi-pyramid, the ratio of the maximum extension length of the first part on the side surface of the first quasi-pyramid below itself to the length of the side surface of the first quasi-pyramid is less than or equal to 0.3.

[0015] In the case of adopting the above technical solution, as described above, although the first part included in the first semiconductor layer can reduce the transmission loss between the first semiconductor layer and the conductive material, the hydrogen content in the first part of the first semiconductor layer is relatively low, resulting in a relatively weak passivation effect of the first part on the semiconductor substrate (compared with the second part); based on this, when the ratio of the maximum extension length of the first part of the first semiconductor layer on the side surface of the first quasi-pyramid below itself to the length of the side surface of the first quasi-pyramid is less than or equal to 0.3 along the inclined direction of the side surface of the first quasi-pyramid, the part with a high passivation effect in the first semiconductor layer (including the above second part) can have a larger coverage range on the textured surface, which can further reduce the number of surface defects on the textured surface. Additionally, in the actual manufacturing process, the heating rate at the top of the quasi-pyramid is faster than that at its own base, and it is easier to accumulate more heat at its top to make its crystallization degree higher. Based on this, when the ratio of the maximum extension length of the first part of the first semiconductor layer on the side surface of the first quasi-pyramid below itself to the length of the side surface of the first quasi-pyramid is less than or equal to 0.3 along the inclined direction of the side surface of the first quasi-pyramid, it can prevent the part of the first semiconductor layer above the first quasi-pyramid from overheating due to the large extension length of the first part of the first semiconductor layer above the first quasi-pyramid, ensuring that the first part of the first semiconductor layer at the top of the first quasi-pyramid also has a certain passivation effect, and further improving the working efficiency of the solar cell.

[0016] As a possible implementation solution, the thickness of the above-mentioned first semiconductor layer is greater than or equal to 10 nm, and / or the thickness of the first semiconductor layer is less than or equal to 45 nm. In this case, the lower limit and / or upper limit of the thickness of the first semiconductor layer including amorphous silicon and / or nanocrystalline silicon are greater, which is conducive to reducing the thermal impact of heat on the semiconductor substrate through the thicker first semiconductor layer, preventing thermal damage to the semiconductor substrate during the crystallization process of at least part of the first semiconductor layer, and ensuring that the solar cell has a high yield. Moreover, the thicker first semiconductor layer has a high passivation effect, which can further reduce the carrier recombination rate at the textured surface and further improve the working efficiency of the solar cell.

[0017] As a possible implementation solution, the above-mentioned solar cell further includes a transparent conductive layer, and the transparent conductive layer covers at least the side of the first semiconductor layer facing away from the semiconductor substrate. In this case, the transparent conductive layer has a high conductivity, can timely export the carriers collected by the first semiconductor layer, and can reduce the carrier recombination rate.

[0018] As a possible implementation solution, the above-mentioned pseudo-pyramid is a pyramid with a sharp apex angle; or, the pseudo-pyramid is a pseudo-pyramid with a rounded chamfer; or, the pseudo-pyramid is a pseudo-pyramid with a truncated apex angle. In this case, the pseudo-pyramid can have at least the above three examples, which is conducive to improving the applicability of the solar cell provided by the present invention in different application scenarios. In addition, there is no need to strictly control the manufacturing accuracy to obtain a pseudo-pyramid with a single morphology, which reduces the process difficulty and is conducive to improving the yield of the solar cell.

[0019] As a possible implementation solution, the surface of the above-mentioned pseudo-pyramid is a plane. In this case, compared with the surface of the pseudo-pyramid being uneven, when the surface of the pseudo-pyramid is a plane, the undulation degree of the pseudo-pyramid is relatively low, which is conducive to enabling the first semiconductor layer deposited on the textured surface to have a larger thickness and further improving the high passivation effect of the first semiconductor layer.

[0020] As a possible implementation solution, the surface roughness of the first part of the above-mentioned first semiconductor layer is greater than that of the second part. In this case, the specific surface area of the first part of the first semiconductor layer is larger, which is conducive to increasing the contact area between the first part and the conductive material, reducing the contact resistance between the first part and the conductive material, further reducing the transmission loss of carriers from the first semiconductor layer to the conductive material, and further improving the working efficiency of the solar cell. In addition, in the actual manufacturing process, laser irradiation or high-temperature annealing is required to achieve the crystallization modification of part of the first semiconductor layer. The heating rate of the top of the quasi-pyramid is faster than that of its own substrate, and it is easier to achieve crystallization modification. Moreover, the change in the surface roughness of the first part is related to the change in the crystallization degree of the first part and the escape of hydrogen in itself. Based on this, when the surface roughness of the first part is greater than that of the second part, there is no need to cause dehydrogenation due to the longer heating time of each part of the first semiconductor layer in order to make the second part covering the base of the first type of pyramid of the first semiconductor layer also have a large surface roughness, ensuring that the first semiconductor layer has a high passivation effect.

[0021] As a possible implementation solution, the above-mentioned first semiconductor layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer. The first doped semiconductor layer is disposed on the side of the first intrinsic semiconductor layer facing away from the semiconductor substrate. And, along the direction close to the textured surface, the maximum size of the grains included in the first part of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer; and / or, the crystallization depth of the first part of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer.

[0022] In the case of adopting the above technical solution, the first intrinsic semiconductor layer and the first doped semiconductor layer can form a selective contact structure, which has excellent interface passivation effect and can realize the selective collection of carriers, reducing the carrier recombination rate in the region of the semiconductor substrate where the first semiconductor layer is formed, and further improving the photoelectric conversion efficiency of the solar cell. Secondly, along the direction close to the textured surface, the maximum size of the grains included in the first part of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer. At this time, the part of the first intrinsic semiconductor layer corresponding to the largest grains still has a passivation effect on the semiconductor substrate, which can further reduce the carrier recombination rate. Secondly, the application principle of the beneficial effect that the crystallization depth of the first part of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer can refer to the previous text and will not be elaborated here.

[0023] As a possible implementation solution, the above solar cell further includes a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer. Among them, the second semiconductor layer and the first semiconductor layer are disposed on the same side of the semiconductor substrate, and the first semiconductor layer extends to cover a part of the second semiconductor layer on the side facing away from the semiconductor substrate; and / or, the second semiconductor layer is disposed on the second side of the semiconductor substrate, and the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0024] In the case of adopting the above technical solution, when the second semiconductor layer and the first semiconductor layer are disposed on the same side of the semiconductor substrate, the solar cell provided by the present invention is a back contact cell, which can reduce the influence of the light-shielding electrode structure on the light utilization rate on the light-facing side, and further improve the photoelectric conversion efficiency of the solar cell. In addition, when the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, there are various possible examples of the material of the second semiconductor layer, which is beneficial to improving the applicability of the solar cell provided by the present invention in different application scenarios.

[0025] In a second aspect, the present invention provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes: providing a semiconductor substrate. The semiconductor substrate has opposite first and second sides. At least one of the first side and the second side is a target side. At least a part of the surface of the target side is a textured surface. A plurality of pseudo-pyramids are formed on the textured surface. The plurality of pseudo-pyramids include a plurality of first pseudo-pyramids. Next, a first semiconductor layer is formed on the textured surface. The material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes a first part covering the top of the first pseudo-pyramid and a second part covering the base of the first pseudo-pyramid; the crystallization degree of the first part is greater than that of the second part.

[0026] As a possible implementation solution, a laser irradiation process is adopted to crystallize at least a part of the first semiconductor layer, so that the crystallization degree of the first part of the first semiconductor layer is greater than that of the second part of the first semiconductor layer.

[0027] As a possible implementation solution, the wavelength of the laser used in the above laser irradiation process is greater than or equal to 325 nm and less than or equal to 532 nm; and / or, the pulse width of the laser irradiation process is picosecond or nanosecond level; and / or, the laser energy density of the laser irradiation process is greater than or equal to 200 mJ / cm 2 and less than or equal to 6000 mJ / cm 2 .

[0028] The beneficial effects of the second aspect and its various implementation manners in the present invention can be referred to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are provided to further understand the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0030] Figure 1 is a longitudinal sectional schematic view of the first structure of the solar cell provided by the embodiment of the present invention;

[0031] Figure 2 is a partial structure SEM image of the solar cell provided by the embodiment of the present invention at a single type of pyramid;

[0032] Figure 3 is Figure 2 a partial enlarged TEM image of the region framed by the bold rectangular solid line in at the first magnification;

[0033] Figure 4 is Figure 2 a partial enlarged TEM image of the region framed by the bold rectangular solid line in at the second magnification;

[0034] Figure 5 is Figure 2 a partial enlarged TEM image of the region framed by the rectangular dashed line in ;

[0035] Figure 6 is Figure 2 a partial enlarged TEM image of the region framed by the thinner rectangular dashed line in ;

[0036] Figure 7 is a partial structure SEM image of the solar cell provided by the embodiment of the present invention at multiple types of pyramids;

[0037] Figure 8 is a longitudinal sectional schematic view of the second structure of the solar cell provided by the embodiment of the present invention;

[0038] Figure 9 is a longitudinal sectional schematic view of the third structure of the solar cell provided by the embodiment of the present invention;

[0039] Figure 10 is a longitudinal sectional schematic view of the fourth structure of the solar cell provided by the embodiment of the present invention;

[0040] Figure 11 is a longitudinal sectional schematic view of the fifth structure of the solar cell provided by the embodiment of the present invention;

[0041] Figure 12 is a longitudinal sectional schematic view of the sixth structure of the solar cell provided by the embodiment of the present invention;

[0042] Figure 13 Schematic diagram of the result of a kind of pyramid-like morphology in the solar cell provided by the embodiment of the present invention;

[0043] Figure 14 Schematic diagram of the result of another kind of pyramid-like morphology in the solar cell provided by the embodiment of the present invention;

[0044] Figure 15 Longitudinal sectional view of the seventh structure of the solar cell provided by the embodiment of the present invention;

[0045] Figure 16 Longitudinal sectional view of the eighth structure of the solar cell provided by the embodiment of the present invention;

[0046] Figure 17 Longitudinal sectional view of the ninth structure of the solar cell provided by the embodiment of the present invention;

[0047] Figure 18 Longitudinal sectional view of the tenth structure of the solar cell provided by the embodiment of the present invention;

[0048] Figure 19 Longitudinal sectional view of the eleventh structure of the solar cell provided by the embodiment of the present invention;

[0049] Figure 20 Longitudinal sectional view of the twelfth structure of the solar cell provided by the embodiment of the present invention.

[0050] Reference numerals: 11 is a semiconductor substrate, 12 is a target surface, 13 is a pyramid-like structure, 14 is a first semiconductor layer, 15 is a first part, 16 is a second part, 17 is a transparent conductive layer, 18 is a first intrinsic semiconductor layer, 19 is a first doped semiconductor layer, 20 is a second semiconductor layer, 21 is an insulating layer, 22 is an interface passivation layer, 23 is a second doped semiconductor layer. Detailed implementation manners

[0051] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0052] Various schematic structural diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where certain details are enlarged for clearer expression and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual requirements.

[0053] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined. "Several" means one or more unless otherwise specifically defined.

[0055] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated. Among them, amorphous silicon and nanocrystalline silicon materials contain hydrogen, which can hydrogenate the dangling bonds on the surface of the semiconductor substrate, reduce surface defects, and thus have a high passivation effect on the semiconductor substrate. Therefore, when the material of the semiconductor layer in the solar cell includes amorphous silicon and / or nanocrystalline silicon, it is beneficial to reduce the carrier recombination rate.

[0057] However, compared with semiconductor layers with higher crystallization degrees such as polycrystalline silicon or single-crystalline silicon, the effective doping concentration of semiconductor layers with materials including amorphous silicon and / or nanocrystalline silicon is relatively low, resulting in poor conductivity of semiconductor layers with materials including amorphous silicon and / or nanocrystalline silicon in existing solar cells. Furthermore, it leads to a relatively high transmission loss between the semiconductor layer with materials including amorphous silicon and / or nanocrystalline silicon and the conductive material (transparent conductive layer or electrode), which is not conducive to improving the working efficiency of the solar cell.

[0058] To solve the above technical problems, on the one hand, an embodiment of the present invention provides a solar cell. As Figures 1 to 7 shown, the solar cell includes: a semiconductor substrate 11 and a first semiconductor layer 14. The semiconductor substrate 11 includes opposite first and second surfaces. At least one of the first and second surfaces is a target surface 12. At least a partial region of the surface of the target surface 12 is a textured surface, and a plurality of pyramidal-like structures 13 are formed on the textured surface. The plurality of pyramidal-like structures 13 include a plurality of first-type pyramids. The first semiconductor layer 14 is disposed on the textured surface, and the material of the first semiconductor layer 14 includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer 14 includes a first portion 15 covering the top of the first-type pyramids and a second portion 16 covering the base of the first-type pyramids. The crystallization degree of the first portion 15 is greater than that of the second portion 16. The number of the plurality of first-type pyramids can be a part of the plurality of pyramidal-like structures 13. For example, the number of the plurality of first-type pyramids can account for 70%, 50%, 40%, etc. of the plurality of pyramidal-like structures. Specifically, it can be reasonably set according to the thickness of the first semiconductor layer and the laser conditions.

[0059] Among them, as Figures 1 to 7 shown, the above-mentioned first semiconductor layer 14 can follow the surface morphology of the textured surface. At this time, the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11 has a substantially the same undulating morphology as the textured surface. However, due to the influence of the deposition process, the thickness of the first semiconductor layer 14 at the top of the pyramidal-like structure 13 may be different from the thickness of the first semiconductor layer 14 at the base of the pyramidal-like structure 13.

[0060] In the case of adopting the above technical solution, as Figures 1 to 7 shown, compared with the case where the surface of the first semiconductor layer 14 facing away from the semiconductor substrate 11 is a plane, when the first semiconductor layer 14 is disposed on the textured surface, the surface of the first semiconductor layer 14 facing away from the semiconductor substrate 11 has a rough morphology substantially the same as that of the textured surface. At this time, the first semiconductor layer 14 has a larger specific surface area, which can increase the contact area between the first semiconductor layer 14 and the conductive material (such as a transparent conductive layer or an electrode), and reduce the transmission loss of the carriers collected in the first semiconductor layer 14 to the conductive material. In addition, it can be understood that, under the condition that other factors are the same, the smaller the crystallization degree of the semiconductor layer, the smaller the grains in the semiconductor layer, and even the amorphous silicon material shows disorder. And the smaller the grains in the semiconductor layer, the more interfaces there are between the grains in the semiconductor layer, so the resistance of the grain interfaces will be relatively large. The larger crystallization degree referred to in the embodiments of the present invention may mean a larger crystallization rate, a larger grain size, and / or a larger number of grains. For example, when the first semiconductor layer is a nanocrystalline silicon layer (which generally still contains a part of amorphous silicon inside, which is inevitable and the content of the amorphous silicon part is small, as is known in the art), the first part with a larger crystallization degree has a larger crystallization rate and grain size than the second part. When the first semiconductor layer is amorphous silicon (which may contain a small amount of nanocrystalline silicon inside, but the content of the nanocrystalline silicon part is very small, for example, less than 5%, as is known in the art), grains with an ordered lattice are generated inside the first part with a larger crystallization degree, and its crystallization degree increases, while the second part with a smaller crystallization degree remains an amorphous silicon material and does not generate grains after being treated by laser or the like.

[0061] Moreover, in the actual manufacturing process, the semiconductor layer is generally crystallized at a relatively high temperature to improve the crystallization degree of the semiconductor layer; while the semiconductor layer with smaller grains is more sensitive to temperature, and the effective doping concentration of the semiconductor layer obtained at a relatively low doping temperature is also relatively low. Therefore, compared with the case where the crystallization degrees of the part of the first semiconductor layer covering the top of the pseudo-pyramid and the part of the first semiconductor layer covering the base of the pseudo-pyramid are both relatively low, as Figures 1 to 7 shown, in the solar cell provided by the embodiment of the present invention, the crystallization degree of the first part 15 of the first semiconductor layer 14 (by Figures 2 to 6It can be seen that when the first part 15 of the first semiconductor layer 14 contains crystal grains, that is, at least part of it has a relatively regular lattice distribution, and the crystallization degree is greater than that of the second part 16 of the first semiconductor layer 14, it is beneficial to reduce the number of interfaces between the crystal grains in the first part 15 of the first semiconductor layer 14 and reduce the transmission resistance of the first part 15 of the first semiconductor layer 14. Moreover, at this time, the first part 15 of the first semiconductor layer 14 can be crystallized at a relatively high temperature, enabling more dopants to be doped into the first part 15 of the first semiconductor layer 14, thereby facilitating an increase in the effective doping concentration of the first part 15 of the first semiconductor layer 14, improving the conductivity of the first part 15 of the first semiconductor layer 14, reducing the contact resistance between the first semiconductor layer 14 and the conductive material (transparent conductive layer or electrode), and further facilitating a reduction in the transmission loss of the carriers collected in the first semiconductor layer 14 to the conductive material. At the same time, in the first semiconductor layer 14, the second part 16 has a relatively low crystallization degree. In the case of crystallization treatment at a reduced temperature, at least the second part 16 of the first semiconductor layer 14 has a relatively high hydrogen content, such that at least the second part 16 of the first semiconductor layer 14 has a relatively high passivation effect on the textured surface, reducing the number of defects on the textured surface and improving the working efficiency of the solar cell. In short, forming a first part 15 with a relatively large crystallization degree at the top of the first type of pyramid can ensure a reduction in the contact resistance between the conductive material and the first semiconductor layer 14. However, at the same time, the first part 15 with a relatively large crystallization degree cannot be too large, that is, the second part 16 at the base of the first type of pyramid has a relatively low crystallization degree, which can ensure the passivation effect of the first semiconductor layer 14, that is, a balance between the contact resistance and the passivation effect is achieved. As for the boundary between the first part 15 and the second part 16 in the first semiconductor layer 14, it is determined by Figure 6 It can be seen that when in the first semiconductor layer 14, the part near the top of the first type of pyramid and with a grain size and / or crystallization depth greater than the part of the first semiconductor layer 14 distributed above the remaining regions of the first type of pyramid is the first part 15, and the edge contour of the first part 15 is the boundary between the first part 15 and the second part 16.

[0062] In the actual application process, the embodiments of the present invention do not make specific limitations on the material and conductivity type of the semiconductor substrate. Exemplarily, the above semiconductor substrate can be a silicon substrate. Alternatively, the above semiconductor substrate can also be a substrate of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.

[0063] Secondly, the semiconductor substrate has opposite first and second surfaces. Among them, the first surface of the semiconductor substrate can correspond to the light-facing surface of the solar cell, and in this case, the second surface of the semiconductor substrate corresponds to the backlight surface of the solar cell; or, the first surface of the semiconductor substrate can also correspond to the backlight surface of the solar cell, and in this case, the second surface of the semiconductor substrate corresponds to the light-facing surface of the solar cell. In addition, since the first semiconductor layer is formed on the textured surface of the target surface, the first and second surfaces of the semiconductor substrate can be determined as the target surface according to the requirements for the formation position of the first semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0064] Exemplarily, as Figure 1 , Figure 8 and Figure 9 shown, when the solar cell provided by the embodiment of the present invention is a double-sided contact cell, among the first surface and the second surface, only the first surface can be the target surface 12, or only the second surface can be the target surface 12, or both the first surface and the second surface can be the target surface 12. It should be noted that, as Figure 9 shown, when both the first surface and the second surface are the target surface 12, the conduction types of the two first semiconductor layers 14 formed on the first surface and the second surface are opposite.

[0065] Exemplarily, as Figure 10 shown, when the solar cell provided by the embodiment of the present invention is a back contact cell, among the first surface and the second surface, the one corresponding to the backlight surface of the solar cell is the target surface 12. Specifically, when the first surface of the semiconductor substrate 11 corresponds to the backlight surface of the solar cell, the first surface is the target surface 12. And when the second surface of the semiconductor substrate 11 corresponds to the backlight surface of the solar cell, the second surface is the target surface 12.

[0066] In addition, as Figure 10 shown, in the target surface 12, only the surface of a local area can be a textured surface, and the surfaces of the remaining areas can be a polished surface or a curved surface with unevenness, etc. Or, as Figure 8 and Figure 9 shown, it can also be that the entire area surface of the target surface 12 is a textured surface. Specifically, the distribution range of the textured surface on the target surface 12 can be determined according to the type of the solar cell and the actual application scenario, and no specific limitation is made here.

[0067] Exemplarily, as Figure 8 and Figure 9 shown, in the case where the solar cell is a double-sided contact cell, the entire area surface of the target surface 12 can be a textured surface. Or, as Figure 11 shown, only a local area of the target surface 12 can be a textured surface, and the surfaces of the remaining areas of the target surface 12 can be a polished surface or a curved surface with unevenness, etc.

[0068] Exemplarily, as Figure 10 shown, when the solar cell is a back-contact cell, it is also possible that only the surface of the region corresponding to the first semiconductor layer 14 in the target surface 12 is a textured surface, and the surfaces of the remaining regions of the target surface 12 can be in morphologies such as polished surfaces. Or, as Figure 12 shown, it is also possible that all regions of the target surface 12 are textured surfaces.

[0069] In terms of the setting of the pseudo-pyramids, the embodiments of the present invention do not specifically limit the morphology, size, and distribution of the pseudo-pyramids formed on the textured surface, as long as they can be applied to the solar cells provided by the embodiments of the present invention.

[0070] Exemplarily, as Figure 11 and Figure 12 shown, the above pseudo-pyramids 13 can be pyramids with sharp apex angles; or, as Figure 13 shown, the above pseudo-pyramids 13 can also be pseudo-pyramids 13 with rounded chamfers; or, as Figure 14 shown, the pseudo-pyramids 13 can also be pseudo-pyramids 13 with flattened apex angles. In this case, the pseudo-pyramids 13 can have at least the above three examples, which is beneficial to improving the applicability of the solar cells provided by the embodiments of the present invention in different application scenarios. In addition, there is no need to strictly control the manufacturing accuracy to obtain pseudo-pyramids 13 with a single morphology, reducing the process difficulty and being beneficial to improving the yield of the solar cells.

[0071] Exemplarily, as Figure 11 and Figure 12 shown, the surfaces of the above pseudo-pyramids 13 can also be flat surfaces. In this case, compared with the surfaces of the pseudo-pyramids being uneven surfaces, when the surfaces of the pseudo-pyramids 13 are flat surfaces, the surfaces of the pseudo-pyramids 13 are relatively flat, and the undulation degree of the pseudo-pyramids 13 on the textured surface is relatively low, which is beneficial to enabling the first semiconductor layer 14 deposited on the textured surface to have a larger thickness and further improving the passivation effect of the first semiconductor layer 14. Or, as Figures 2 to 4 shown, the surfaces of the above pseudo-pyramids 13 can also have uneven microstructures, and the positions of these microstructures can correspond to the parts of the first semiconductor layer 14 with a higher degree of crystallization.

[0072] Exemplarily, the one-dimensional dimension of the above-mentioned pyramid-like structure (which can be the side length, diagonal length, height, etc. of the base of the pyramid-like structure) can be greater than or equal to 2 μm and less than or equal to 4 μm. For example, the one-dimensional dimension of the pyramid-like structure can be 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.6 μm, 3.8 μm, or 4 μm, etc. In this case, not only can the contact area between the first semiconductor layer and the conductive material be increased by the presence of the pyramid-like structure, but also the surface texture can have a certain light-trapping effect, improving the utilization rate of light by the semiconductor substrate. Additionally, it can prevent the processing temperature from being too high and affecting the passivation effect of the first semiconductor layer due to the small one-dimensional dimension of the pyramid-like structure, which may cause a larger crystallized first part with a greater degree of crystallization in the first semiconductor layer within a fixed range above the top of the first pyramid-like structure among multiple pyramid-like structures; or prevent the extension range of the larger crystallized first part in the first semiconductor layer above the top of the first pyramid-like structure or the crystallization depth of the larger crystallized first part in the first semiconductor layer from being too large under the same processing conditions when the one-dimensional dimension of the first pyramid-like structure is large, ensuring that the first semiconductor layer has a high passivation effect.

[0073] Regarding the distribution of different pyramid-like structures on the surface texture, it can be understood that the distance between the top and the base of a pyramid-like structure with a greater height is larger. And the base of the pyramid-like structure has a larger contact area with the semiconductor substrate, and the semiconductor substrate has a good heat dissipation effect. Therefore, during the crystallization process of at least part of the first semiconductor layer, the heat dissipated by the top of a pyramid-like structure with a greater height may be less after being heated, and it is easier to accumulate more heat to crystallize itself. Additionally, when using a laser irradiation process to crystallize at least part of the first semiconductor layer, since the pyramid-like structure has a reflection effect on the laser, the reflected laser is more likely to be concentrated on the top of the pyramid-like structure with a greater height, resulting in a higher heating degree of the top of the pyramid-like structure with a greater height and making it easier to crystallize at the part of the first semiconductor layer corresponding to the top of the pyramid-like structure with a greater height. Moreover, when the distribution density of other pyramid-like structures around a single pyramid-like structure is large, the reflected laser is more likely to be concentrated on the top of this single pyramid-like structure. Based on this, the distribution of different pyramid-like structures on the surface texture can be determined according to the requirements for the distribution of the first part with a greater degree of crystallization in the first semiconductor layer in the actual application scenario, and no specific limitation is provided here.

[0074] For the above-mentioned first semiconductor layer, in terms of the film layer structure, as Figure 11 and Figure 12 shown, the first semiconductor layer 14 can be a single-layer structure; in this case, the first semiconductor layer 14 can only include a first doped semiconductor layer. Or, the first semiconductor layer can also be a stack composed of at least two film layers. Exemplarily, as Figure 15As shown, the above-mentioned first semiconductor layer 14 may include: a first intrinsic semiconductor layer 18 and a first doped semiconductor layer 19. The first doped semiconductor layer 19 is disposed on a side of the first intrinsic semiconductor layer 18 facing away from the semiconductor substrate 11. In this case, the first intrinsic semiconductor layer 18 and the first doped semiconductor layer 19 may form a selective contact structure, which has an excellent interface passivation effect, can achieve selective carrier collection, reduce the carrier recombination rate in the region of the semiconductor substrate 11 where the first semiconductor layer 14 is formed, and further improve the photoelectric conversion efficiency of the solar cell.

[0075] In terms of materials, the material of the first semiconductor layer may include only any one of amorphous silicon and nanocrystalline silicon, or may include both amorphous silicon and nanocrystalline silicon, as long as the crystallization degree of the first semiconductor layer covering at least a first part of the top of the class pyramid is greater than the crystallization degree of the second part of the first semiconductor layer covering the base of the class pyramid.

[0076] It should be noted that in the first semiconductor layer, the crystallization degree of only the first part covering at least a part of the top of the class pyramid is greater than the crystallization degree of the second part of the first semiconductor layer covering the base of the class pyramid, and the material of the remaining part of the first semiconductor layer except the first part is amorphous silicon. Since the class pyramid is a microstructure formed on the textured surface, when the number of the first type of pyramids below the above-mentioned first part is limited, it can be considered that the material of the first semiconductor layer is only amorphous silicon, and the above situation should also be considered to be included within the protection scope of the present invention.

[0077] Secondly, when the material of the first semiconductor layer includes at least two types, the distribution of different materials in the first semiconductor layer can be determined according to the crystallization degree of different parts of the first semiconductor layer and the actual manufacturing process, and no specific limitation is made here.

[0078] Exemplarily, such as Figures 2 to 6As shown, in the first semiconductor layer 14, the material of the first part may include amorphous silicon; and / or, in the first semiconductor layer 14, the material of the second part may include nano-crystalline silicon. In this case, when other factors are the same, compared with nano-crystalline silicon, the degree of crystallization of the amorphous silicon material is lower, and the amorphous silicon material is less affected by heat during the crystallization process, so that the hydrogen content in the amorphous silicon material is relatively high. Based on this, when the material of the second part in the first semiconductor layer 14 includes amorphous silicon, it is beneficial to make the second part covering at least the base of the first type of pyramid in the first semiconductor layer 14 contain more hydrogen, which is beneficial to hydrogenate the dangling bonds on the surface of the semiconductor substrate, reduce surface defects, and thus have a high passivation effect on the semiconductor substrate. When the material of the first part with at least a greater degree of crystallization in the first semiconductor layer 14 includes nano-crystalline silicon, it is beneficial to make the first part in the first semiconductor layer 14 have high conductivity and effective doping concentration, reduce the contact resistance between the first part in the first semiconductor layer 14 and the conductive material (transparent conductive layer or electrode), and further facilitate reducing the transmission loss of the carriers collected in the first semiconductor layer 14 to the conductive material.

[0079] Exemplarily, as Figure 2 shown, in the first semiconductor layer 14, the material of the part with a greater degree of crystallization may include nano-crystalline silicon, and the material of the part with a smaller degree of crystallization (including the second part 16 of the first semiconductor layer 14) may be amorphous silicon. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects when the material of at least the part covering the base of the pyramid-like structure 13 in the first semiconductor layer 14 includes amorphous silicon, and the material of at least the part with a greater degree of crystallization in the first semiconductor layer 14 includes nano-crystalline silicon, which will not be elaborated here.

[0080] In the actual application process, the material of the part of the first semiconductor layer covering the base of the pyramid-like structure may be only amorphous silicon, and at this time, the part of the first semiconductor layer covering the base of the pyramid-like structure has a high passivation effect on the semiconductor substrate. In this case, the material of the first part of the first semiconductor layer covering the top of the first type of pyramid may be only nano-crystalline silicon, or may include both nano-crystalline silicon and amorphous silicon. Among them, in the actual manufacturing process, the degree of heat absorption of different regions of the first part of the first semiconductor layer covering the top of the first type of pyramid gradually decreases along the direction close to the textured surface. Therefore, the region of the first part of the first semiconductor layer covering the top of the first type of pyramid far from the textured surface is more likely to crystallize. Based on this, when the material of the first part of the first semiconductor layer covering the top of the first type of pyramid includes both nano-crystalline silicon and amorphous silicon, the region of the nano-crystalline silicon material is more likely to be distributed in the region of the first part of the first semiconductor layer covering the top of the first type of pyramid far from the textured surface.

[0081] Alternatively, the material of the portion of the first semiconductor layer covering the base of the pyramid-like structure may include nanocrystalline silicon in addition to amorphous silicon. In this case, in the portion of the first semiconductor layer covering the base of the pyramid-like structure, the proportion of nanocrystalline silicon may be less than, equal to, or greater than the proportion of amorphous silicon. In this situation, the material of the first portion of the first semiconductor layer covering the top of the first type of pyramid may be only nanocrystalline silicon, or may include both nanocrystalline silicon and amorphous silicon. Among them, when the material of the first portion of the first semiconductor layer covering the top of the first type of pyramid includes nanocrystalline silicon and amorphous silicon, the distribution of nanocrystalline silicon and amorphous silicon may refer to the previous text and will not be elaborated here.

[0082] Or, the material of each part of the first semiconductor layer may be all nanocrystalline silicon, and the crystallization degree of the nanocrystalline silicon in the first portion of the first semiconductor layer covering the top of the first type of pyramid is greater than the crystallization degree of the nanocrystalline silicon in the second portion of the first semiconductor layer covering the base of the first type of pyramid.

[0083] In terms of the crystallization degree, the embodiments of the present invention do not specifically limit the magnitudes of the crystallization degrees of the first portion of the first semiconductor layer covering the top of the first type of pyramid and the second portion of the first semiconductor layer covering the base of the first type of pyramid. It can be understood that, as described above, when the crystallization degree of the first portion of the first semiconductor layer covering the top of the first type of pyramid is relatively large, it is beneficial to improve the conductivity of the first portion of the first semiconductor layer covering the top of the first type of pyramid, reduce the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and further facilitate reducing the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, in the first semiconductor layer, at least the second portion has a relatively small crystallization degree. In the case of crystallization treatment at a reduced temperature, at least the second portion has a relatively high hydrogen content, so that at least the second portion has a relatively high passivation effect on the textured surface. Therefore, according to the requirements for the passivation effect and transmission loss of the first semiconductor layer in the actual application scenario, the crystallization degree, grain size, crystallization depth, etc. of different parts of the first semiconductor layer can be determined.

[0084] In terms of the grain size, the first portion of the first semiconductor layer contains grains, and the maximum size of the grains may be equal to the thickness of the first portion. At this time, the first portion of the first semiconductor layer has relatively high conductivity, which can further reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material.

[0085] Or, as Figure 2As shown, the maximum size of the grains in the first part of the first semiconductor layer 14 can also be smaller than the thickness of the first part. In this case, during the actual manufacturing process, the larger the grain size in the first part of the first semiconductor layer 14, the higher the temperature during the crystallization process of the first part of the first semiconductor layer 14. And the higher the processing temperature, the greater the amount of hydrogen escaping from the first part of the first semiconductor layer 14, resulting in a reduction in the passivation effect of the first part of the first semiconductor layer 14 on the semiconductor substrate. Therefore, compared with the case where the grain size in the first part of the first semiconductor layer 14 is equal to the thickness of the first part, when the grain size in the first part of the first semiconductor layer 14 is smaller than the thickness of the first part, the corresponding crystallization temperature of the first semiconductor layer 14 is lower, which is beneficial for making the first part of the first semiconductor layer 14 have higher conductivity and effective doping concentration, reducing the transmission loss between the first part of the first semiconductor layer 14 and the conductive material, while making the part of the first semiconductor layer 14 where no grains grow have a passivation effect on the semiconductor substrate, which is beneficial for balancing the passivation effect and transmission loss corresponding to the first semiconductor layer 14, and further improving the working performance of the solar cell.

[0086] As for the specific value of the grain size in the first semiconductor layer, it can be determined according to the thickness of the first semiconductor layer in the actual application scenario, as well as the requirements for the passivation effect and transmission loss of the first semiconductor layer, and no specific limitation is made here.

[0087] Exemplarily, the grain size in the first semiconductor layer can be less than or equal to 50 nm. For example: the grain size in the first semiconductor layer can be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 30 nm, 40 nm or 50 nm, etc.

[0088] In terms of the crystallization depth, the crystallization depth of the first part of the first semiconductor layer can be equal to the thickness of the part. Or, the crystallization depth of the first part of the first semiconductor layer can be smaller than the thickness of the first part. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects when the grain size in the first part of the first semiconductor layer is smaller than the thickness of the first part described above, and will not be elaborated here.

[0089] Among them, the crystallization depth of each region of the first part of the first semiconductor layer can be the same. Or, as Figure 2As shown, the crystallization depth of the first part of the first semiconductor layer 14 (i.e., the part with a greater degree of crystallization) gradually decreases along the inclined direction of the side surface of the first type of pyramid and towards the base of the first type of pyramid. In this case, when crystallizing at least part of the first semiconductor layer 14, the processing temperature of each part of the first semiconductor layer 14 covering the pyramid-like structure 13 gradually decreases along the inclined direction of the side surface of the pyramid-like structure 13 and towards the base of the pyramid-like structure 13. In the case where the first part with a greater degree of crystallization of the first semiconductor layer 14 has high conductivity and an effective doping concentration, it is beneficial to reduce the influence of the high temperature during the crystallization process on the remaining part of the first semiconductor layer 14, ensuring that the remaining part of the first semiconductor layer 14 has a high hydrogen content, so that the remaining part of the first semiconductor layer 14 has a high passivation effect on the semiconductor substrate 11.

[0090] Thus, when the grain sizes and crystallization depths of the parts of the first semiconductor layer covering the top of the first type of pyramid are different, they respectively correspond to different beneficial effects. Appropriate grain sizes and crystallization depths can be obtained by adjusting the manufacturing parameters according to the requirements of the actual application scenario, improving the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. In addition, when the first semiconductor layer includes the first intrinsic passivation layer and the first doped semiconductor layer, and the crystallization depth is less than the thickness of the first part, along the direction towards the textured surface, the maximum crystallization depth of the first part of the first semiconductor layer with a greater degree of crystallization can be less than or equal to the thickness of the first doped semiconductor layer. At this time, the first intrinsic semiconductor layer corresponding to the part of the first semiconductor layer with a greater degree of crystallization still has a passivation effect on the semiconductor substrate, and can further reduce the carrier recombination rate. Along the direction towards the textured surface, the grain size of the first part of the first semiconductor layer with a greater degree of crystallization can be less than or equal to the thickness of the first doped semiconductor layer.

[0091] In addition, during the actual application process, the first part with a greater degree of crystallization in the first semiconductor layer can be disposed only above the top of the partial class pyramids included in the textured surface (i.e., at this time, the multiple class pyramids include, in addition to the first-class pyramids, the remaining class pyramids), or can be disposed above the tops of all the class pyramids included in the textured surface (i.e., at this time, the multiple class pyramids only include the first-class pyramids). The number of the first-class pyramids corresponding to the first part with a greater degree of crystallization in the first semiconductor layer can be determined according to the distribution and height of different class pyramids during the actual manufacturing process. Additionally, as described above, although the first part with a greater degree of crystallization in the first semiconductor layer can reduce the transmission loss between the first semiconductor layer and the conductive material, the passivation effect of the first part with a greater degree of crystallization in the first semiconductor layer on the semiconductor substrate is relatively weak (compared with the second part with a smaller degree of crystallization in the first semiconductor layer). Based on this, the setting range of the first part with a greater degree of crystallization in the first semiconductor layer at the top of the first-class pyramids can be determined according to the requirements for the passivation effect and transmission loss corresponding to the first semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0092] Exemplarily, along the inclined direction of the side surface of the first-class pyramid, the ratio of the maximum extension length of the first part of the first semiconductor layer on the side surface of the first-class pyramid located below itself to the length of the side surface of the first-class pyramid can be less than or equal to 0.3. For example: the ratio of the maximum extension length of the first part of the first semiconductor layer on the side surface of the first-class pyramid located below itself to the length of the side surface of the first-class pyramid can be 0.05, 0.1, 0.15, 0.2, 0.25, or 0.3, etc. In this case, a relatively large coverage range of the first part in the first semiconductor layer on the textured surface can be achieved, and the number of surface defects on the textured surface can be further reduced. Additionally, during the actual manufacturing process, the heating rate at the top of the class pyramid is faster than that of its own substrate, and it is easier to accumulate more heat at its own top to make its crystallization degree higher. Based on this, when the ratio of the maximum extension length of the first part of the first semiconductor layer on the side surface of the first-class pyramid located below itself to the length of the side surface of the first-class pyramid is less than or equal to 0.3 along the inclined direction of the side surface of the first-class pyramid, it can prevent the first part of the first semiconductor layer above the first-class pyramid from overheating due to a large extension length, which affects its own passivation effect, and ensure that the first part of the first semiconductor layer at the top of the first-class pyramid also has a certain passivation effect, further improving the working efficiency of the solar cell.

[0093] In terms of conductivity type, the embodiment of the present invention does not limit the conductivity type of the first doped semiconductor layer included in the first semiconductor layer. Specifically, the conductivity type of the first doped semiconductor layer included in the first semiconductor layer can be opposite to or the same as the conductivity type of the semiconductor substrate.

[0094] In addition, when the first surface and the second surface of the semiconductor substrate are not the target surfaces at the same time, such as Figure 15 and Figure 16 As shown, the solar cell may further include a second semiconductor layer 20 having a conductivity type opposite to that of the first semiconductor layer 14. The second semiconductor layer 20 may be disposed on the semiconductor substrate 11 at a position that is determined according to the type of solar cell and actual needs, and is not specifically limited here.

[0095] Specifically, if Figure 16 As shown, in the case where the solar cell is a double-sided contact cell, the first semiconductor layer 14 and the second semiconductor layer 20 are respectively disposed on two opposite sides of the semiconductor substrate 11 .

[0096] Or, if Figure 15 As shown, in the case where the solar cell is a back contact cell, the second semiconductor layer 20 and the first semiconductor layer 14 are arranged on the same surface of the semiconductor substrate 11. In this case, the solar cell provided by the embodiment of the present invention is a back contact cell, which can reduce the influence of the light shielding electrode structure on the light utilization rate on the light side, and further improve the photoelectric conversion efficiency of the solar cell. Figure 17 As shown, the first semiconductor layer 14 and the second semiconductor layer 20 may be spaced apart and distributed in a direction parallel to the target surface 12; or Figure 15 As shown, the first semiconductor layer 14 may also extend to cover the portion of the second semiconductor layer 20 that is away from the semiconductor substrate 11. In this case, when the first semiconductor layer 14 is formed, the amount of selective etching of the first semiconductor material used to manufacture the first semiconductor layer 14 and arranged in the entire layer may be reduced, which is beneficial to improving the manufacturing efficiency of the solar cell.

[0097] Among them, Figure 18 and Figure 19As shown, when the first semiconductor layer 14 extends to cover a part of the second semiconductor layer 20 on the side facing away from the semiconductor substrate 11, the part of the first semiconductor layer 14 extending onto the second semiconductor layer 20 can be isolated by an insulating layer 21 such as silicon oxide or silicon nitride, or the first doped semiconductor layer 19 included in the first semiconductor layer 14 can also be isolated by the first intrinsic semiconductor layer 18. Specifically, in the case where the first doped semiconductor layer 19 included in the first semiconductor layer 14 is isolated by the first intrinsic semiconductor layer 18, it can be understood that the thickness of the first intrinsic semiconductor layer 18 not only affects the transmission loss of carriers through the first intrinsic semiconductor layer 18 to the first doped semiconductor layer 19, but also affects the passivation effect of the first intrinsic semiconductor layer 18, and also affects its own leakage isolation effect on the first doped semiconductor layer 19 and the second semiconductor layer 20. Based on this, in the first semiconductor layer 14, the first part covering the top of the first type of pyramid and having a greater degree of crystallization has higher conductivity. On the premise of reducing the transmission loss between the first part and the conductive material, while ensuring that the working efficiency of the solar cell provided by the embodiment of the present invention is not reduced compared with that of the existing solar cell, the setting of the first part with a greater degree of crystallization can reserve an adjustable space for thickening the thickness of the first intrinsic semiconductor layer 18. It can not only further suppress the leakage between the first doped semiconductor layer 19 and the second semiconductor layer 20 through the first intrinsic semiconductor layer 18 with a larger thickness, but also improve the passivation effect of the first intrinsic semiconductor layer 18 on the semiconductor substrate 11 and reduce the carrier recombination rate.

[0098] Specifically, as Figure 18 shown, the above-mentioned second semiconductor layer 20 can be a single-layer structure. In this case, the second semiconductor layer 20 can only include the second doped semiconductor layer. Alternatively, the second semiconductor layer can also be a stack composed of at least two film layers. Exemplarily, as Figure 19 shown, the above-mentioned second semiconductor layer 20 can include: an interface passivation layer 22 and a second doped semiconductor layer 23. The second doped semiconductor layer 23 is disposed on the side of the interface passivation layer 22 facing away from the semiconductor substrate 11. In this case, the interface passivation layer 22 and the second doped semiconductor layer 23 can form a selective contact structure, having an excellent interface passivation effect, and capable of realizing selective collection of carriers, reducing the carrier recombination rate in the region of the semiconductor substrate 11 where the second semiconductor layer 20 is formed, and further improving the photoelectric conversion efficiency of the solar cell.

[0099] In terms of materials, the material of the second semiconductor layer can be the same as or different from that of the first semiconductor layer. When the material of the second semiconductor layer is different from that of the first semiconductor layer, the material of the second semiconductor layer can include any semiconductor material different from the first semiconductor layer. Exemplarily, the material of the second semiconductor layer can include at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. At this time, there are multiple possible examples of the material of the second semiconductor layer, which is beneficial to improving the applicability of the solar cell provided by the present invention in different application scenarios.

[0100] Preferably, when the solar cell provided by the embodiment of the present invention is a back contact cell, the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer, and the second semiconductor layer includes an interface passivation layer and a second doped semiconductor layer. Among them, the interface passivation layer includes a tunneling passivation layer, and the second doped semiconductor layer includes a doped polycrystalline silicon layer.

[0101] Regarding the surface morphology of the semiconductor substrate where the second semiconductor layer is formed, the embodiment of the present invention does not specifically limit the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer. Exemplarily, the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer can be a polished surface, a textured surface, or an uneven curved surface, etc. Among them, when the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer is a textured surface and the material of the second semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, the crystallization degree of the first part of the second semiconductor layer covering at least part of the top of the pseudo-pyramid can be greater than the crystallization degree of the second part covering the base of the pseudo-pyramid; or, the crystallization degrees of each part of the second semiconductor layer can be substantially the same. Specifically, when the crystallization degree of the first part of the second semiconductor layer covering at least part of the top of the pseudo-pyramid can be greater than the crystallization degree of the second part covering the base of the pseudo-pyramid, the characteristics such as the crystallization degree size, grain size, and crystallization depth of the first part and the second part of the second semiconductor layer, as well as the distribution of the first part, can refer to the corresponding situation of the first part and the second part included in the first semiconductor layer described above, and will not be elaborated here.

[0102] It should be noted that when the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is the same as the conductivity type of the semiconductor substrate, the solar cell includes the above-mentioned second semiconductor layer. When the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is opposite to the conductivity type of the semiconductor substrate, the solar cell may or may not include the above-mentioned second semiconductor layer.

[0103] Regarding the thickness of the first semiconductor layer, the embodiment of the present invention does not specifically limit the thickness of the first semiconductor layer, which can be determined according to the type of the solar cell in the actual application scenario and the requirements for the passivation effect and transmission loss of the first semiconductor layer.

[0104] Exemplarily, the thickness of the first semiconductor layer may be greater than or equal to 10 nm, and / or less than or equal to 45 nm. For example, the thickness of the first semiconductor layer may be 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc. In this case, the lower limit and / or upper limit of the thickness of the first semiconductor layer including amorphous silicon and / or nanocrystalline silicon is larger, which is beneficial to reducing the thermal impact of heat on the semiconductor substrate through the thicker first semiconductor layer, preventing thermal damage to the semiconductor substrate during the crystallization process of at least part of the first semiconductor layer, and ensuring a high yield of the solar cell. Moreover, the thicker first semiconductor layer has a higher passivation effect, which can further reduce the carrier recombination rate at the textured surface and further improve the working efficiency of the solar cell.

[0105] In terms of surface topography, the surface roughness of each part of the surface of the first semiconductor layer facing away from the semiconductor substrate may be substantially the same. Or, as Figure 2 shown, the surface roughness of the first part of the first semiconductor layer 14 may also be greater than the surface roughness of the second part. In this case, the specific surface area of the first part of the first semiconductor layer 14 is larger, which is beneficial to increasing the contact area between the first part and the conductive material, reducing the contact resistance between the first part and the conductive material, further reducing the transmission loss of carriers from the first semiconductor layer 14 to the conductive material, and further improving the working efficiency of the solar cell. Additionally, in the actual manufacturing process, laser irradiation or high-temperature annealing, etc. are required to achieve the crystallization modification of part of the first semiconductor layer 14, and the heating rate at the top of the pyramidal structure 13 is faster than that of its own substrate, making it easier to achieve crystallization modification; moreover, the change in the surface roughness of the first part is related to the change in the crystallization degree of the first part and the escape of hydrogen within itself. Based on this, when the surface roughness of the first part is greater than the surface roughness of the second part, there is no need to cause dehydrogenation due to the longer heating time of each part of the first semiconductor layer 14 in order to make the second part covering the base of the first type of pyramidal structure also have a large surface roughness, ensuring that the first semiconductor layer 14 has a high passivation effect. At this time, the difference between the surface roughness of the first part and the surface roughness of the second part can be determined according to the difference in the crystallization degree of the first part and the second part and the actual application scenario, which will not be elaborated here.

[0106] As a possible implementation scheme, as Figure 20As shown, the above solar cell may further include a transparent conductive layer 17, and the transparent conductive layer 17 covers at least one side of the first semiconductor layer 14 facing away from the semiconductor substrate 11. In this case, the transparent conductive layer 17 has a high conductivity, can timely export the carriers collected by the first semiconductor layer 14, and can reduce the carrier recombination rate.

[0107] In the actual application process, the embodiments of the present invention do not specifically limit the material and thickness of the transparent conductive layer, as long as it can be applied to the solar cell provided by the embodiments of the present invention. It should be noted that when the solar cell provided by the embodiments of the present invention is a back contact cell, the transparent conductive layer may only cover one side of the first semiconductor layer facing away from the semiconductor substrate. Or, as Figure 20 shown, the transparent conductive layer 17 not only covers one side of the first semiconductor layer 14 facing away from the semiconductor substrate 11, but also covers one side of the second semiconductor layer 20 facing away from the semiconductor substrate 11, and an insulating groove is provided in the transparent conductive layer 17 to separate the portions of the transparent conductive layer 17 covering the first semiconductor layer 14 and the second semiconductor layer 20 respectively to prevent short circuit.

[0108] Second, the embodiments of the present invention provide a manufacturing method of a solar cell. The manufacturing method of the solar cell includes the following steps: First, provide a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces. At least one of the first surface and the second surface is a target surface. At least a partial area of the surface of the target surface is a matte surface. A plurality of pseudo pyramids are formed on the matte surface, and the plurality of pseudo pyramids include a plurality of first pseudo pyramids. Next, form a first semiconductor layer on the matte surface. The material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes a first portion covering the top of the first pseudo pyramid and a second portion covering the base of the first pseudo pyramid, and the crystallization degree of the first portion is greater than that of the second portion.

[0109] Specifically, the structure, materials, etc. of the solar cell manufactured by using the manufacturing method provided by the embodiments of the present invention can refer to the description of the structure, materials, etc. of the solar cell provided in the first aspect above, and will not be elaborated here.

[0110] Among them, the specific process of forming the first semiconductor layer can be determined according to the type of the manufactured solar cell.

[0111] Exemplarily, in the case where the manufactured solar cell is a double-sided contact cell, after forming a textured surface on at least a partial region of the surface of the target side of the semiconductor substrate, a first semiconductor material layer disposed as a whole layer on the target side can be formed by processes such as chemical vapor deposition. When only a partial region of the target side is textured, after forming the first semiconductor material layer, processes such as laser or wet etching can be used to selectively etch the first semiconductor material layer to remove the portion of the first semiconductor material layer that does not correspond to the textured surface. If all regions of the target side are textured, the above-mentioned first semiconductor material layer disposed as a whole layer is the first semiconductor layer. Then, after obtaining the first semiconductor layer, a laser irradiation process can be used to crystallize at least a part of the first semiconductor layer so that the crystallization degree of the first part of the first semiconductor layer is greater than that of the second part. Specifically, the first semiconductor layer generates heat after absorbing light, causing its own temperature to rise. When the temperature rises to a certain level, the first semiconductor layer will present a crystalline state. Moreover, due to the reflection of the laser on the surface of the pseudo-pyramid and the difference in the heat dissipation speed at different positions of the pseudo-pyramid (the heat dissipation speed at the top of the pseudo-pyramid is slower, and the heat dissipation speed at the base of the pseudo-pyramid is faster), the temperature of the first part of the first semiconductor layer covering the top of the first type of pyramid is higher than that of the parts at other positions. Therefore, the first part of the first semiconductor layer covering the top of the first type of pyramid has a greater crystallization degree.

[0112] Specifically, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined according to requirements such as the extension range of the first part of the first semiconductor layer covering the top of the first type of pyramid and having a greater crystallization degree in the actual application scenario, and no specific limitation is made here. It can be understood that when the processing wavelength of the laser irradiation process is smaller, the pulse width is larger, the laser energy density is higher, and the processing time is longer, when using the laser irradiation process to process the first semiconductor layer, the temperature increase degree of the first semiconductor layer is greater, which is more conducive to forming a first part with a greater crystallization depth and a longer extension length.

[0113] Exemplarily, the processing wavelength of the laser irradiation process can be greater than or equal to 325 nm and less than or equal to 532 nm. For example: the processing wavelength can be 325 nm, 330 nm, 350 nm, 80 nm, 400 nm, 430 nm, 450 nm, 480 nm, 500 nm, or 532 nm, etc.

[0114] Exemplarily, the pulse width of the laser irradiation process can be picosecond-level or nanosecond-level. For example: the pulse width can be 10 ps, 50 ps, 100 ps, 300 ps, 500 ps, 800 ps, 1 ns, or 5 ns, etc.

[0115] Exemplarily, the laser energy density of the laser irradiation process can be greater than or equal to 200 mJ / cm 2 and less than or equal to 6000 mJ / cm 2 . For example, the laser energy density can be 200 mJ / cm 2 , 240 mJ / cm 2 , 280 mJ / cm 2 , 300 mJ / cm 2 , 400 mJ / cm 2 , 500 mJ / cm 2 , 1000 mJ / cm 2 , 2000 mJ / cm 2 , 3000 mJ / cm 2 , 4000 mJ / cm 2 , 5000 mJ / cm 2 or 6000 mJ / cm 2 etc.

[0116] In addition, in the case where the manufactured solar cell is a double-sided contact cell, if the solar cell further includes a second semiconductor layer, the second semiconductor layer can be formed on the side of the semiconductor substrate facing away from the first semiconductor layer by at least using a doping process before or after forming the first semiconductor layer.

[0117] Exemplarily, in the case where the manufactured solar cell is a back contact cell, if the first semiconductor layer and the second semiconductor layer are spaced apart in a direction parallel to the first surface, the first semiconductor layer and the second semiconductor layer can be formed respectively by the method of forming the first semiconductor layer in a local area of the target surface described above. Then, a laser irradiation process can be used to crystallize at least part of the first semiconductor layer, so that the crystallization degree of the first part of the first semiconductor layer covering the top of the first type of pyramid is greater than the crystallization degree of the second part of the first semiconductor layer covering the base of the first type of pyramid. If the first semiconductor layer extends to cover part of the second semiconductor layer, a deposition process and a doping process can be used to form a second semiconductor material layer provided as a whole layer on the target surface, and then a process such as laser or wet etching can be used to selectively remove part of the second semiconductor material layer to expose the area of the semiconductor substrate for manufacturing the first semiconductor layer. Then, under the masking action of the corresponding mask layer, at least the area of the semiconductor substrate for manufacturing the first semiconductor layer is textured so that a textured surface is formed on the surface of part of the target area. Then, the first semiconductor layer can be formed in the manner described above, and the crystallization degree of the first part of the first semiconductor layer covering the top of the first type of pyramid is greater than the crystallization degree of the second part of the first semiconductor layer covering the base of the first type of pyramid. In this case, the parameter settings of the laser irradiation process can refer to the above, and will not be elaborated here.

[0118] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference may be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated herein.

[0119] For the beneficial effects of the third aspect and its various implementation manners in the embodiments of the present invention, reference may be made to the analysis of the corresponding beneficial effects in the first aspect and its various implementation manners, which will not be elaborated herein.

[0120] In the above description, no detailed description is made of the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0121] The above describes the embodiments of the present invention. However, these embodiments are only for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; At least a part of the target surface is a velvet surface, and a plurality of pyramid-like surfaces are formed on the velvet surface; And a first semiconductor layer is arranged on the velvet surface, the material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon; the multiple pyramid-like layers include multiple first-type pyramids, the first semiconductor layer includes a first part covering the top of the first-type pyramid and a second part covering the base of the first-type pyramid, and the degree of crystallization of the first part is greater than that of the second part.

2. The solar cell according to claim 1, characterized in that The first portion contains grains, and the maximum size of the grains is smaller than the thickness of the first portion.

3. The solar cell according to claim 1, characterized in that Along the inclination direction of the side surface of the pyramid-like pyramid, a ratio between a maximum extension length of the first part on the side surface of the first-type pyramid below the first part and a length of the side surface of the first-type pyramid is less than or equal to 0.

3.

4. The solar cell according to claim 1, characterized in that The thickness of the first semiconductor layer is greater than or equal to 10 nm, and / or the thickness of the first semiconductor layer is less than or equal to 45 nm.

5. The solar cell according to claim 1, characterized in that: The solar cell further includes a transparent conductive layer, and the transparent conductive layer at least covers a side of the first semiconductor layer facing away from the semiconductor substrate.

6. The solar cell according to claim 1, characterized in that The quasi-pyramid is a pyramid with a sharp vertex angle; Or, the quasi-pyramid is a quasi-pyramid with rounded chamfers; Alternatively, the quasi-pyramid is a quasi-pyramid with flattened top corners.

7. The solar cell according to claim 1, characterized in that The surface of the pyramid-like structure is a plane; And / or, the surface roughness of the first portion is greater than the surface roughness of the second portion.

8. The solar cell according to any one of claims 1 to 7, characterized in that: The first semiconductor layer comprises: a first intrinsic semiconductor layer and a first doped semiconductor layer; the first doped semiconductor layer is arranged on a side of the first intrinsic semiconductor layer away from the semiconductor substrate; Along a direction close to the texture surface, a maximum size of grains contained in the first portion is less than or equal to a thickness of the first doped semiconductor layer.

9. The solar cell according to any one of claims 1 to 7, characterized in that: The solar cell further comprises a second semiconductor layer of opposite conductivity type to the first semiconductor layer; The second semiconductor layer and the first semiconductor layer are arranged on the same surface of the semiconductor substrate, and the first semiconductor layer extends to cover a portion of the second semiconductor layer facing away from the semiconductor substrate; and / or the second semiconductor layer is arranged on the second surface of the semiconductor substrate, and the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

10. The solar cell according to any one of claims 1 to 7, characterized in that: The material of the first part includes nanocrystalline silicon; the material of the second part is amorphous silicon.

11. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; At least a part of the target surface is a velvet surface; a plurality of pyramid-like structures are formed on the velvet surface; the plurality of pyramid-like structures include a plurality of first-type pyramids, A first semiconductor layer is formed on the velvet surface, wherein the material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon; the first semiconductor layer includes a first part covering the top of the first type of pyramid and a second part covering the base of the first type of pyramid, and the degree of crystallization of the first part is greater than that of the second part.

12. The method for manufacturing a solar cell according to claim 11, characterized in that: A laser irradiation process is used to crystallize at least a portion of the first semiconductor layer, so that the degree of crystallization of the first portion is greater than that of the second portion.

13. The method for manufacturing a solar cell according to claim 12, characterized in that: The wavelength of the laser used in the laser irradiation process is greater than or equal to 325nm and less than or equal to 532nm; And / or, the pulse width of the laser irradiation process is in the picosecond level or nanosecond level; And / or, the laser energy density of the laser irradiation process is greater than or equal to 200 mJ / cm 2 , and less than or equal to 6000mJ / cm 2 .

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