Time delay reporting method and device

Abstract

The embodiment of the invention provides a time delay reporting method, and the method comprises the steps: reporting target time delays corresponding to data at a plurality of specific positions in a data stream, and enabling the specific positions to be spaced by a fixed length; wherein the period of the plurality of specific positions corresponds to the length of one or more convolution interleaving sequences, and the specific positions correspond to a delay line with the maximum or minimum time delay introduced in convolution interleaving; or, the period of the plurality of specific positions corresponds to the length of one or more distribution sequences, and each distribution sequence corresponds to eight distributed subsequences; or the period of the plurality of specific positions corresponds to an integral multiple of N data blocks, each data block in the N data blocks corresponds to a forward error correction (FEC) code word, N is a positive integer, and the length of each data block is 120 bits, or 128 bits, or 110 bits, or 126 bits. By using the scheme, the time delay can be accurately reported.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 202410565639.8 and the invention title "A Delay Reporting Method and Device", which was filed with the National Intellectual Property Administration on May 8, 2024. The entire content of this Chinese patent application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and in particular, to a delay reporting method and device. Background Art

[0003] Data interaction can occur between communication devices. The sending end can send a message to the receiving end. The sending end can add the sending timestamp of the message to the message sent to the receiving end. Correspondingly, after the receiving end receives the message sent by the sending end, it can record the receiving timestamp of the message for subsequent processing measures based on the sending timestamp and the receiving timestamp. For example, in a time synchronization scenario, the receiving end can perform time synchronization based on the sending timestamp and the receiving timestamp. Herein, the sending end can be understood as the communication device acting as the sending end, and the receiving end can be understood as the communication device acting as the receiving end.

[0004] The accuracy of the aforementioned sending timestamp and the accuracy of the receiving timestamp directly affect the accuracy of the results obtained from subsequent processing measures. For example, in a time synchronization scenario, the accuracy of the sending timestamp and the receiving timestamp directly affects the precision of time synchronization.

[0005] Therefore, how the sending end accurately determines the sending timestamp of the message and how the receiving end accurately determines the receiving timestamp of the message are problems that need to be solved urgently at present. Summary of the Invention

[0006] Embodiments of this application provide a delay reporting method and device that can accurately report the delay.

[0007] In a first aspect, the present application provides a method for delay reporting, which can be applied to a first module. The first module can report the target delays corresponding to the data at multiple specific positions in a data stream, and there is a fixed length interval between the multiple specific positions. In a specific example, the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences. When the first module corresponds to the sending end, the specific positions correspond to the delay lines with the maximum delay introduced in the convolutional interleaving. When the first module corresponds to the receiving end, the specific positions correspond to the delay lines with the minimum delay introduced in the convolutional interleaving. In this scenario, when the first module corresponds to the sending end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay introduced by the convolutional interleaving operation. When the first module corresponds to the receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay introduced by the inverse convolutional deinterleaving operation. In yet another specific example, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 sub-sequences after distribution. In this scenario, when the first module corresponds to the sending end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay introduced by the distribution operation. When the first module corresponds to the receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay introduced by the multiplexing operation. In yet another specific example, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction (FEC) codeword. N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits. In this scenario, when the first module corresponds to the sending end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay introduced by the inner code FEC encoding operation. When the first module corresponds to the receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay introduced by the FEC inner code decoding operation. Therefore, in the embodiments of the present application, if the first module corresponds to the sending end, the target delay corresponding to the data at the specific position is equivalent to the maximum delay. If the first module corresponds to the receiving end, the target delay corresponding to the data at the specific position is equivalent to the minimum delay. Thus, it can be seen that the accurate delay reporting can be achieved by using this solution.

[0008] In a possible implementation, the convolutional interleaving corresponds to three delay lines, and the delay line with the maximum or minimum introduced delay is the first delay line among the three delay lines in the convolutional interleaving. Specifically, when the first module corresponds to the sending end, the delay line with the maximum introduced delay is the first delay line among the three delay lines in the convolutional interleaving. When the first module corresponds to the receiving end, the delay line with the minimum introduced delay is the first delay line among the three delay lines in the convolutional interleaving.

[0009] In a possible implementation, for the transmitting end, when performing convolutional interleaving operation, the first delay line is used to delay each data unit it receives by 2*Q*D bits, the second delay line among the three delay lines is used to delay each data unit it receives by Q*D bits, and the third delay line among the three delay lines does not perform a delay operation on each data unit it receives. D is the number of bits included in each data unit, and Q is a positive integer. For the receiving end, when performing inverse convolutional deinterleaving operation, the third delay line is used to delay each data unit it receives by 2*Q*D bits, the second delay line is used to delay each data unit it receives by Q*D bits, and the first delay line does not perform a delay operation on each data unit it receives.

[0010] In an example, the value of Q is related to the interface rate. When the interface rate corresponds to 200G BASE-R, Q = 544. When the interface rate corresponds to 400G BASE-R, Q = 272. When the interface rate corresponds to 800G BASE-R, Q = 136. When the interface rate corresponds to 1.6T BASE-R, Q = 68.

[0011] In a possible implementation, convolutional interleaving corresponds to three delay lines, and the delay line with the maximum or minimum introduced time delay is the third delay line among the three delay lines in convolutional interleaving. Specifically, when the first module corresponds to the transmitting end, the delay line with the maximum introduced time delay is the third delay line among the three delay lines in convolutional interleaving. When the first module corresponds to the receiving end, the delay line with the minimum introduced time delay is the third delay line among the three delay lines in convolutional interleaving.

[0012] In a possible implementation, for the transmitting end, when performing convolutional interleaving operation, the first delay line does not perform a delay operation on each data unit it receives, the second delay line among the three delay lines is used to delay each data unit it receives by 6*D bits, and the third delay line among the three delay lines is used to delay each data unit it receives by 12*D bits. D is the number of bits included in each data unit. For the receiving end, when performing convolutional interleaving operation, the third delay line does not perform a delay operation on each data unit it receives, the second delay line is used to delay each data unit it receives by 6*D bits, and the first delay line is used to delay each data unit it receives by 12*D bits.

[0013] In a possible implementation, the number of data units included in each of the convolutional interleaved sequences is equal to the number of delayed rows in the convolutional interleaving. For example, the number of delayed rows can be 3 rows. In this scenario, each convolutional interleaved sequence can include 3 data units. In an example, each of the 3 data units includes 40 bits. In other words, each convolutional interleaved sequence can include 120 bits.

[0014] In a possible implementation, the sender can perform a 1:8 distribution operation on a distribution sequence, that is, distribute the distribution sequence to 8 streams. In this scenario, each distribution sequence can include 8 data blocks, and each stream can be distributed one data block. Among them, the data block distributed in each stream can also be referred to as a subsequence of the distribution sequence. In other words, after a 1:8 distribution operation is performed on a distribution sequence, 8 subsequences can be obtained. Correspondingly, the receiver can perform an 8:1 multiplexing operation on the data blocks on 8 streams to obtain the distribution sequence. In this scenario, since the waiting delay of the data block distributed on the first stream is the longest when the sender performs the 1:8 distribution operation, and the waiting delay of the data block on the first stream is the shortest when the receiver performs the 8:1 multiplexing operation, the specific position can correspond to the first stream among the foregoing 8 streams.

[0015] In a possible implementation, if the sender needs to perform 8:1 codeword interleaving after performing inner code FEC encoding, the value of the foregoing N can be 8. In other words, the period of the multiple specific positions corresponds to an integer multiple of 8 data blocks, and each of the 8 data blocks corresponds to an FEC codeword.

[0016] In a possible implementation, if the sender needs to perform 32:1 codeword interleaving after performing inner code FEC encoding, the value of the foregoing N can be 32. In other words, the period of the multiple specific positions corresponds to an integer multiple of 32 data blocks, and each of the 32 data blocks corresponds to an FEC codeword.

[0017] In a possible implementation, the FEC codeword is an FEC inner codeword that is processed by outer code FEC encoding and then performs inner code FEC encoding. In this scenario, the foregoing data stream can be a data stream that has been processed by outer code FEC encoding and is received by the module performing inner code FEC through an attachment unit interface (AUI).

[0018] In a possible implementation, the FEC inner codeword is a Hamming codeword. In a specific example, the sender can perform inner code FEC encoding using Hamming code encoding and perform 8:1 codeword interleaving on the obtained FEC inner codeword.

[0019] In a possible implementation, the FEC inner codeword is a Bose Chaudhuri Hocquenghem (BCH) codeword. In a specific example, the transmitting end can perform inner code FEC encoding using BCH code encoding and perform 32:1 codeword interleaving on the obtained FEC inner codeword.

[0020] In a possible implementation, after the receiving end receives the FEC inner codeword that has undergone inner code FEC encoding, it can perform inner code FEC decoding on the FEC inner codeword. In an example, if the foregoing first module corresponds to the receiving end, the foregoing data stream can also be the data stream obtained by the receiving end performing inner code FEC decoding.

[0021] In a possible implementation, considering that for the transmitting end, when it performs convolutional interleaving operation, the time delay introduced by the starting position of the convolutional interleaving sequence is the largest. For the receiving end, when it performs inverse convolutional deinterleaving operation, the time delay introduced by the starting position of the convolutional interleaving sequence is the smallest. Therefore, the specific position corresponds to the starting position of the one or more convolutional interleaving sequences. Wherein, the starting position can be the first bit or the first symbol or the first byte.

[0022] In a possible implementation, considering that for the transmitting end, when it performs the distribution operation, the time delay introduced by the starting position of the distribution sequence is the largest. For the receiving end, when it performs the multiplexing operation, the time delay introduced by the starting position of the distribution sequence is the smallest. Therefore, the specific position corresponds to the starting position of the one or more distribution sequences.

[0023] In a possible implementation, considering that for the transmitting end, when it performs inner code FEC encoding, the time delay introduced by the starting positions of the foregoing N data blocks is the largest. For the receiving end, when it performs inner code FEC decoding, the time delay introduced by the starting positions of the foregoing N data blocks is the smallest. Therefore, the specific position corresponds to the starting positions that are integer multiples of the foregoing N data blocks.

[0024] In a possible implementation, among the data at the foregoing multiple specific positions, the data at each specific position may correspond to a first time delay. Therefore, the data at the foregoing multiple specific positions may correspond to multiple first time delays. Considering that the existing Institute of Electrical and Electronics Engineers (IEEE) 802.3cx, Chapter 90, defines corresponding maximum time delay registers and minimum time delay registers for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx, Chapter 90, mechanism for reporting the time delay of the physical layer, the maximum value and / or minimum value of the multiple first time delays may be reported. In other words, the foregoing target time delay may be the maximum value and / or minimum value of the multiple first time delays. For this case, the first module may also measure the first time delay corresponding to the data at each specific position among the data at the multiple specific positions, to obtain multiple first time delays, so as to report the maximum value and / or minimum value of the multiple first time delays, and implement the reporting of the time delay information.

[0025] In a possible implementation, when the first module reports the foregoing target time delay, in a specific implementation, the target time delay may be reported to the second module. In an example, the second module may be a media access control (MAC) layer module of a communication device. In this way, the MAC layer module may compensate the time stamp recorded by itself based on the target time delay, so that the compensated time stamp is more accurate.

[0026] In a second aspect, the present application provides a time delay reporting device, including: a sending unit, configured to report a target time delay corresponding to data at multiple specific positions in a data stream, where a fixed length is spaced between the multiple specific positions; where: the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific position corresponds to the delay line with the maximum or minimum time delay introduced in the convolutional interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 distributed subsequences; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) codeword, N is a positive integer, and the length of each data block is: 120 bits, or, 128 bits, or, 110 bits, or 126 bits.

[0027] In a possible implementation, the delay line with the maximum or minimum time delay introduced is the first delay line among the three delay lines in the convolutional interleaving.

[0028] In a possible implementation, the first delay line is used to delay each data unit it receives by 2*Q*D bits, the second delay line among the three delay lines is used to delay each data unit it receives by Q*D bits, and the third delay line among the three delay lines does not perform a delay operation on each data unit it receives, where D is the number of bits included in each data unit and Q is a positive integer; or, the third delay line is used to delay each data unit it receives by 2*Q*D bits, the second delay line is used to delay each data unit it receives by Q*D bits, and the first delay line does not perform a delay operation on each data unit it receives.

[0029] In a possible implementation, Q takes a value of 544 or 272 or 136 or 68.

[0030] In a possible implementation, the delay line with the maximum or minimum introduced time delay is the third delay line among the three delay lines in the convolutional interleaving.

[0031] In a possible implementation, the first delay line does not perform a delay operation on each data unit it receives, the second delay line among the three delay lines is used to delay each data unit it receives by 6*D bits, and the third delay line among the three delay lines is used to delay each data unit it receives by 12*D bits, where D is the number of bits included in each data unit; or, the third delay line does not perform a delay operation on each data unit it receives, the second delay line is used to delay each data unit it receives by 6*D bits, and the first delay line is used to delay each data unit it receives by 12*D bits.

[0032] In a possible implementation, each convolutional interleaving sequence includes 3 data units, and each of the 3 data units includes 40 bits.

[0033] In a possible implementation, each distribution sequence includes 8 data blocks, each distribution sequence is used to perform 1:8 distribution processing, or each distribution sequence is a sequence obtained by performing 8:1 multiplexing processing, and the specific position corresponds to the first stream among the 8 streams corresponding to the 1:8 distribution processing or 8:1 multiplexing processing.

[0034] In a possible implementation, N takes a value of 8 or 32; or the FEC codeword is an FEC inner codeword that is first processed by outer code FEC encoding and then by inner code FEC encoding; or, the FEC inner codeword is a Hamming codeword or a BCH codeword; or, the data stream is a data stream received through the Attachment Unit Interface AUI; or, the data stream is a data stream obtained by performing inner code FEC decoding.

[0035] In a possible implementation, the specific position corresponds to the starting position of the one or more convolutional interleaved sequences; or, the specific position corresponds to the starting position of the one or more distribution sequences; or, the specific position corresponds to the starting position that is an integer multiple of the N data blocks; the starting position is the first bit or the first symbol or the first byte.

[0036] In a possible implementation, the apparatus further includes: a processing unit, configured to measure a first time delay corresponding to the data at each of the multiple specific positions, and obtain multiple first time delays; wherein, the target time delay includes the maximum value and / or the minimum value of the multiple first time delays.

[0037] In a possible implementation, the sending unit is configured to: report the target time delay corresponding to the data at the multiple specific positions in the data stream to a Media Access Control (MAC) layer.

[0038] In a third aspect, an embodiment of the present application provides a time delay reporting apparatus, including a circuit, and the circuit is configured to execute the method described in the above first aspect and any item of the above first aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a physical layer (PHY) chip, and the PHY chip is configured to execute the method described in the above first aspect and any item of the above first aspect.

[0040] In a fifth aspect, an embodiment of the present application provides an optical module, and the optical module is configured to execute the method described in the above first aspect and any item of the above first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1a It is a schematic structural diagram of a communication apparatus provided by an embodiment of the present application;

[0043] Figure 1b It is a schematic structural diagram of another communication apparatus provided by an embodiment of the present application;

[0044] Figure 1c It is a schematic structural diagram of another communication apparatus provided by an embodiment of the present application;

[0045] Figure 1d Schematic diagram of operations included in an in - code FEC provided by an embodiment of this application;

[0046] Figure 1e Schematic diagram of a convolutional interleaving provided by an embodiment of this application;

[0047] Figure 1f Schematic diagram of a de - convolutional de - interleaving provided by an embodiment of this application;

[0048] Figure 1g Schematic diagram of the latency introduced by a convolutional interleaving and a de - convolutional de - interleaving provided by an embodiment of this application;

[0049] Figure 1h Schematic diagram of a 120 - bit block distribution provided by an embodiment of this application;

[0050] Figure 1i Schematic diagram of the latency introduced by a 120 - bit block distribution and a 120 - bit block multiplexing provided by an embodiment of this application;

[0051] Figure 1j Schematic diagram of the latency introduced by an in - code FEC encoding or decoding function provided by an embodiment of this application;

[0052] Figure 1k Schematic diagram of operations included in an in - code FEC provided by an embodiment of this application;

[0053] Figure 1L Schematic diagram of a convolutional interleaving provided by an embodiment of this application;

[0054] Figure 1m Schematic diagram of the latency introduced by a convolutional interleaving and a de - convolutional de - interleaving provided by an embodiment of this application;

[0055] Figure 1n Schematic diagram of the latency introduced by an in - code FEC encoding or decoding function provided by an embodiment of this application;

[0056] Figure 2 Schematic diagram of the process of a latency reporting method provided by an embodiment of this application;

[0057] Figure 3 Schematic diagram of the structure of a first module provided by an embodiment of this application;

[0058] Figure 4 Schematic diagram of the structure of a latency reporting device provided by an embodiment of this application;

[0059] Figure 5 Schematic diagram of the structure of a PHY chip or an optical module provided by an embodiment of this application;

[0060] Figure 6 Schematic diagram of the structure of a device provided by an embodiment of the present application;

[0061] Figure 7 Schematic diagram of the structure of a device provided by an embodiment of the present application. Detailed implementation manners

[0062] The embodiment of the present application provides a method and device for delay reporting, which can accurately report the delay.

[0063] For ease of understanding, first, the application scenario for reporting the delay is introduced.

[0064] In a time synchronization scenario, communication devices can perform time synchronization by interacting with messages. The communication devices mentioned in the embodiment of the present application can be network devices such as switches, routers, slicing packet network (SPN) devices, or optical transmission network (OTN) devices, or can be a part of components on the network device, such as a single board, line card, or interface on the network device, or can be a functional module on the network device, or can be a chip, or can be a pluggable optical module on the network device, or can also be a server, a network card on the server, or a network card of other devices. The embodiment of the present application does not make specific limitations. For example, the communication devices can be directly connected through an Ethernet cable or an optical cable.

[0065] The 1588 protocol is a high-precision time synchronization protocol. The 1588 protocol can provide time synchronization accuracy at the nanosecond (ns) level. Currently, the International Telecommunication Union - Telecommunication (ITU-T) G.8273.2 defines four levels (classes) of time synchronization accuracy requirements, namely class A, class B, class C, and class D. Among them, the time accuracy corresponding to class A is ±100 ns; the time accuracy corresponding to class B is ±70 ns; the time accuracy corresponding to class C is ±30 ns; the time accuracy corresponding to class D is ±5 ns. Therefore, in an example, communication devices can perform time synchronization by interacting with 1588 messages. The 1588 messages mentioned here can be understood as messages that follow the 1588 protocol.

[0066] When time synchronization is achieved by the interaction of 1588 messages between communication devices, in a specific implementation, the communication device that sends the 1588 message can add a transmission timestamp to the 1588 message, and this transmission timestamp indicates the transmission moment of the 1588 message. Correspondingly, the communication device that receives the 1588 message will record the reception timestamp of the 1588 message, and this reception timestamp indicates the reception moment of the 1588 message. Further, the communication device that receives the 1588 message can perform time synchronization based on the aforementioned transmission timestamp and reception timestamp. Since the transmission timestamp and reception timestamp are input parameters for time synchronization, therefore, the accuracy of the transmission timestamp and the reception timestamp directly affects the accuracy of time synchronization. In other words, it is particularly important to ensure the accuracy of the aforementioned transmission timestamp and reception timestamp.

[0067] Currently, the way for a communication device to record a timestamp is that the MAC layer of the communication device records the timestamp. In a specific scenario, for a communication device including an Ethernet interface, the MAC layer of the communication device can record the timestamp.

[0068] Next, in combination with the structure of the communication device, the way for the communication device to record the timestamp will be introduced.

[0069] See Figure 1a , this figure is a schematic structural diagram of a communication device provided by an embodiment of the present application, which includes the structure of a sending-end communication device and the structure of a receiving-end communication device.

[0070] As Figure 1a shown, whether it is a communication device acting as a sending end or a receiving end, it can both include a MAC layer and a physical layer, and the physical layer can further include a physical coding sublayer (PCS), a physical medium attachment (PMA), and a physical media dependent (PMD). In addition, it can also include an application layer, and the application layer can correspond to upper-layer services, for example.

[0071] As a sending end, its MAC layer can generate a MAC frame and send it to the physical layer. For example, the MAC layer can receive data sent by an upstream device or upper-layer services, and can encapsulate the data to form a MAC frame. Another example is that if the MAC layer does not receive data sent by an upstream device or upper-layer services, the MAC layer will generate a corresponding MAC frame based on an idle (IDLE) code stream.

[0072] The MAC layer of the sending end sends the MAC frame to the physical layer of the sending end. The physical layer may include PCS, PMA, and PMD. The MAC layer of the sending end may record the timestamp when it sends the MAC frame to the physical layer as the aforementioned sending timestamp.

[0073] The PCS can process the received data stream and send the processed data to the PMA. The data stream mentioned here can be a bit stream including multiple bits, and this data stream can be obtained by processing the MAC frame.

[0074] The PMA can modulate the data from the PCS into a signal supported by the channel for transmission.

[0075] The PMD is a signal transmitter for transmitting the signal modulated by the PMA through the transmission medium.

[0076] The physical layer of the receiving end receives the signal transmitted on the aforementioned transmission medium, processes the signal, and then passes it to the MAC layer of the receiving end. As described above, the physical layer of the receiving end also includes PMD, PMA, and PCS.

[0077] The PMD of the receiving end first receives the signal transmitted on the transmission medium. Then, the PMA demodulates the signal. The data obtained after the PMA demodulation is passed to the PCS, and the PCS performs corresponding operations on the received data. Among them, the operations performed by the PCS of the receiving end are the inverse operations of those performed by the PCS of the sending end. Further, the PCS may send the processed data stream to the MAC layer. At this point, after the MAC layer of the receiving end receives the data stream sent by the PCS, it can obtain the MAC frame sent by the sending end and further process the MAC frame. For example, the MAC frame is parsed and sent to the upstream device or the upper-layer service. When the MAC of the receiving end receives the data stream processed by the PCS, the MAC layer of the receiving end may record the timestamp when it receives the data stream as the receiving timestamp.

[0078] To support the high-precision time synchronization feature of 1588. The physical layer of the communication device can report the delay of the data stream passing through the physical layer to the MAC layer, so that when the MAC records the sending and receiving timestamps of the 1588 message, based on the delay of the data stream passing through the physical layer, the recorded timestamps are compensated, so that the sending and receiving timestamps of the 1588 message after the MAC layer compensation are more accurate. Specifically:

[0079] For the sending end, the MAC layer can add the aforementioned delay of the data stream passing through the physical layer to the timestamp recorded by itself to obtain the sending timestamp. It is not difficult to understand that this sending timestamp can be considered as the timestamp when the physical layer of the sending end actually sends the data stream.

[0080] For the receiving end, the MAC layer can subtract the delay of the foregoing data stream passing through the physical layer from the time stamp recorded by itself to obtain the receiving time stamp. It is not difficult to understand that this receiving time stamp can be regarded as the time stamp when the physical layer of the receiving end actually receives the data stream.

[0081] As described above, the data stream transmitted through the physical layer is a bit stream including multiple bits. The physical layer cannot identify which parts of the bit stream correspond to the 1588 message. Therefore, the physical layer cannot accurately count the delay of the 1588 message. To solve this problem, in some scenarios, it is necessary to ensure the stability of the physical layer delay. That is: the delay of the data stream passing through the physical layer is stable near a fixed value. In this way, the physical layer can report this fixed value to the MAC layer. Correspondingly, the MAC layer can perform time stamp compensation based on this fixed value.

[0082] It should be noted that for any communication device, it can act as both a sending end and a receiving end. In other words, Figure 1a the roles of the sending end and the receiving end shown can be interchanged. If Figure 1a the roles of the sending end and the receiving end shown are interchanged, the flow direction of the data stream will also change accordingly, that is: the flow direction of the data stream can be from the sending end after role interchange to the receiving end after role interchange.

[0083] In some scenarios, the PCS of the physical layer of the communication device can include an FEC function. Reference can be made to Figure 1b Figure 1b which is another schematic structural diagram of a communication device provided by an embodiment of the present application. Figure 1b The structure of the communication device shown is basically the same as that of the communication device shown in Figure 1a except that the PCS of the communication device shown in Figure 1b includes an FEC function.

[0084] For Figure 1b the communication device shown, the FEC function of the sending end will perform FEC encoding, and this encoding process includes adding check bits. In addition, the sending end will also perform a data stream interleaving operation. Similarly, the PCS of the receiving end will perform FEC decoding, and this decoding process includes deleting check bits. In addition, the receiving end will also perform a deinterleaving operation on the data stream.

[0085] In one example, the FEC function of the PCS can also be called an outer code FEC function, and the FEC codeword obtained by the PCS of the sending end performing FEC encoding can be called an FEC outer codeword.

[0086] ​In addition, the current IEEE 802.3dj Task Force (B400G standard) defines that the physical layer supports the concatenated coding function. Specifically, inner code FEC is inserted between PMA and PMD for inner code FEC encoding and decoding. As an example, the FEC codeword obtained by the inner code FEC encoding at the transmitting end can be referred to as the inner code FEC codeword.

[0087] Reference can be made to Figure 1c for understanding. Figure 1c FIG. is a schematic structural diagram of another communication device provided by an embodiment of the present application. As Figure 1c shown, the physical layer of the communication device supporting concatenated coding includes: PCS supporting the FEC function, PMA 101, PMA 102, inner code FEC, and PMD.

[0088] Among them, PMA 101 and PMA 102 interact through AUI. Among them:

[0089] PCS and PMA 101 may belong to the first chip, and PMA 102, inner code FEC, and PMD may belong to the optical module.

[0090] The inner code FEC needs to perform operations related to the inner code.

[0091] In one example, the operations included in the inner code FEC can be understood by referring to Figure 1d for understanding. Figure 1d FIG. is a schematic diagram of the operations included in an inner code FEC provided by an embodiment of the present application.

[0092] As Figure 1d shown:

[0093] For the transmitting end, the operations performed by the inner code FEC include: convolutional interweaver, 120-bit block distribution, inner code FEC processing, 8:1 pulse amplitude modulation 4 (PAM4) interweaving, 1024-bit padded data insertion, and other processings. Among them, the inner code FEC processing may include circular shift and inner code FEC encoding and other processings, and other processings include PAM4 encoding processing and the like.

[0094] Correspondingly, for the receiving end, the operations performed by the inner FEC include: other processing, inner FEC sync and pad removal, 1:8 PAM4 de-interleaving, inner FEC processing, 120-bit block multiplexing (120b block mux), and de-convolutional de-interweaving. Among them, the inner FEC processing may include processing such as cyclic shift and inner FEC decoding, and other processing includes PAM4 encoding processing, etc.

[0095] Wherein:

[0096] Convolutional interleaving involves various design parameters, including the number of delay lines, the length of the delay block, the number of delay blocks, etc. In one example, the number of delay lines for convolutional interleaving can be 3 lines, corresponding to Figure 1e and Figure 1f line0, line1, and line2 in Figure 1e and Figure 1f The length of the delay block can correspond to D in Figure 1e and Figure 1f For example, D can be 40 bits. The number of delay blocks can correspond to Q in Figure 1e and Figure 1f And the number of delay blocks for each delay line is different. Taking 3 delay lines as an example, the number of delay blocks for them can be 0, D, and 2D respectively, then the number of delayed bits is 0 (no delay operation is performed), 2 * Q * D, and Q * D respectively. Another example is that when the selected number of delay blocks is different, the number of delayed bits for each delay line can also be Figure 1L 0 (no delay operation is performed), 6 * D, and 12 * D in

[0097] As a specific example, the convolutional interleaving operation at the sending end sends every 40 bits (where every 40 bits is called a data unit) to 3 delay lines in a polling manner. Reference can be made to Figure 1e shown in Figure 1e which is a schematic diagram of a convolutional interleaving provided by an embodiment of the present application. These 3 delay lines respectively correspond to Figure 1e line0, line1, and line2 shown in Figure 1e Among them, line0 is also called the first delay line, line1 is also called the second delay line, and line2 is also called the third delay line. As shown in Figure 1e line0 (i.e., the first delay line) can send each data unit it receives (corresponding to Figure 1eD) in the leftmost and rightmost small boxes is delayed by 2*Q*D bits. Line1 (i.e., the second delay line) can delay each data unit it receives by Q*D bits, and line2 (i.e., the third delay line) does not perform a delay operation on each data unit it receives. Wherein:

[0098] D in 2*Q*D and 2*Q*D is the number of bits included in each data unit, that is, the value of D in 2*Q*D and 2*Q*D is 40. Q is a positive integer. In one example, the value of Q is related to the interface rate of the communication device. When the interface rate corresponds to 200GBASE-R, Q = 544. When the interface rate corresponds to 400G BASE-R, Q = 272. When the interface rate corresponds to 800G BASE-R, Q = 136. When the interface rate corresponds to 1.6T BASE-R, Q = 68.

[0099] Similarly, for the inverse convolutional deinterleaving operation at the receiving end, every 40 bits are also sent to the three delay lines in a polling manner. The processing operations of the three delay lines at the receiving end are opposite to those of the three delay lines at the sending end, and reference can be made to Figure 1f as shown. Figure 1f is a schematic diagram of inverse convolutional deinterleaving provided by an embodiment of the present application. As Figure 1f shown, line2 (i.e., the third delay line) can delay each data unit it receives by 2*Q*D bits, line1 (i.e., the second delay line) can delay each data unit it receives by Q*D bits, and line0 (i.e., the first delay line) does not perform a delay operation on each data unit it receives.

[0100] In one example, the 3 data units successively sent to the three delay lines can also be referred to as a convolutional interleaving sequence. In other words, when the number of delay lines is 3, a convolutional interleaving sequence can include 3 data units (i.e., 120 bits). When the number of delay lines is N, the number of data units included in the convolutional interleaving sequence is also N.

[0101] Since the three delay lines have different delays for data units during the execution of convolutional interleaving or inverse convolutional deinterleaving operations, the convolutional interleaving and inverse convolutional deinterleaving operations will introduce a time delay in the shape of a sawtooth wave. Reference can be made to Figure 1g for understanding. Figure 1g is a schematic diagram of the time delay introduced by convolutional interleaving and inverse convolutional deinterleaving provided by an embodiment of the present application. Figure 1g In the figure shown, the abscissa represents the bit stream processed by convolutional interleaving or inverse convolutional deinterleaving, and the ordinate represents the time delay. Among them, TX represents the time delay introduced by the convolutional interleaving operation at the sending end, and RX represents the time delay introduced by the inverse convolutional deinterleaving operation at the receiving end.

[0102] In Figure 1g , the period of the sawtooth wave corresponds to the length of 3 data blocks, and the time corresponding to the length of 3 data blocks is:

[0103] 3 * 40 / (106.25G * 2) ≈ 0.5647 ns.

[0104] The amplitude of the sawtooth wave is: 2 * Q * 40 / (106.25G * 2). Different Q values result in different amplitudes of the sawtooth wave. Specifically:

[0105] If Q is equal to 544, the amplitude of the sawtooth wave is: 2 * 544 * 40 / (106.25G * 2) ≈ 204.8 ns;

[0106] If Q is equal to 272, the amplitude of the sawtooth wave is: 2 * 272 * 40 / (106.25G * 2) ≈ 102.4 ns;

[0107] If Q is equal to 136, the amplitude of the sawtooth wave is: 2 * 136 * 40 / (106.25G * 2) ≈ 51.2 ns;

[0108] If Q is equal to 68, the amplitude of the sawtooth wave is: 2 * 68 * 40 / (106.25G * 2) ≈ 25.6 ns.

[0109] In the above calculation formula: 106.25G * 2 is the bit rate for convolutional interleaving (or inverse convolutional deinterleaving) of the data stream. The 2 in "2 * Q * 40" represents that 1 symbol includes 2 bits, and 40 is the number of bits included in one data unit.

[0110] As can be seen from the above description of convolutional interleaving at the sending end and inverse convolutional deinterleaving at the receiving end, for the sending end, the time delay introduced by the first delay line is the largest, and the time delay corresponding to the data at the starting position in a convolutional interleaving sequence corresponds to the maximum time delay introduced by the convolutional interleaving operation at the sending end. For the receiving end, the time delay introduced by the first delay line is the smallest, and the time delay corresponding to the data at the starting position in a convolutional interleaving sequence corresponds to the minimum time delay introduced by the inverse convolutional deinterleaving operation at the receiving end. Specifically, Figure 1g The positions circled by the hollow circles and solid circles in

[0111] correspond to the first delay line, and this position corresponds to the starting position of a convolutional interleaving sequence.

[0112] In Figure 1gAmong them, the periods of the idle circles and the solid circles both correspond to 120 bits, that is, the length of 3 data units, and the length of each data unit is 40 bits.

[0113] For the 120-bit block distribution operation at the sending end, for each data block including 120 bits, it is distributed to 8 Inner FEC flows according to the polling principle, and then sent out uniformly. Reference can be made to Figure 1h for understanding. Figure 1h This is a schematic diagram of 120-bit block distribution provided by an embodiment of the present application. As Figure 1h shown, the 8 Inner FEC flows correspond to Inner FEC flow0 to Inner FEC flow7. Among them, Inner FEC flow0 can be considered as the first flow among these 8 Inner FEC flows, Inner FEC flow1 can be considered as the second flow among these 8 Inner FEC flows, and so on. Inner FEC flow7 can be considered as the eighth flow among these 8 Inner FEC flows. As Figure 1h shown, 120-bit block 0 to 120-bit block 7 are sequentially distributed to Inner FEC flow0 to Inner FEC flow7, and 120-bit block 8 to 120-bit block 15 are sequentially distributed to Inner FEC flow0 to Inner FEC flow7. The distribution process of the 120-bit block will result in the longest data waiting delay for flow 0 and the shortest data waiting delay for flow 7. The 120-bit block multiplexing at the receiving end is the reverse process of the 120-bit block distribution. The receiving end combines the data of 8 Inner FEC flows into one path, resulting in the shortest data waiting delay for flow 0 and the longest data waiting delay for flow 7.

[0114] Since the waiting durations of the data on each Inner FEC flow at the sending end and the receiving end are different, the 120-bit block distribution and the 120-bit block multiplexing operations will introduce a delay in the shape of a sawtooth wave. Reference can be made to Figure 1i for understanding. Figure 1i This is a schematic diagram of the delay introduced by 120-bit block distribution and 120-bit block multiplexing provided by an embodiment of the present application. Figure 1i As shown, the abscissa represents the bit stream processed by 120-bit block distribution or 120-bit block multiplexing, and the ordinate represents the delay. Among them, TX represents the delay introduced by the 120-bit block distribution operation at the sending end, and RX represents the delay introduced by the 120-bit block multiplexing operation at the receiving end.

[0115] InFigure 1i In it, the period of the sawtooth wave corresponds to the length of 8 120-bit segments, and the time corresponding to the length of 8 120-bit segments is:

[0116] 8 * 120 / (106.25G * 2) ≈ 4.5176 ns.

[0117] The amplitude of the sawtooth wave is also approximately equal to 4.5176 ns.

[0118] In one example, 8 120-bit segments that are successively distributed to 8 Inner FEC flows can also be referred to as a distribution sequence. In other words, a distribution sequence can include 8 * 120 = 960 bits. That is, the length of the distribution sequence corresponds to the product of the number of data streams after distribution and the length of the convolutional interleaving sequence. When the number of streams after distribution is N, the number of bits included in the distribution sequence is also N * 120 bits.

[0119] As described above regarding the 120-bit block distribution performed by the sender and the 120-bit block multiplexing performed by the receiver, for the sender, the delay introduced by the starting position of a distribution sequence is the largest. In other words, the delay corresponding to the data at the starting position in a distribution sequence corresponds to the maximum delay introduced by the sender's 120-bit block distribution operation. For the receiver, the delay introduced by the starting position of a distribution sequence is the smallest. In other words, the delay corresponding to the data at the starting position in a distribution sequence corresponds to the minimum delay introduced by the receiver's 120-bit block multiplexing operation. Among them, the starting position in the distribution sequence corresponds to Inner FEC flow0. Specifically, Figure 1i The positions circled by the hollow circles and solid circles in

[0120] In Figure 1i correspond to the starting position of the distribution sequence and also correspond to Inner FEC flow0. The periods of both the idle circles and the solid circles in

[0121] correspond to 960 bits. For the inner code FEC encoding at the sender, for example, for every 120-bit information bits, 8-bit parity bits are inserted. Combining with the 8:1 codeword interleaving after the inner code FEC encoding is equivalent to inserting 64-bit parity bits every 960-bit information bits. On the receiving side, it is a reverse process, and 64-bit parity bits are deleted every 960-bit information bits. In this scenario, the FEC inner codeword obtained after performing the inner code FEC encoding can be a Hamming codeword.

[0122] The addition and deletion of parity bits during the inner code FEC encoding and decoding processes will introduce a sawtooth-shaped delay. For understanding, reference can be made to Figure 1j Figure 1j ​Schematic diagram of the latency introduced by the inner code FEC encoding or decoding function provided by the embodiments of this application. Wherein:

[0123] The sawtooth wave period is: 1024 / 113.4375G / 2 ≈ 4.5ns, and the sawtooth wave amplitude is approximately 64 / 113.4375G / 2 ≈ 0.28125ns.

[0124] In the formula 1024 / 113.4375G / 2:

[0125] 1024 corresponds to the number of bits contained in 8 FEC inner code codewords. One FEC inner code codeword includes 128 bits;

[0126] 113.4375G corresponds to the baud rate of a single physical channel (lane);

[0127] 2 indicates that in the scenario of PAM4 encoding of the data stream, one symbol includes 2 bits;

[0128] In the formula 64 / 113.4375G / 2:

[0129] 64 indicates that in the 8:1 codeword interleaving, the first bit of the ninth virtual lane, located at the 65th bit in the interleaved data, needs to wait for the first 64 bits to be sent before it can be sent;

[0130] 113.4375G corresponds to the baud rate of a single physical channel;

[0131] 2 indicates that one symbol includes 2 bits.

[0132] As described above for Figure 1j It can be seen that the period of the sawtooth wave corresponds to 8 data blocks, and one data block corresponds to one FEC inner code codeword that is a Hamming code codeword. For example, one data block can include 128 bits, and these 128 bits correspond to one FEC inner code codeword encoded by the Hamming code. Another example is that one data block can include 120 bits, and after these 120 bits are encoded by the Hamming code, 128 bits of FEC inner code codeword can be obtained. In Figure 1i The positions circled by the hollow circles and solid circles correspond to the starting positions of the aforementioned 8 data blocks. For the transmitting end, the latency corresponding to the position circled by the hollow circle corresponds to the maximum latency introduced by the transmitting end when performing the inner code FEC encoding operation. For the receiving end, the latency corresponding to the position circled by the solid circle corresponds to the minimum latency introduced by the receiving end when performing the FEC inner code decoding operation.

[0133] In Figure 1gAmong them, the periods of the idle circles and the solid circles both correspond to 8 data blocks. In one example, one data block includes 128 bits. In another example, one data block includes 120 bits.

[0134] Among them, the data blocks can be numbered in sequence. There are m data blocks between two adjacent circles, which can be that the difference between the numbers of the data blocks corresponding to these two adjacent circles is m. For this case, the period of the position corresponding to the aforementioned circle is also m. For example, there are 8 data blocks between the data blocks corresponding to two hollow circles, which can be that the difference between the numbers of the data blocks corresponding to these two hollow circles is 8. Correspondingly, the period of the position marked by the hollow circle is 8.

[0135] In another example, the operations included in the inner code FEC can be understood with reference to Figure 1k for understanding. Figure 1k It is a schematic diagram of the operations included in an inner code FEC provided by an embodiment of this application. Figure 1k The operations included in the inner code FEC shown have a different scenario from Figure 1d the operations included in the inner code FEC shown. Generally, Figure 1d it can be applicable to short-distance communication scenarios, Figure 1k and it can be applicable to longer-distance communication scenarios.

[0136] As Figure 1k shown:

[0137] For the transmitter, the operations performed by the inner code FEC include: alignment lock and lane deskew, lane reorder, permutation, convolutional interleaving, BCH coding, cyclic shift, BCH interleaving, pilot insertion, dual polarization 16-state quadrature amplitude modulation (DP-16QAM) coding, and digital-to-analog conversion via a digital-to-analog converter (DAC).

[0138] Correspondingly, for the receiver, the operations performed by the inner code FEC include: analog-to-digital conversion via an analog-to-digital converter (ADC), DP-16QAM decoding, BCH deinterleaving, pilot removal, cyclic shift, BCH decoding, inverse convolutional deinterleaving, and inverse permutation.

[0139] Among them:

[0140] The convolutional interleaving operation at the transmitting end sends every 40 bits (where every 40 bits is called a data unit) to 3 delay lines in a polling manner, as can be referred to Figure 1L as shown Figure 1L which is a schematic diagram of convolutional interleaving provided by an embodiment of the present application. These 3 delay lines respectively correspond to Figure 1L line0, line1, and line2 shown as follows. Among them, line0 is also called the first delay line, line1 is also called the second delay line, and line2 is also called the third delay line. As Figure 1L shown, line0 (i.e., the first delay line) does not perform a delay operation on each data unit it receives. Line1 (i.e., the second delay line) can delay each data unit it receives by 6*D bits, and line2 (i.e., the third delay line) can delay each data unit it receives by 12*D bits. Wherein: D is the number of bits included in each data unit, that is, the value of D is 40.

[0141] Similarly, the inverse convolutional deinterleaving operation at the receiving end also sends every 40 bits to three delay lines in a polling manner. The processing operations of the three delay lines at the receiving end are opposite to those of the three delay lines at the transmitting end. Line2 (i.e., the first delay line) does not perform a delay operation on each data unit it receives. Line1 (i.e., the second delay line) can delay each data unit it receives by 6*D bits, and line0 (i.e., the third delay line) can delay each data unit it receives by 12*D bits.

[0142] In one example, the 3 data units successively sent to the three delay lines can also be called a convolutional interleaving sequence. In other words, a convolutional interleaving sequence can include 3 data units (i.e., 120 bits).

[0143] Since the delays of the three delay lines for data units are different when performing convolutional interleaving or inverse convolutional deinterleaving operations, the convolutional interleaving and inverse convolutional deinterleaving operations introduce a time delay in the shape of a sawtooth wave. As can be referred to Figure 1m for understanding, Figure 1m which is a schematic diagram of the time delay introduced by convolutional interleaving and inverse convolutional deinterleaving provided by an embodiment of the present application. Figure 1m As shown, the abscissa represents the bit stream processed by convolutional interleaving or inverse convolutional deinterleaving, and the ordinate represents the time delay. Among them, TX represents the time delay introduced by the convolutional interleaving operation at the transmitting end, and RX represents the time delay introduced by the inverse convolutional deinterleaving operation at the receiving end.

[0144] In Figure 1mAmong them, the period of the sawtooth wave corresponds to the length of 3 data blocks, and the time corresponding to the length of 3 data blocks is:

[0145] 3 * 40 / (106.25G / 4) ≈ 4.5176 ns.

[0146] The amplitude of the sawtooth wave corresponds to the time of 12 * D bits: 12 * 40 / (106.25G / 4) ≈ 18.0706 ns. Among them:

[0147] 106.25G / 4 is the bit rate for performing convolutional interleaving (or inverse convolutional deinterleaving) on the data stream.

[0148] As can be seen from the above description of performing convolutional interleaving at the sending end and inverse convolutional deinterleaving at the receiving end, for the sending end, the time delay introduced by the third delay line is the largest. For the receiving end, the time delay introduced by the third delay line is the smallest. Specifically, Figure 1m the positions circled by the hollow circles and solid circles in

[0149] In Figure 1m the period of the idle circle and the period of the solid circle both correspond to 120 bits.

[0150] The inner code FEC encoding at the sending end can be, for example, inserting 16 parity bits for every 110 bits of information bits. Combining the 32:1 codeword interleaving after the inner code FEC encoding is equivalent to inserting 512 parity bits for every 3520 bits of information bits. The receiving side is a reverse process, and for every 3520 bits of information bits, 512 parity bits will be deleted.

[0151] The addition and deletion of parity bits in the inner code FEC encoding and decoding processes will introduce a time delay in the shape of a sawtooth wave. It can be referred to Figure 1n for understanding, Figure 1n is a schematic diagram of the time delay introduced by an inner code FEC encoding or decoding function provided by an embodiment of the present application. Among them:

[0152] The sawtooth wave period is: 126 * 32 / (106.25G / 4) ≈ 151.7929 ns, and the sawtooth wave amplitude is approximately 512 / (106.25G / 4) ≈ 19.2753 ns.

[0153] As described above for Figure 1nAs can be seen from the description, the period of the sawtooth wave corresponds to 32 data blocks, and one data block corresponds to one FEC inner code word that is a BCH code word. For example, one data block may include 126 bits, and these 126 bits correspond to one FEC inner code word encoded by the BCH code. Also, for example, one data block may include 110 bits, and after these 110 bits are encoded by the BCH code, a 126-bit FEC inner code word can be obtained. In Figure 1n In it, the positions circled by the hollow circles and the solid circles correspond to the starting positions of the aforementioned 32 data blocks. For the transmitting end, the delay corresponding to the position circled by the hollow circle corresponds to the maximum delay introduced by the transmitting end when performing the inner code FEC encoding operation. For the receiving end, the delay corresponding to the position circled by the solid circle corresponds to the minimum delay introduced by the receiving end when performing the FEC inner code decoding operation.

[0154] In Figure 1n In it, the periods of both the idle circles and the solid circles correspond to 32 data blocks. In one example, one data block includes 126 bits, and in another example, one data block includes 110 bits.

[0155] Regarding the aforementioned delay introduced by the inner code FEC function, the Institute of Electrical and Electronics Engineers (IEEE) 802.3cx standard stipulates that for the transmitting end, the reported delay is equivalent to the maximum delay, and for the receiving end, the reported delay is equivalent to the minimum delay.

[0156] However, the IEEE 802.3cx standard does not stipulate the specific implementation method for the transmitting end to report the maximum delay and the specific implementation method for the receiving end to report the minimum delay in the scenario where the physical layer supports the concatenated coding function.

[0157] In addition, the existing IEEE 802.3cx Section 90 requires that when the physical layer of a communication device reports the delay, each layer reports the maximum delay and the minimum delay separately. Specifically, IEEE 802.3cx Section 90 defines the registers for each layer to report the maximum delay and the minimum delay. For example, IEEE 802.3cx Section 90 defines the TX maximum delay register of PMA / PMD, the TX minimum delay register of PMA / PMD, the RX maximum delay register of PMA / PMD, and the RX minimum delay register of PMA / PMD, where:

[0158] The TX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device is the transmitting end;

[0159] The TX minimum delay register of PMA / PMD is used to report the minimum delay of PMA / PMD when the communication device acts as a transmitter;

[0160] The RX maximum delay register of PMA / PMD is used to report the maximum delay of PMA / PMD when the communication device acts as a receiver;

[0161] The RX minimum delay register of PMA / PMD is used to report the minimum delay of PMA / PMD when the communication device acts as a receiver.

[0162] In view of this, the embodiments of the present application provide a delay reporting method. For multiple operations performed by the inner code FEC, the delay corresponding to each operation in the multiple operations can be determined respectively, so as to report the delay corresponding to each operation to the MAC layer. The solution provided by the embodiments of the present application can accurately report the delay in a scenario where the physical layer supports the concatenated coding function, under the condition of following the "for the transmitter, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay" stipulated by the EEE 802.3cx standard.

[0163] Next, the delay reporting method provided by the embodiments of the present application will be introduced with reference to the accompanying drawings.

[0164] Before introducing the delay reporting method provided by the embodiments of the present application, it should be noted that:

[0165] For a communication device, it may include a physical layer module, and the physical layer module is used to implement the functions implemented by the foregoing physical layer. For the physical layer, it may include multiple sub-modules, and each sub-module is used to implement a specific physical layer function. For example, the physical layer module includes a PCS sub-module, a PMA sub-module, and a PMD sub-module. The PCS sub-module is used to implement the functions implemented by the foregoing PCS, the PMA sub-module is used to implement the functions implemented by the foregoing PMA, and the PMD sub-module is used to implement the functions implemented by the foregoing PMD.

[0166] In addition, the communication device may further include an optical module, and the optical module may also include corresponding sub-modules for implementing corresponding functions. For example, for a communication device with the structure Figure 1c shown in the figure, the optical module may include a PMA sub-module, an inner code FEC module, and a PMD sub-module. Among them, the inner code FEC module is used to implement the inner code FEC function.

[0167] In addition, time synchronization is only an application scenario provided by the embodiments of the present application. The solutions of the embodiments of the present application can also be applied to other scenarios. For example, in the scenario of in-flow detection, a communication device can also use the solutions of the embodiments of the present application to determine the transmission timestamp or reception timestamp of a message. For the application scenarios of the embodiments of the present application, they are not listed one by one here.

[0168] See Figure 2 , which is a schematic flowchart of a delay reporting method provided by an embodiment of the present application.

[0169] Figure 2 The delay reporting method shown can be applied to a first module. The first module can be a module in a communication device. The communication device mentioned here can be a communication device as a sending end or a communication device as a receiving end. The embodiments of the present application do not make specific limitations. The structure of the first module can be as Figure 3 shown. Figure 3 is a schematic structural diagram of a first module provided by an embodiment of the present application. As shown in Figure 3 , the first module includes a bitstream processing module, a delay determination module, and a delay reporting module. The bitstream processing module can include an FEC module and other modules that interact with the FEC module. The delay determination module is used to determine the delay, and the delay reporting module is used to report the determined delay to a second module.

[0170] In one example, the first module can be a PHY module or an optical module. As a specific example, the structure of the communication device including the first module is Figure 1c shown. For this case, Figure 3 the FEC module shown can be a module that implements the inner code FEC function. Among them, the module that implements the inner code FEC function can also be referred to as the "inner code FEC module".

[0171] The PHY module mentioned in the embodiments of the present application can be, for example, a PHY chip for implementing PHY functions.

[0172] Figure 2 The method can include the following S101 - S102.

[0173] S101: Determine the target time delay corresponding to data at multiple specific positions in the data stream. The multiple specific positions are separated by a fixed length. The period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum delay introduced in convolutional interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 sub-sequences after distribution; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction (FEC) codeword. N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0174] In an embodiment of the present application, the data stream is a bit stream including multiple bits.

[0175] In an example, the first module may be Figure 1d the module corresponding to the inner code FEC shown. If the first module is the module corresponding to the sending end, the first module may perform convolutional interleaving operation, 120-bit block distribution operation, and inner code FEC encoding operation on the data entering the first module. Correspondingly, if the first module is the module corresponding to the receiving end, the first module may perform FEC inner code decoding operation, 120-bit block multiplexing operation, and inverse convolutional de-interleaving operation on the data entering the first module. For this case:

[0176] In an example, the target time delay may be the time delay introduced by the sending end performing convolutional interleaving. At this time, the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences. As described above, one convolutional interleaving sequence may include 3 40-bit, that is, one convolutional interleaving sequence includes 120 bits. For this case, referring to the description of Figure 1g above, it can be known that the time delay corresponding to the position circled by the hollow circle in the foregoing Figure 1g is the maximum time delay corresponding to the sending end performing convolutional interleaving operation. Therefore, the period of the multiple specific positions corresponds to Figure 1g the period of the hollow circle in Figure 1g For example, the period of the multiple specific positions may be an integer multiple of the period of the hollow circle in Figure 1gThe position circled by the hollow circle corresponds to the delay line with the largest introduced delay. The delay line with the smallest introduced delay is the first delay line among the three delay lines. Among them, for the transmitting end, the corresponding first delay line can delay each data unit it receives by 2*Q*D bits. The corresponding second delay line among the three delay lines can delay each data unit it receives by Q*D bits. The corresponding third delay line among the three delay lines does not perform a delay operation on each data unit it receives. Regarding the values of the data unit, Q, and D, reference can be made to the relevant description part of Figure 1g as described above, and no repeated description will be made here.

[0177] In this scenario, the data stream can be the data stream entering the convolutional interleaving module of the transmitting end, or the data stream after being processed by the convolutional interleaving module. Among them, the convolutional interleaving module is used to perform convolutional interleaving processing. Among them, before the data stream enters the convolutional interleaving module for processing, it can be subjected to outer code FEC encoding processing by the PCS of the transmitting end. It can be referred to Figure 1c for understanding that the data stream subjected to the outer code FEC encoding processing can be transmitted to the PMA101 of the PCS and passed to the PMA102 of the optical module through the AUI. Further, it is passed from the PMA102 of the optical module to the inner code FEC so that the convolutional interleaving module of the inner code FEC can further perform convolutional interleaving processing.

[0178] As described before for Figure 1g the position circled by the hollow circle, it can be known that the position circled by the hollow circle can correspond to the starting position of the convolutional interleaving sequence. In other words, the specific position corresponds to the starting position of one or more convolutional interleaving sequences.

[0179] In another example, the target delay can be the delay introduced by the receiving end performing inverse convolutional deinterleaving. At this time, the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences. As described before, one convolutional interleaving sequence can include 3 40-bit data, that is, one convolutional interleaving sequence includes 120 bits. For this case, referring to the description of Figure 1g as described above, the delay corresponding to the position circled by the solid circle in the foregoing Figure 1g is the minimum delay corresponding to the receiving end performing the inverse convolutional deinterleaving operation. Therefore, the period of the multiple specific positions can correspond to Figure 1g the period of the solid circle in Figure 1g For example, the period of the multiple specific positions can be an integer multiple of the period of the solid circle in Figure 1gThe position circled by the solid circle corresponds to the delay line with the minimum introduced delay. The delay line with the minimum introduced delay is the first delay line among the three delay lines. Among them, the first delay line corresponding to the receiving end does not perform a delay operation on each data unit it receives. The second delay line corresponding to the receiving end can delay each data unit it receives by Q * D bits. The third delay line corresponding to the receiving end can delay each data unit it receives by 2 * Q * D bits. Regarding the values of Q and D, reference can be made to the relevant description part of Figure 1g in the previous text, and no repeated description will be given here.

[0180] In this scenario, as an example, the data stream can be the data stream sent from the sending end to the receiving end, and this data stream can be the data stream entering the convolutional interleaving module of the receiving end. As another example, the data stream can also be the data stream after being processed by the convolutional interleaving module of the receiving end, where the convolutional interleaving module of the receiving end is used to perform inverse convolutional deinterleaving processing.

[0181] As described before for Figure 1g the position circled by the solid circle, it can be known that the position circled by the solid circle can correspond to the starting position of the convolutional interleaving sequence. In other words, the specific position corresponds to the starting position of one or more convolutional interleaving sequences.

[0182] In the embodiments of the present application, the first module is the module corresponding to the sending end, and it can be understood that the first module is the module in the communication device serving as the sending end; the first module is the module corresponding to the receiving end, and it can be understood that the first module is the module in the communication device serving as the receiving end. Among them, the first module being the module corresponding to the receiving end can also be understood as the first module corresponding to the receiving end, and the first module being the module corresponding to the sending end can also be understood as the first module corresponding to the sending end.

[0183] In an example, the target delay can be the delay introduced by the sending end performing 120-bit block distribution. At this time, the period of the multiple specific positions corresponds to the length of one or more distribution sequences. The sending end can perform 1:8 distribution processing on the distribution sequence and distribute multiple data blocks including 120 bits to 8 inner FEC flows. As described before, one distribution sequence can include 8 120 bits, that is, one distribution sequence includes 960 bits. For this situation, referring to the description of Figure 1i in the previous text, it can be known that the delay corresponding to the position circled by the hollow circle in the foregoing Figure 1i is the maximum delay corresponding to the sending end performing 120-bit block distribution operation. Therefore, the period of the multiple specific positions corresponds to Figure 1i the period of the hollow circle in Figure 1iAn integer multiple of the period of the hollow circles. In other words, the periods of the multiple specific positions can correspond to the lengths of one or more distribution sequences. In this scenario, Figure 1i The positions circled by the hollow circles correspond to the starting positions of the distribution sequences and the first stream (i.e., the first inner FEC flow) corresponding to the 1:8 distribution process.

[0184] In yet another example, the target latency can be the latency introduced by the receiver performing 120-bit block multiplexing. At this time, the periods of the multiple specific positions correspond to the lengths of one or more distribution sequences. The receiver can perform 8:1 multiplexing processing on the distribution sequences to combine 120-bit data blocks on 8 inner FEC flows into one data stream. For this case, referring to the previous description of Figure 1i it can be known that the latency corresponding to the positions circled by the solid circles described above is the minimum latency corresponding to the receiver performing 120-bit block multiplexing operations. Therefore, the periods of the multiple specific positions correspond to Figure 1i the period of the solid circles. For example, the periods of the multiple specific positions can be Figure 1i an integer multiple of the period of the solid circles. In other words, the periods of the multiple specific positions can correspond to the lengths of one or more distribution sequences. In this scenario, Figure 1i The positions circled by the solid circles correspond to the starting positions of the distribution sequences and the first stream (i.e., the first inner FEC flow) corresponding to the 8:1 multiplexing process. Figure 1i

[0185] In one example, the target latency can be the latency introduced by the transmitter performing inner code FEC encoding. At this time, the periods of the multiple specific positions correspond to an integer multiple of N data blocks. For this case, referring to the previous description of Figure 1j it can be known that the latency corresponding to the positions circled by the hollow circles described above is the maximum latency corresponding to the transmitter performing inner code FEC encoding operations. Therefore, the periods of the multiple specific positions correspond to Figure 1j the period of the hollow circles. For example, the periods of the multiple specific positions can be Figure 1j an integer multiple of the period of the hollow circles. As previously described for Figure 1j it can be known that the period of the hollow circles is 8 data blocks. Therefore, in one example, the aforementioned N is equal to 8. In other words, the periods of the multiple specific positions can correspond to an integer multiple of 8 data blocks. In this scenario, Figure 1j Figure 1j ​​The position circled by the hollow circle corresponds to the starting position that is an integer multiple of the aforementioned 8 data blocks. Each of the 8 data blocks may include 128 bits or may include 120 bits. Among them, 128 bits are the FEC inner code codewords obtained after Hamming code encoding, and 120 bits are the data before Hamming code encoding.

[0186] In this scenario, as an example, the data stream may be the data stream entering the inner code FEC encoding module of the sending end, where the inner code FEC encoding module is used to perform inner code FEC encoding. Before the data stream enters the inner code FEC encoding module, it may have undergone outer code FEC encoding processing by the PCS of the sending end. It can be referred to Figure 1c for understanding that the data stream that has undergone the outer code FEC encoding processing can be transmitted to the PMA101 of the PCS and passed to the PMA102 of the optical module through the AUI. Further, it is passed from the PMA102 of the optical module to the inner code FEC so that the convolutional interleaving module of the inner code FEC can further perform convolutional interleaving processing. As another example, the data stream may also be the data stream after being processed by the inner code FEC encoding module. In other words, the data stream may include the FEC inner code codewords that have undergone outer code FEC encoding processing and then inner code FEC encoding.

[0187] In another example, the target latency may be the latency introduced by the receiving end performing inner code FEC decoding. At this time, the periods of the multiple specific positions correspond to integer multiples of N data blocks. For this case, referring to the previous description of Figure 1j it can be known that the latency corresponding to the position circled by the solid circle in the aforementioned Figure 1j is the minimum latency corresponding to the receiving end performing the inner code FEC decoding operation. Therefore, the periods of the multiple specific positions correspond to Figure 1j the period of the solid circle in Figure 1j . For example, the periods of the multiple specific positions may be an integer multiple of the period of the solid circle in Figure 1j . As described before for Figure 1j the period of the solid circle is 8 data blocks. Therefore, in one example, the aforementioned N is equal to 8. In other words, the periods of the multiple specific positions may correspond to integer multiples of 8 data blocks. In this scenario,

[0188] In this scenario, as an example, the data stream can be the data stream entering the inner code FEC decoding module of the receiving end, where the inner code FEC decoding module is used to perform inner code FEC decoding. As another example, the data stream can also be the data stream obtained by performing inner code FEC decoding via the inner code FEC decoding module.

[0189] In yet another example, the first module can be Figure 1k the module corresponding to the inner code FEC shown. If the first module is the module corresponding to the sending end, the first module can perform convolutional interleaving operations and inner code FEC encoding operations on the data entering the first module. Correspondingly, if the first module is the module corresponding to the receiving end, the first module can perform FEC inner code decoding operations and inverse convolutional deinterleaving operations on the data entering the first module. For this case:

[0190] In one example, the target delay can be the delay introduced by the sending end performing convolutional interleaving. At this time, the periods of the multiple specific positions correspond to the length of one or more convolutional interleaving sequences. As described above, one convolutional interleaving sequence can include 3 40-bit units, that is, one convolutional interleaving sequence includes 120 bits. For this case, referring to the previous description of Figure 1m it can be known that the delay corresponding to the position circled by the hollow circle in the foregoing Figure 1m is the maximum delay corresponding to the sending end performing convolutional interleaving operations. Therefore, the periods of the multiple specific positions correspond to Figure 1m the periods of the hollow circles in Figure 1m For example, the periods of the multiple specific positions can be an integer multiple of the periods of the hollow circles in Figure 1m In other words, the periods of the multiple specific positions can correspond to the length of one or more convolutional interleaving sequences. In this scenario, Figure 1m the position circled by the hollow circle in

[0191] corresponds to the delay line with the maximum introduced delay, and the delay line with the maximum introduced delay is the third delay line among the three delay lines. Among them, for the sending end, the corresponding first delay line may not perform a delay operation on each data unit it receives, the corresponding second delay line among the three delay lines can delay each data unit it receives by 6*D bits, and the corresponding third delay line among the three delay lines can delay each data unit it receives by 12*D bits. Regarding the value of D, reference can be made to the relevant description part of Figure 1m above, and no repeated description will be made here.In this scenario, the data stream can be the data stream entering the convolutional interleaving module at the transmitting end, or the data stream after being processed by the convolutional interleaving module, where the convolutional interleaving module is used to perform convolutional interleaving processing. Among them, before the data stream enters the convolutional interleaving module for processing, it can be subjected to outer code FEC encoding processing by the PCS at the transmitting end. For reference, see Figure 1c It can be understood that the data stream subjected to the outer code FEC encoding processing can be transmitted to PMA101 of the PCS and passed to PMA102 of the optical module through the AUI. Further, it is passed from PMA102 of the optical module to the inner code FEC so that the convolutional interleaving module of the inner code FEC can further perform convolutional interleaving processing.

[0192] In another example, the target latency can be the latency introduced by the receiving end performing inverse convolutional deinterleaving. At this time, the periods of the multiple specific positions correspond to the length of one or more convolutional interleaving sequences. As described above, one convolutional interleaving sequence can include 3 40-bit data, that is, one convolutional interleaving sequence includes 120 bits. For this case, referring to the previous description of Figure 1m , it can be known that the latency corresponding to the positions circled by the solid circles in the foregoing Figure 1m is the minimum latency corresponding to the receiving end performing the inverse convolutional deinterleaving operation. Therefore, the periods of the multiple specific positions can correspond to Figure 1m the periods of the solid circles in Figure 1m For example, the periods of the multiple specific positions can be an integer multiple of the periods of the solid circles in Figure 1m In this scenario, the position circled by the solid circle in Figure 1m corresponds to the delay line with the minimum introduced latency, and the delay line with the minimum introduced latency is the third delay line among the three delay lines. Among them, the third delay line corresponding to the receiving end does not perform a delay operation on each data unit it receives. The second delay line corresponding to the receiving end can delay each data unit it receives by 6*D bits. The first delay line corresponding to the receiving end can delay each data unit it receives by 12*D bits. Regarding the value of D, reference can be made to the relevant description part of Figure 1m above, and no repeated description will be made here.

[0193] In this scenario, as an example, the data stream can be the data stream sent from the transmitting end to the receiving end, and this data stream can be the data stream entering the convolutional interleaving module at the receiving end. As another example, the data stream can also be the data stream after being processed by the convolutional interleaving module at the receiving end, where the convolutional interleaving module at the receiving end is used to perform inverse convolutional deinterleaving processing.

[0194] In one example, the target latency may be the latency introduced by the sender performing inner code FEC encoding. At this time, the periods of the multiple specific positions correspond to an integer multiple of N data blocks. For this case, referring to the previous description of Figure 1n it can be known that the latency corresponding to the position circled by the hollow circle in the foregoing Figure 1n is the maximum latency corresponding to the sender performing the inner code FEC encoding operation. Therefore, the periods of the multiple specific positions correspond to the periods of the hollow circles in Figure 1n For example, the periods of these multiple specific positions may be an integer multiple of the periods of the hollow circles in Figure 1n As described previously for Figure 1n it can be known that the period of the hollow circle is 32 data blocks. Therefore, in one example, the foregoing N is equal to 32. In other words, the periods of the multiple specific positions may correspond to an integer multiple of 32 data blocks. In this scenario, Figure 1n the position circled by the hollow circle in corresponds to the starting position of an integer multiple of the foregoing 32 data blocks. Each of the 32 data blocks may include 126 bits or may include 110 bits. Among them, 126 bits are the FEC inner code codewords obtained after BCH code encoding, and 110 bits are the data before BCH code encoding.

[0195] In this scenario, as an example, the data stream may be the data stream entering the inner code FEC encoding module of the sender, where the inner code FEC encoding module is used to perform inner code FEC encoding. Before the data stream enters the inner code FEC encoding module, it may have undergone outer code FEC encoding processing by the PCS of the sender. It can be referred to Figure 1c for understanding that the data stream that has undergone the outer code FEC encoding processing may be transmitted to PMA101 of the PCS and passed to PMA102 of the optical module through the AUI. Further, it is passed from PMA102 of the optical module to the inner code FEC so that the convolutional interleaving module of the inner code FEC can further perform convolutional interleaving processing. As another example, the data stream may also be the data stream after being processed by the inner code FEC encoding module. In other words, the data stream may include the FEC inner code codewords that have undergone outer code FEC encoding processing and then inner code FEC encoding.

[0196] In yet another example, the target latency may be the latency introduced by the receiver performing inner code FEC decoding. At this time, the periods of the multiple specific positions correspond to an integer multiple of N data blocks. For this case, referring to the previous description of Figure 1n it can be known that the foregoing Figure 1nThe time delay corresponding to the position circled by the solid circle in the middle is the minimum time delay corresponding to the inner code FEC decoding operation performed by the receiving end. Therefore, the period of the multiple specific positions corresponds to Figure 1n the period of the solid circle in the middle. For example, the period of the multiple specific positions can be Figure 1n an integer multiple of the period of the solid circle in the middle. As described before for Figure 1n it can be known that the period of the solid circle is 32 data blocks. Therefore, in one example, the aforementioned N is equal to 32. In other words, the period of the multiple specific positions can correspond to an integer multiple of 32 data blocks. In this scenario, Figure 1n the position circled by the solid circle in the middle corresponds to the starting position of an integer multiple of the aforementioned 32 data blocks. Among them, each of the 32 data blocks can include 126 bits or 110 bits. Among them, 126 bits are the FEC inner code codewords obtained after BCH code encoding, and 110 bits are the data before BCH code encoding.

[0197] In this scenario, as an example, the data stream can be the data stream entering the inner code FEC decoding module of the receiving end, where the inner code FEC decoding module is used to perform inner code FEC decoding. As another example, the data stream can also be the data stream obtained by performing inner code FEC decoding by the inner code FEC decoding module.

[0198] In one example, among the data of the multiple specific positions, the data of each specific position can correspond to a first time delay. Therefore, the data of the multiple specific positions can correspond to multiple first time delays.

[0199] In the embodiments of the present application, the multiple first time delays can be the same, or not completely the same or completely different. The embodiments of the present application do not make specific limitations.

[0200] As described before, the existing IEEE 802.3cx Section 90 defines corresponding maximum time delay registers and minimum time delay registers for each layer of the physical layer. Therefore, in order to be compatible with the current IEEE 802.3cx Section 90's mechanism for reporting the time delay of the physical layer, the maximum value and / or minimum value of the multiple first time delays can be reported. In other words, the aforementioned target time delay can be the maximum value and / or minimum value of the multiple first time delays.

[0201] As described before, the multiple first time delays can be the same, or not completely the same or completely different. When the multiple first time delays are the same, the maximum value and the minimum value are the same. When the multiple first time delays are not completely the same or completely different, the maximum value is less than the minimum value.

[0202] In one example, when specifically implemented, the first module may measure the first latency corresponding to the data at each of the multiple specific positions in the data of the multiple specific positions, to obtain a plurality of first latencies. For example:

[0203] The embodiments of the present application do not specifically limit the specific implementation manner for determining the first latency.

[0204] In one example, the first module may record the latency for the data at a specific position in the data stream, so as to determine the first latency. In another example, the first module may determine the latency of the data at multiple positions in the data stream passing through the first module, so as to obtain a plurality of corresponding latencies at the multiple positions. The multiple positions mentioned herein may include the specific position. For example, the multiple positions may be each position in the target data. Correspondingly, the first latency may be determined from the plurality of latencies. That is: the latency corresponding to the specific position is extracted from the plurality of latencies, so as to obtain the first latency. For example: for a data stream, the first module may determine the latency of each bit of data in the data stream passing through the first module, and extract the latency of the data at a specific position (such as the start position of each convolutional interleaved sequence) in the data stream from it, so as to obtain the first latency.

[0205] The embodiments of the present application do not specifically limit the determination manner of the latency of the data at any position in the data stream passing through the first module. The following introduces two possible implementation manners.

[0206] In one implementation manner, the first module may record the first moment when it receives the data at this position, and record the second moment when it sends out the data at this position, and determine the difference obtained by subtracting the first moment from the second moment as the latency of the data at this position passing through the first module.

[0207] In yet another example, after receiving the data at this position, the first module may cache the data at this position. Correspondingly, the first module may send out the cached data in sequence according to the data that has been cached in the cache. Therefore, the position of the data at this position in the cache may represent the duration that the data at this position needs to wait in the cache, and this waiting duration may represent the latency of the data at this position passing through the first module. Therefore, the first module may determine the latency of the data at this position passing through the first module according to the position of the data at this position in the cache.

[0208] S102: Report the target latency corresponding to the data at multiple specific positions in the data stream.

[0209] In an embodiment of the present application, the first module may report the target delay to the second module. In one example, the second module may be the MAC layer module of a communication device. In this way, the MAC layer module may compensate the timestamp recorded by itself based on the target delay, so that the compensated timestamp is more accurate.

[0210] In one example, the first module may report the target delay to the second module alone, or may add the target delay and the delay of other operations of the data stream passing through the inner code FEC and then report them to the second module together. The embodiments of the present application do not make specific limitations.

[0211] The first module may report the target delay to the second module by using a corresponding register. In a scenario where the target delay includes the aforementioned maximum value and / or minimum value, in one example, the first module may report the maximum value and / or minimum value to the second module by using a corresponding register. The following introduces several specific implementation manners for the first module to report the maximum value and / or minimum value to the second module by using a corresponding register.

[0212] In one example, if the first module corresponds to the sending end, then:

[0213] As a specific example, new registers may be defined to report the maximum value and / or minimum value to the second module. For example, define the TX maximum delay register and / or TX minimum delay register of the inner code FEC. The TX maximum delay register is used to report the maximum value, and the TX minimum delay register is used to report the minimum value. In other words, the first module may use the TX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the TX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0214] As another specific example, the first module may use the TX maximum delay register of the PMA / PMD to report the maximum value to the second module. Similarly, the first module may use the TX minimum delay register of the PMA / PMD to report the minimum value to the second module. By adopting this method, the existing registers can be used to implement the reporting of the target delay.

[0215] In one example, if the first module corresponds to the receiving end, then:

[0216] As yet another specific example, new registers may be defined to report the maximum value and / or minimum value to the second module. For example, define an RX maximum delay register and / or an RX minimum delay register for the inner code FEC. The RX maximum delay register is used to report the maximum value, and the RX minimum delay register is used to report the minimum value. In other words, the first module may use the RX maximum delay register of the inner code FEC to report the maximum value to the second module, and / or use the RX minimum delay register of the inner code FEC to report the minimum value to the second module.

[0217] As another specific example, the first module may use the RX maximum delay register of PMA / PMD to report the maximum value to the second module. Similarly, the first module may use the RX minimum delay register of PMA / PMD to report the minimum value to the second module.

[0218] From the above description, it can be seen that by using the solution of the embodiments of the present application, for the dynamic periodic delay part (i.e., the delay part in the shape of a sawtooth wave), the first module can follow the principle that "for the sender, the reported delay is equivalent to the maximum delay, and for the receiver, the reported delay is equivalent to the minimum delay" to accurately report the delay to the second module.

[0219] The above introduced the delay reporting method provided by the embodiments of the present application. Next, the solution provided by the embodiments of the present application will be introduced in combination with a specific scenario.

[0220] In this scenario, the structure of the communication device may adopt Figure 1d the structure shown. The first module may be an optical module of the communication device, and the optical module includes PMA102, inner code FEC, and PMD.

[0221] Embodiment 1:

[0222] For the communication device acting as the sender, its optical module may perform the following operations:

[0223] S1: Record the delay of the i-th convolutional interleaved sequence in the data stream it sends after the convolutional interleaving operation to obtain DelayTX1(1, i), where:

[0224] 1 represents the starting position, which may be the 1st bit, the 1st byte, or the 1st symbol.

[0225] The value of i may be 1, 2, 3,... s.

[0226] S2: Determine the maximum value DelayTX_max1 of DelayTX1(1, i) and the minimum value DelayTX_min1 of DelayTX1(1, i).

[0227] S3: Report DelayTX_max1 and DelayTX_min1 to the MAC layer module, or report (DelayTX_max1 + sum11) and (DelayTX_min1 + sum12) to the MAC layer module.

[0228] In one example, DelayTX_max1 or (DelayTX_max1 + sum11) can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min1 or (DelayTX_min1 + sum12) can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0229] In another example, DelayTX_max1 or (DelayTX_max1 + sum11) can be reported to the MAC layer module through the TX maximum delay register of the PMA / PMD, and DelayTX_min1 or (DelayTX_min1 + sum12) can be reported to the MAC layer module through the TX minimum delay register of the PMA / PMD.

[0230] Among them, sum11 can be the maximum value of the sum of the delays of the data stream passing through other operations, and sum12 can be the minimum value of the sum of the delays of the data stream passing through other operations. sum11 and sum12 can be the same, or sum11 can be greater than sum12. Other operations mentioned here can be, for example, the 120-bit block distribution operation and the inner code FEC encoding operation in the inner code FEC.

[0231] For a communication device acting as a receiver, its optical module can perform the following operations:

[0232] S1': Record the delay of the i-th convolutional interleaving sequence in the data stream it sends after the convolutional interleaving operation to obtain DelayRX1(1, i), where:

[0233] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0234] The value of i can be 1, 2, 3,..., s.

[0235] S2': Determine the maximum value DelayRX_max1 of DelayRX1(1, i) and the minimum value DelayRX_min1 of DelayRX1(1, i).

[0236] S3’: Report DelayRX_max1 and DelayRX_min1 to the MAC layer module, or report (DelayRX_max1 + sum11’) and (DelayRX_min1 + sum12’) to the MAC layer module.

[0237] In one example, DelayRX_max1 or (DelayRX_max1 + sum11’) can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min1 or (DelayRX_min1 + sum12’) can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0238] In another example, DelayRX_max1 or (DelayRX_max1 + sum11’) can be reported to the MAC layer module through the RX maximum delay register of PMA / PMD, and DelayRX_min1 or (DelayRX_min1 + sum12’) can be reported to the MAC layer module through the RX minimum delay register of PMA / PMD.

[0239] Among them, sum11’ can be the maximum value of the sum of the delays of the data stream through other operations, and sum12’ can be the minimum value of the sum of the delays of the data stream through other operations. sum11’ and sum12’ can be the same, or sum11’ can be greater than sum12’. Other operations mentioned here can be, for example, the 120-bit block multiplexing operation in the inner code FEC, the FEC inner code decoding operation, etc.

[0240] Embodiment 2:

[0241] For a communication device acting as a transmitter, its optical module can perform the following operations:

[0242] S4: Record the delay of the i-th distribution sequence in the data stream it sends after the 120-bit block distribution operation to obtain DelayTX2(1, j), where:

[0243] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0244] The value of i can be 1, 2, 3,..., s.

[0245] S5: Determine the maximum value DelayTX_max2 of DelayTX2(1, j) and the minimum value DelayTX_min2 of DelayTX2(1, j).

[0246] S6: Report DelayTX_max2 and DelayTX_min2 to the MAC layer module, or report (DelayTX_max2 + sum21) and (DelayTX_min2 + sum22) to the MAC layer module.

[0247] In one example, DelayTX_max2 or (DelayTX_max2 + sum21) can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min2 or (DelayTX_min2 + sum22) can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0248] In another example, DelayTX_max2 or (DelayTX_max2 + sum21) can be reported to the MAC layer module through the TX maximum delay register of PMA / PMD, and DelayTX_min2 or (DelayTX_min2 + sum22) can be reported to the MAC layer module through the TX minimum delay register of PMA / PMD.

[0249] Among them, sum21 can be the maximum value of the sum of the delays of the data stream passing through other operations, and sum22 can be the minimum value of the sum of the delays of the data stream passing through other operations. sum21 and sum22 can be the same, or sum21 can be greater than sum22. Other operations mentioned here can be, for example, the convolutional interleaving operation and the inner code FEC encoding operation in the inner code FEC.

[0250] For a communication device acting as a receiver, its optical module can perform the following operations:

[0251] S4': Record the delay of the i-th distribution sequence in the data stream sent by it after the 120-bit block multiplexing operation to obtain DelayRX2(1, j), where:

[0252] 1 represents the starting position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0253] The value of i can be 1, 2, 3,..., s.

[0254] S5': Determine the maximum value DelayRX_max2 of DelayRX2(1, j) and the minimum value DelayRX_min2 of DelayRX2(1, j).

[0255] S6’: Report DelayRX_max2 and DelayRX_min2 to the MAC layer module, or report (DelayRX_max2 + sum21’) and (DelayRX_min2 + sum22’) to the MAC layer module.

[0256] In one example, DelayRX_max2 or (DelayRX_max2 + sum21’) can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min2 or (DelayRX_min2 + sum22’) can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0257] In another example, DelayRX_max2 or (DelayRX_max2 + sum21’) can be reported to the MAC layer module through the RX maximum delay register of PMA / PMD, and DelayRX_min2 or (DelayRX_min2 + sum22’) can be reported to the MAC layer module through the RX minimum delay register of PMA / PMD.

[0258] Wherein, sum21’ can be the maximum value of the sum of the delays of the data stream through other operations, sum22’ can be the minimum value of the sum of the delays of the data stream through other operations, sum21’ can be equal to sum22’, and sum21’ can also be greater than sum22’. Other operations mentioned here can be, for example, the inverse convolution deinterleaving operation and the FEC inner code decoding operation in the inner code FEC.

[0259] Embodiment 3:

[0260] For the communication device acting as the transmitting end, its optical module can perform the following operations:

[0261] S7: Record the delay of the start position of the kth data block in the data stream it transmits after being encoded by the inner code FEC to obtain DelayTX3(1, k), where:

[0262] 1 represents the start position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0263] The value of k can be 8, 16, 32,... 8*s, and at this time a data block includes 128 bits or 120 bits; or the value of k can be 32, 64, 96,... 32*s, and at this time a data block includes 126 bits or 110 bits.

[0264] S8: Determine the maximum value DelayTX_max3 of DelayTX3(1, k) and the minimum value DelayTX_min3 of DelayTX3(1, k).

[0265] S9: Report DelayTX_max3 and DelayTX_min3 to the MAC layer module, or report (DelayTX_max3 + sum31) and (DelayTX_min3 + sum32) to the MAC layer module.

[0266] In one example, DelayTX_max3 or (DelayTX_max3 + sum31) can be reported to the MAC layer module through the TX maximum delay register of the inner code FEC, and DelayTX_min3 or (DelayTX_min3 + sum32) can be reported to the MAC layer module through the TX minimum delay register of the inner code FEC.

[0267] In another example, DelayTX_max3 or (DelayTX_max3 + sum31) can be reported to the MAC layer module through the TX maximum delay register of PMA / PMD, and DelayTX_min3 or (DelayTX_min3 + sum32) can be reported to the MAC layer module through the TX minimum delay register of PMA / PMD.

[0268] Among them, sum31 can be the maximum value of the sum of the delays of the data stream passing through other operations, sum32 can be the minimum value of the sum of the delays of the data stream passing through other operations, sum31 can be equal to sum32, and sum31 can also be greater than sum32. Other operations mentioned here can be, for example, the convolutional interleaving operation in the inner code FEC, or the convolutional interleaving operation and the 120-bit block distribution operation.

[0269] For a communication device acting as a receiver, its optical module can perform the following operations:

[0270] S7’: Record the delay of the start position of the k-th data block in the data stream it sends after being encoded by the inner code FEC to obtain DelayRX3(1, k), where:

[0271] 1 represents the start position, which can be the 1st bit, the 1st byte, or the 1st symbol.

[0272] The value of k can be 8, 16, 32,... 8*s, and at this time a data block includes 128 bits or 120 bits; or the value of k can be 32, 64, 96,... 32*s, and at this time a data block includes 126 bits or 110 bits.

[0273] S8’: Determine the maximum value DelayRX_max3 of DelayRX3(1, k) and the minimum value DelayRX_min3 of DelayRX(1, k).

[0274] S9’: Report DelayRX_max3 and DelayRX_min3 to the MAC layer module, or report (DelayRX_max3 + sum31’) and (DelayRX_min3 + sum32’) to the MAC layer module.

[0275] In one example, DelayRX_max3 or (DelayRX_max3 + sum31’) can be reported to the MAC layer module through the RX maximum delay register of the inner code FEC, and DelayRX_min3 or (DelayRX_min3 + sum32’) can be reported to the MAC layer module through the RX minimum delay register of the inner code FEC.

[0276] In another example, DelayRX_max3 or (DelayRX_max3 + sum31’) can be reported to the MAC layer module through the RX maximum delay register of PMA / PMD, and DelayRX_min3 or (DelayRX_min3 + sum32’) can be reported to the MAC layer module through the RX minimum delay register of PMA / PMD.

[0277] Wherein, sum31’ can be the maximum value of the sum of the delays of the data stream through other operations, sum32’ can be the minimum value of the sum of the delays of the data stream through other operations, sum31’ can be equal to sum32’, or sum31’ can be greater than sum32’. Other operations mentioned here can be, for example, the inverse convolution and deinterleaving operation in the inner code FEC, or the inverse convolution and deinterleaving operation and the 120-bit block multiplexing operation.

[0278] Based on the delay reporting method provided in the above embodiments, the embodiments of the present application further provide a corresponding delay reporting device, which can be used to execute the delay reporting method provided in the above embodiments.

[0279] In a specific example, the delay reporting device can be as Figure 4 shown. Figure 4 It is a schematic structural diagram of a delay reporting device provided by an embodiment of the present application.

[0280] As Figure 4 shown, the delay reporting device 400 includes: a sending unit 401.

[0281] The sending unit 401 is configured to report the target time delays corresponding to data at multiple specific positions in a data stream, where a fixed length interval exists between the multiple specific positions; wherein: the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum introduced time delay in convolutional interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 distributed sub-sequences; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction (FEC) codeword, N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

[0282] In a possible implementation manner, the delay line with the maximum or minimum introduced time delay is the first delay line among the three delay lines in convolutional interleaving.

[0283] In a possible implementation manner, the first delay line is configured to delay each data unit it receives by 2*Q*D bits, the second delay line among the three delay lines is configured to delay each data unit it receives by Q*D bits, and the third delay line among the three delay lines does not perform a delay operation on each data unit it receives, D is the number of bits included in each data unit, and Q is a positive integer; or, the third delay line is configured to delay each data unit it receives by 2*Q*D bits, the second delay line is configured to delay each data unit it receives by Q*D bits, and the first delay line does not perform a delay operation on each data unit it receives.

[0284] In a possible implementation manner, the value of Q is 544 or 272 or 136 or 68.

[0285] In a possible implementation manner, the delay line with the maximum or minimum introduced time delay is the third delay line among the three delay lines in convolutional interleaving.

[0286] In a possible implementation manner, the first delay line does not perform a delay operation on each data unit it receives, the second delay line among the three delay lines is configured to delay each data unit it receives by 6*D bits, and the third delay line among the three delay lines is configured to delay each data unit it receives by 12*D bits, D is the number of bits included in each data unit; or, the third delay line does not perform a delay operation on each data unit it receives, the second delay line is configured to delay each data unit it receives by 6*D bits, and the first delay line is configured to delay each data unit it receives by 12*D bits.

[0287] In a possible implementation, each of the convolutional interleaved sequences includes 3 data units, and each of the 3 data units includes 40 bits.

[0288] In a possible implementation, each of the distribution sequences includes 8 data blocks. Each of the distribution sequences is used to perform 1:8 distribution processing, or each of the distribution sequences is a sequence obtained by performing 8:1 multiplexing processing. The specific position corresponds to the first stream among the 8 streams corresponding to the 1:8 distribution processing or the 8:1 multiplexing processing.

[0289] In a possible implementation, the value of N is 8 or 32; or the FEC codeword is an FEC inner codeword that is subjected to outer code FEC encoding processing and then inner code FEC encoding; or, the FEC inner codeword is a Hamming codeword or a BCH codeword; or, the data stream is a data stream received through the attachment unit interface AUI; or, the data stream is a data stream obtained by performing inner code FEC decoding.

[0290] In a possible implementation, the specific position corresponds to the starting position of the one or more convolutional interleaved sequences; or, the specific position corresponds to the starting position of the one or more distribution sequences; or, the specific position corresponds to the starting position that is an integer multiple of the N data blocks; the starting position is the first bit or the first symbol or the first byte.

[0291] In a possible implementation, the device 400 further includes: a processing unit 402, configured to measure a first delay corresponding to the data at each of the multiple specific positions, and obtain multiple first delays; wherein, the target delay includes the maximum value and / or the minimum value among the multiple first delays.

[0292] In a possible implementation, the sending unit 401 is configured to: report the target delay corresponding to the data at the multiple specific positions in the data stream to the media access control MAC layer.

[0293] Regarding the specific implementation of each unit of the device 400, reference may be made to the description part of the delay reporting method provided in the above embodiments of the present application. The device 400 can implement the delay reporting method described in the above embodiments, and no repeated description will be given here. Each unit in the device 400 can be a software unit implemented by a computer program or a hardware unit implemented by a circuit.

[0294] In yet another specific example, the foregoing delay reporting device may include a circuit, and the circuit is configured to execute the delay reporting method provided in the above embodiments.

[0295] In the embodiments of the present application, the latency reporting device mentioned may be an optical module or a PHY chip.

[0296] In one example, the structure of the PHY chip or optical module may be as Figure 5 shown. Refer to Figure 5 , this figure is a schematic structural diagram of a PHY chip or optical module provided by an embodiment of the present application. Figure 5 The PHY chip or optical module 500 shown includes an interface circuit 501 and a processing circuit 502. The interface circuit 501 is used to receive and / or transmit data, and the processing circuit 502 is used to perform data processing. The PHY chip or optical module 500 can implement the latency reporting method described in the above embodiments. The interface circuit 501 and the processing circuit 502 may be divided in terms of the actual circuit structure, that is, the PHY chip or optical module 500 includes two parts of circuits, namely the interface circuit 501 and the processing circuit 502. Or, the interface circuit 501 and the processing circuit 502 may be divided in terms of functional logic, that is, the PHY chip or optical module 500 includes an overall circuit, and this overall circuit can implement the process of the interface circuit 501 corresponding to receiving and / or transmitting data, and can also implement the process of data processing corresponding to the processing circuit 502.

[0297] In one example, the interface circuit 501 is used to report the target latency corresponding to the data at multiple specific positions in the data stream, and the intervals between the multiple specific positions are of a fixed length; where: the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum latency introduced in the convolutional interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 sub-sequences after distribution; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction FEC codeword, N is a positive integer, and the length of each data block is: 120 bits, or, 128 bits, or, 110 bits, or 126 bits. The processing circuit 502 is used to measure the first latency corresponding to the data at each specific position among the data at the multiple specific positions, and obtain multiple first latencies; where the target latency includes the maximum value and / or the minimum value among the multiple first latencies.

[0298] Refer to Figure 6 , this figure is a schematic structural diagram of a device provided by an embodiment of the present application. Figure 6The device 600 shown includes an interface circuit 601 and a processing circuit 602. The interface circuit 601 is used to receive and / or transmit data, and the processing circuit 602 is used to process data. The device 600 can implement the delay reporting method described in the above embodiments. The interface circuit 601 and the processing circuit 602 can be divided in terms of the actual circuit structure, that is, the device 600 includes two parts of circuits, namely the interface circuit 601 and the processing circuit 602. Or, the interface circuit 601 and the processing circuit 602 can be divided in terms of functional logic, that is, the device 600 includes an overall circuit, and this overall circuit can implement the process of the interface circuit 601 corresponding to receiving and / or transmitting data, and can also implement the process of the data processing corresponding to the processing circuit 602.

[0299] As a specific example, the interface circuit 601 is used to report the target delays corresponding to the data at multiple specific positions in the data stream, and the multiple specific positions are spaced at a fixed length; wherein: the period of the multiple specific positions corresponds to the length of one or more convolutional interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum delay introduced in the convolutional interleaving; or, the period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 distributed subsequences; or, the period of the multiple specific positions corresponds to an integer multiple of N data blocks, and each of the N data blocks corresponds to a forward error correction FEC codeword, N is a positive integer, and the length of each data block is: 120 bits, or, 128 bits, or, 110 bits, or 126 bits. The processing circuit 602 is used to measure the first delay corresponding to the data at each of the multiple specific positions in the data at the multiple specific positions, and obtain multiple first delays; wherein, the target delay includes the maximum value and / or the minimum value among the multiple first delays.

[0300] See Figure 7 , which is a schematic structural diagram of a device provided by an embodiment of the present application.

[0301] In one example, Figure 7 the device 700 shown can be used to execute the delay reporting method corresponding to Figure 2 provided by the above method embodiment.

[0302] Please refer to Figure 7 as shown, the device 700 includes: a communication interface 720. The communication interface 720 is used to execute the delay reporting method corresponding to Figure 2 provided by the above method embodiment.

[0303] In one example, the device 700 may further include a processor 710. The number of processors 710 in the device 700 can be one or more.Figure 7 Take a processor as an example. The processor 710 and the communication interface 720 jointly execute the latency reporting method provided in the above method embodiments corresponding to Figure 2 For example, the processor 710 is used to measure a first latency corresponding to each piece of data at multiple specific positions in the data stream, obtaining a plurality of first latencies; wherein, the target latency includes the maximum value and / or the minimum value among the plurality of first latencies. The communication interface 720 is used to report the target latency corresponding to the data at multiple specific positions in the data stream.

[0304] The processor 710 may be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. The processor 710 may include a digital signal processor (DSP). The processor 710 may further include a hardware chip. The above hardware chip may be an ASIC, a programmable logic device (PLD), or a combination thereof. The above PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0305] In one example, the device 700 further includes a memory 730. The memory 730 may include a volatile memory, such as a random-access memory (RAM); the memory 730 may also include a non-volatile memory, such as a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 730 may further include a combination of the above types of memories. The memory 730 may store, for example, the aforementioned target latency.

[0306] Optionally, the memory 730 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 710 may read the programs in the memory 730 to implement the method provided in the embodiments of the present application.

[0307] In the embodiments of the present application, the processor 710, the communication interface 720, and the memory 730 may be connected through a bus system or other means. Among them, Figure 7 take the connection through the bus system 740 as an example.

[0308] The bus system 740 may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus system 740 may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 7 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0309] The delay reporting device 400, the PHY chip or the optical module 500, the device 600, and the device 700 provided above may all be network devices such as switches, routers, SPN devices, or OTN devices, or may be a part of the components on the network device, such as a single board, a line card, or an interface on the network device, or may be a functional module on the network device, or may be a chip, or may be a pluggable optical module on the network device, or may also be a server, a network card on the server, or a network card of other devices. The embodiments of the present application do not make specific limitations.

[0310] Terms such as "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and the above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order different from that shown or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0311] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0312] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical service division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0313] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0314] In addition, in each embodiment of this application, each service unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software service units.

[0315] If the integrated unit is implemented in the form of a software service unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of this application. And the aforementioned storage medium includes: USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs and other various media that can store program codes.

[0316] Those skilled in the art should be able to realize that in one or more of the above examples, the operations described in the present invention can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these operations can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0317] The above specific implementation manners have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above is only the specific implementation manner of the present invention.

[0318] In the above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present application.

Claims

1. A delay reporting method, characterized in that: The method comprises: Report the target latency corresponding to data at multiple specific locations in the data stream, where the multiple specific locations are separated by a fixed length; wherein: The periods of the multiple specific positions correspond to the lengths of one or more convolution interleaving sequences, and the specific positions correspond to the delay lines with the maximum or minimum time delay introduced in the convolution interleaving; or, The period of the multiple specific positions corresponds to the length of one or more distribution sequences, and each of the distribution sequences corresponds to 8 distributed subsequences; or, The period of the multiple specific positions corresponds to an integer multiple of N data blocks, each of the N data blocks corresponds to a forward error correction FEC codeword, N is a positive integer, and the length of each data block is: 120 bits, or 128 bits, or 110 bits, or 126 bits.

2. The method according to claim 1, characterized in that The delay line that introduces the largest or smallest delay is the first delay line among the three delay lines in the convolution interleaving.

3. The method according to claim 2, characterized in that The first delay line is used to delay each data unit received by it by 2*Q*D bits, the second delay line of the three delay lines is used to delay each data unit received by it by Q*D bits, and the third delay line of the three delay lines does not perform a delay operation on each data unit received by it, D is the number of bits included in each data unit, and Q is a positive integer; or, The third delay line is used to delay each data unit it receives by 2*Q*D bits, the second delay line is used to delay each data unit it receives by Q*D bits, and the first delay line does not perform a delay operation on each data unit it receives.

4. The method according to claim 3, characterized in that The value of Q is 544, 272, 136 or 68.

5. The method according to claim 1, characterized in that The delay line that introduces the largest or smallest delay is the third delay line among the three delay lines in the convolution interleaving.

6. The method according to claim 5, characterized in that The first delay line does not perform a delay operation on each data unit received by it, the second delay line of the three delay lines is used to delay each data unit received by it by 6*D bits, and the third delay line of the three delay lines is used to delay each data unit received by it by 12*D bits, where D is the number of bits included in each data unit; or, The third delay line does not perform a delay operation on each data unit it receives, the second delay line is used to delay each data unit it receives by 6*D bits, and the first delay line is used to delay each data unit it receives by 12*D bits.

7. The method according to any one of claims 1 to 6, characterized in that: Each of the convolution interleaved sequences includes 3 data units, and each of the 3 data units includes 40 bits.

8. The method according to claim 1, characterized in that Each of the distribution sequences includes 8 data blocks, each of the distribution sequences is used to perform 1:8 distribution processing, or each of the distribution sequences is a sequence obtained by performing 8:1 multiplexing processing. The specific position corresponds to the first stream of the 8 streams corresponding to the 1:8 distribution processing or 8:1 multiplexing processing.

9. The method according to claim 1, characterized in that: The value of N is 8 or 32; or The FEC codeword is an FEC inner codeword that is processed by outer code FEC encoding and then inner code FEC encoding; or The FEC inner code word is a Hamming code word or a BCH code word; or The data stream is a data stream received via an attachment unit interface AUI; or The data stream is a data stream obtained by performing inner code FEC decoding.

10. The method according to any one of claims 1 to 9, characterized in that: The specific position corresponds to the starting position of the one or more convolution interleaved sequences; or, The specific position corresponds to the starting position of the one or more distribution sequences; or, The specific position corresponds to a starting position of an integer multiple of the N data blocks; The starting position is the first bit, the first symbol, or the first byte.

11. The method according to any one of claims 1 to 10, characterized in that: The method further comprises: Measuring a first time delay corresponding to data at each specific location among the data at the multiple specific locations to obtain multiple first time delays; The target delay includes a maximum value and / or a minimum value among the multiple first delays.

12. The method according to any one of claims 1 to 11, characterized in that: Reports the target latency for data at multiple specific locations in a data stream, including: The target delay corresponding to the data at the multiple specific positions in the data stream is reported to the media access control MAC layer.

13. A delay reporting device, characterized in that: The device is used to execute the method according to any one of claims 1 to 12.

14. A delay reporting device, characterized in that: The device comprises a circuit; The circuit is used to execute the method according to any one of claims 1 to 12.

15. The device according to claim 14, wherein the device is: Optical module, or physical PHY layer chip.

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