Charge super injection memory based on two-dimensional Dirac material and preparation method thereof
By adopting charge super injection technology based on two-dimensional Dirac materials in memory, the shortcomings in data retention time and programming speed of existing memories are solved, and efficient data programming and long-term retention are achieved, suitable for high-speed and long-term data storage needs.
Patent Information
- Application Number
- CN202510273997.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-10
AI Technical Summary
The data retention time of existing volatile memory is extremely short after power outage and needs frequent refresh, resulting in high power consumption and limited application range; rather, the programming speed of non-volatile memory is slow and difficult to meet the high-speed storage needs.
Charge super-injection memory based on two-dimensional Dirac material is employed, and its structure includes a substrate, a gate, a barrier layer, a charge storage layer, a tunnel layer, a channel, a source and a drain. Super-injection and long-term retention of charge are achieved by designing two-dimensional Dirac material channels with tapered energy band structures, combined with appropriate energy band structures and material selection.
It has achieved a significant improvement in data retention capability under the premise of hundreds of picosecond programming speeds, and the data retention time can reach more than 10 years, combining high-speed programming of volatile memory and long-term data retention of non-volatile memory.
Smart Images
Figure CN120129245A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to a memory with charge super-injection and a preparation method thereof. Background Art
[0002] Currently, mainstream memories globally are classified into two categories, volatile memories and non-volatile memories, according to their ability to retain stored data after power-off. SRAM (Static Random Access Memory) is a type of volatile memory that is currently widely used. Its greatest advantage lies in its ability to achieve high-speed data access and processing. The fastest current SRAM can complete data programming within 1 nanosecond. However, SRAM has a significant drawback, that is, the data retention time is extremely short, usually far less than 1 second, which means that the stored data will be quickly lost after power-off. Therefore, SRAM needs to be refreshed frequently to maintain data stability, which not only increases the power consumption of the system but also leads to its limitations in certain application scenarios. Due to these drawbacks, SRAM is currently mainly used as a small-capacity cache in computers, and its application range is relatively limited. Compared with volatile memories, non-volatile memories can retain data for a long time after power-off. Non-volatile memories represented by silicon-based flash memories, although having a long data retention time (usually up to 10 years), have a slow programming speed, usually at the microsecond level. This speed bottleneck makes traditional flash memories difficult to meet the current high-speed storage requirements, so they are mainly applied to low-speed storage fields with low speed requirements, such as embedded systems, mobile device storage, etc.
[0003] Therefore, volatile memories and non-volatile memories each have their own unique advantages and limitations. Volatile memories can achieve high-speed programming, but their data retention time is extremely short, and the stored data will be quickly lost once power is off. Different from volatile memories, non-volatile memories can continue to retain the stored data after power-off, which gives them obvious advantages in long-term data storage and backup. However, their programming speed is low, and this speed bottleneck makes non-volatile memories difficult to meet the requirements of high-speed data access, especially showing significant disadvantages in high-performance applications that require frequent reading and writing. Summary of the Invention
[0004] The purpose of the present invention is to provide a memory based on two-dimensional Dirac materials with charge super-injection and a preparation method thereof, which can significantly improve the data retention ability while maintaining a programming speed at the picosecond level of hundreds.
[0005] The memory based on charge super-injection of two-dimensional Dirac materials of the present invention has a structure including: a substrate, a gate located on the substrate, a barrier layer covering the substrate and the gate, a charge storage layer located on the barrier layer, a tunneling layer located on the charge storage layer, a channel located on the tunneling layer, a source electrode and a drain electrode located on the channel; wherein:
[0006] The channel material uses two-dimensional Dirac materials with a conical energy band structure, and the electron affinity of the channel material is greater than that of the tunneling layer material; at the same time, the electron affinity of the charge storage layer material is greater than that of the tunneling layer and the barrier layer, and the band gap width of the charge storage layer material is less than that of the tunneling layer and the barrier layer; meeting the above energy band structure design principle, the tunneling layer, the charge storage layer, and the barrier layer can form a potential well, so as to ensure that after the charge is injected from the channel into the charge storage layer, it can be maintained therein for a long time.
[0007] Since the channel material uses two-dimensional Dirac materials, the effective mass of the carriers in the two-dimensional Dirac materials is very small, the mean free path is long, and the scattering of the carriers is weak. Under the condition of an applied voltage that does not damage the device structure, the transverse field strength distribution in the two-dimensional Dirac material channel is relatively uniform, and the carriers can be accelerated throughout the channel and continuously obtain energy from the electric field to achieve charge super-injection.
[0008] Furthermore:
[0009] The substrate material is selected from rigid Si, SiO 2 , Al 2 O 3 , HfO 2 ;
[0010] The gate material is selected from one metal or a stack of multiple metals such as Cr, Pt, Au, Ti, Pd, etc.;
[0011] The barrier layer material is selected from dielectrics such as SiO 2 , Al 2 O 3 , HfO 2 , Si 3 N 4 , ZrO 2 , hBN, etc.;
[0012] The charge storage layer material is selected from materials such as HfO x , Au, Pt, graphene, etc.;
[0013] The tunneling layer material is selected from dielectrics such as SiO 2 , Al 2 O 3 , HfO 2 , hBN, etc.;
[0014] The channel material is selected from Dirac materials such as graphene, silicene, and germanene; preferably, the channel thickness is less than 10 nm.
[0015] The source and drain materials are selected from a single metal such as Cr, Pt, Au, Ti, Pd, Bi, Sb or a stack of multiple metals.
[0016] The present invention also performs simulation on this memory. Specifically, TCAD (Semiconductor Process Simulation and Device Simulation Tool) software is used to perform simulation analysis on this memory. The drift-diffusion approximation is used to simulate the transport process of carriers in the two-dimensional Dirac material channel. The high-field velocity saturation model is used to simulate the velocity saturation of carriers under high field strength. The SRH (Shockley-Read-Hall) recombination model and the Auger recombination model are used to describe the carrier exchange process between the conduction band and the valence band. With the source, drain, and gate voltages as boundary conditions, the Poisson equation, the carrier transport equation, and the carrier continuity equation are numerically solved to obtain the physical quantity distribution inside this memory.
[0017] The present invention also provides a preparation method for this memory, and the specific steps are as follows:
[0018] (1) First, lithography and other techniques are used on the substrate to define the position of the metal gate, and physical vapor deposition and other techniques are used to deposit the metal gate and obtain the metal gate through a lift-off process;
[0019] (2) Subsequently, techniques such as atomic layer deposition or dry transfer are used to sequentially deposit or transfer the blocking layer, the charge storage layer, and the tunneling layer;
[0020] (3) Subsequently, the channel is prepared. The channel material is transferred above the tunneling layer using a transfer technique or the channel material is grown above the tunneling layer using chemical vapor deposition technology; subsequently, the uncompleted device is subjected to heat annealing treatment to improve the stability of the structure;
[0021] (4) Finally, the source and drain are prepared using the same method as for preparing the gate.
[0022] The present invention also provides an operation method for this memory, specifically:
[0023] (1) Write electron operation (program the memory to the "1" state), and there are two operation methods:
[0024] (1) Keep the source grounded, apply a positive pulse to the gate and the drain, and a large number of electrons are accelerated from the source to the drain direction in the two-dimensional Dirac material channel to obtain energy and are finally injected into the charge storage layer;
[0025] (2) Keep the gate and source grounded, apply a negative - polarity pulse to the drain. A large number of electrons are accelerated from the drain to the source direction in the two - dimensional Dirac material channel to obtain energy and are finally injected into the charge storage layer.
[0026] (II) Hole - writing operation (programming the memory to the "0" state), there are two operation methods:
[0027] (1) Keep the source grounded, apply negative - polarity pulses to the gate and drain. A large number of holes are accelerated from the source to the drain direction in the two - dimensional Dirac material channel to obtain energy and are finally injected into the charge storage layer;
[0028] (2) Keep the gate and source grounded, apply a positive - polarity pulse to the drain. A large number of holes are accelerated from the drain to the source direction in the two - dimensional Dirac material channel to obtain energy and are finally injected into the charge storage layer.
[0029] The memory based on charge super - injection of two - dimensional Dirac materials of the present invention has a programming speed of up to several hundred picoseconds, and at the same time, the data retention ability can reach more than 10 years, fully combining the advantages of traditional volatile memories and non - volatile memories. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic diagram of the memory structure based on charge super - injection of two - dimensional Dirac materials.
[0031] Figure 2 It is a schematic diagram of the energy band structure in the vertical channel direction of the memory based on charge super - injection of two - dimensional Dirac materials.
[0032] Figure 3 It is the transverse field strength distribution curve in the two - dimensional Dirac material channel of the memory when an appropriate voltage is applied.
[0033] Figure 4 It is the curve of the maximum value of the transverse field strength in the two - dimensional Dirac material channel varying with the channel thickness obtained by TCAD software simulation.
[0034] Figure 5 It is a schematic diagram of the preparation process of the memory based on charge super - injection of two - dimensional Dirac materials.
[0035] Reference numerals in the figure: 1 is the channel, 2 is the tunneling layer, 3 is the charge storage layer, 4 is the blocking layer, 5 is the substrate, 6 is the source, 7 is the drain, and 8 is the gate. DETAILED DESCRIPTION OF THE INVENTION
[0036] The structure of the memory of the present invention is as Figure 1As shown, it includes: a substrate, a gate located on the substrate, a barrier layer covering the substrate and the gate, a charge storage layer located on the barrier layer, a tunneling layer located on the charge storage layer, a channel located on the tunneling layer, a source electrode and a drain electrode located on the channel.
[0037] The substrate of the memory is preferably a rigid substrate such as Si, SiO 2 , Al 2 O 3 , HfO 2 ;
[0038] The gate of the memory is preferably a stack of one or more metals such as Cr, Pt, Au, Ti, Pd, etc.;
[0039] The barrier layer of the memory is preferably a dielectric such as SiO 2 , Al 2 O 3 , HfO 2 , Si 3 N 4 , ZrO 2 , hBN, etc.;
[0040] The charge storage layer of the memory is preferably a material such as HfO x , Au, Pt, graphene, etc.;
[0041] The tunneling layer of the memory is preferably a dielectric such as SiO 2 , Al 2 O 3 , HfO 2 , hBN, etc.;
[0042] The channel of the memory is preferably a Dirac material such as graphene, silicene, germanene, etc.;
[0043] The source electrode and the drain electrode of the memory are preferably a stack of one or more metals such as Cr, Pt, Au, Ti, Pd, Bi, Sb, etc.
[0044] An example of the material selection for a typical such memory is: the gate is selected as Pt metal; the barrier layer is selected as Al 2 O 3 ; the charge storage layer is selected as HfO 2 ; the tunneling layer is selected as hBN; the channel is selected as graphene; the source electrode and the drain electrode are selected as Au metal.
[0045] Such as Figure 2As shown. The channel material of the memory should be selected as a two-dimensional Dirac material with a conical energy band structure, and the electron affinity of the channel material should be greater than that of the tunneling layer material; the electron affinity of the charge storage layer material of the memory should be greater than the electron affinities of both the tunneling layer and the blocking layer, and the band gap width of the charge storage layer material is preferably less than the band gap widths of the tunneling layer and the blocking layer. Meeting the above energy band structure design principles, the tunneling layer, the charge storage layer, and the blocking layer can form a potential well, which can ensure that after the charge is injected from the channel into the charge storage layer, it can be maintained therein for a long time.
[0046] Since the channel material of the memory should be selected as a two-dimensional Dirac material with a conical energy band structure, the effective mass of the carriers in the two-dimensional Dirac material is very small, the mean free path is long, and the carriers are weakly scattered. As Figure 3 shown, compared with the semiconductor material channel, under the condition of the same applied voltage, the transverse field strength distribution in the two-dimensional Dirac material channel is relatively uniform, and the carriers can be uniformly accelerated throughout the channel and continuously obtain energy from the electric field to achieve super-injection of charges.
[0047] The present invention also performs simulation on the memory. The TCAD (Semiconductor Process Simulation and Device Simulation Tool) software is used to perform simulation analysis on the memory, and the drift-diffusion approximation is used to simulate the transport process of carriers in the two-dimensional Dirac material channel. The high-field velocity saturation model is used to simulate the velocity saturation of carriers under high field strength. The SRH (Shockley-Read-Hall) recombination model and the Auger recombination model are used to describe the carrier exchange process between the conduction band and the valence band. With the source, drain, and gate voltages as boundary conditions, the Poisson equation, the carrier transport equation, and the carrier continuity equation are numerically solved to obtain the physical quantity distribution inside the memory. As Figure 4 shown, using the above simulation design, the curve of the maximum value of the transverse field strength in the two-dimensional Dirac material channel of the memory changing with the channel thickness under the condition of the same applied voltage is obtained. It can be seen that as the thickness decreases, the maximum value of the transverse field strength in the two-dimensional Dirac material channel gradually increases, the energy obtained by the carriers accelerating in the channel increases, and the charge injection is enhanced accordingly. Therefore, in order to improve the performance of the memory, the two-dimensional Dirac material channel should not be too thick, and generally it is preferably below 10 nm.
[0048] The present invention provides a preparation method for the memory. Taking a typical material selection of the memory as an example, its flowchart is as Figure 5 shown. The specific steps are as follows:
[0049] (1) First, use techniques such as photolithography or electron beam lithography on the substrate to define the position of the metal gate. Deposit the metal gate using techniques such as physical vapor deposition and finally obtain the metal gate through a lift-off process. The metal material can be selected from elemental substances such as Au, Pt, Cr, Ti, or a stack of multiple metals.
[0050] (2) Deposit Al 2 O 3 (barrier layer) and HfO 2 (charge storage layer) in sequence using techniques such as atomic layer deposition or chemical vapor deposition.
[0051] (3) Transfer the two-dimensional material. First, transfer hBN (tunneling layer) to the position above the gate, and then transfer graphene (channel) above the hBN.
[0052] (4) Perform a heat annealing treatment on the uncompleted device to improve the stability of the structure.
[0053] (5) Finally, fabricate the source and drain using the same method as in step (1) for fabricating the gate.
[0054] The present invention provides an operation method for this memory. For the write electron operation (programming the memory to the "1" state), there are two operation methods: 1. Keep the source grounded, apply a positive pulse to the gate and the drain, and a large number of electrons are accelerated from the source to the drain direction in the two-dimensional Dirac material channel to obtain energy and finally injected into the charge storage layer; 2. Keep the gate and the source grounded, apply a negative pulse to the drain, and a large number of electrons are accelerated from the drain to the source direction in the two-dimensional Dirac material channel to obtain energy and finally injected into the charge storage layer. For the write hole operation (programming the memory to the "0" state), there are two operation methods: 1. Keep the source grounded, apply a negative pulse to the gate and the drain, and a large number of holes are accelerated from the source to the drain direction in the two-dimensional Dirac material channel to obtain energy and finally injected into the charge storage layer; 2. Keep the gate and the source grounded, apply a positive pulse to the drain, and a large number of holes are accelerated from the drain to the source direction in the two-dimensional Dirac material channel to obtain energy and finally injected into the charge storage layer.
Claims
1. A memory based on charge superinjection of two-dimensional Dirac materials, characterized in that: include: A substrate, a gate on the substrate, a barrier layer covering the substrate and the gate, a charge storage layer on the barrier layer, a tunneling layer on the charge storage layer, a channel on the tunneling layer, and a source and a drain on the channel; wherein: The channel material is a two-dimensional Dirac material with a conical energy band structure, and the electron affinity of the channel material is greater than the electron affinity of the tunneling layer material; At the same time, the electron affinity of the charge storage layer material is greater than the electron affinity of the tunneling layer and the blocking layer, and the bandgap width of the charge storage layer material is smaller than the bandgap width of the tunneling layer and the blocking layer; if the above-mentioned band structure design principles are met, the tunneling layer, the charge storage layer, and the blocking layer can form a potential well, thereby ensuring that after the charge is injected into the charge storage layer from the channel, it can be maintained therein for a long time.
2. The memory according to claim 1, characterized in that: Under the condition of applied voltage without damaging the device structure, the lateral field strength in the two-dimensional Dirac material channel is evenly distributed, the carriers are accelerated throughout the channel and continuously obtain energy from the electric field to achieve superinjection of charge.
3. The memory according to claim 1, characterized in that: The substrate material of the memory is selected from rigid Si, SiO2, Al2O3, HfO2; The gate material of the memory is selected from one metal or a stack of multiple metals among Cr, Pt, Au, Ti and Pd; The barrier layer material of the memory is selected from SiO2, Al2O3, HfO2, Si3N4, ZrO2, and hBN medium; The charge storage layer material of the memory is selected from HfO x , Au, Pt, graphene; The tunneling layer material of the memory is selected from dielectric SiO2, Al2O3, HfO2, and hBN; The channel material of the memory is selected from Dirac materials graphene, silicene, and germanene; the channel thickness is less than 10nm; The source and drain materials of the memory are selected from one metal or a stack of multiple metals including Cr, Pt, Au, Ti, Pd, Bi and Sb.
4. The method for preparing a memory according to any one of claims 1 to 3, characterized in that: The specific steps are: (1) First, a position of a metal gate is defined on a substrate using a photolithography technique, a metal gate is deposited using a physical vapor deposition technique, and a metal gate is obtained through a lift-off process; (2) subsequently using atomic layer deposition or dry transfer technology to sequentially deposit or transfer a blocking layer, a charge storage layer, and a tunneling layer; (3) Then, the channel is prepared, and the channel material is transferred to the top of the tunneling layer by using a transfer technology, or the channel material is grown on the top of the tunneling layer by using a chemical vapor deposition technology; then, the unfinished device is subjected to a heating annealing treatment to improve the stability of the structure; (4) Finally, the source and drain are prepared using the same method as the gate.
5. The memory operation method according to any one of claims 1 to 3, characterized in that: (I) Write electronic operation, that is, programming the memory to the "1" state, there are two operation methods: (1) Keep the source grounded, apply positive polarity pulses to the gate and drain, and a large number of electrons are accelerated from the source to the drain in the two-dimensional Dirac material channel to gain energy and are finally injected into the charge storage layer; (2) Keep the gate and source grounded, apply a negative polarity pulse to the drain, and a large number of electrons are accelerated from the drain to the source in the two-dimensional Dirac material channel to gain energy and finally injected into the charge storage layer; (ii) Write hole operation, that is, programming the memory to the "0" state, there are two operation methods: (1) Keep the source grounded, apply negative polarity pulses to the gate and drain, and a large number of holes are accelerated from the source to the drain in the two-dimensional Dirac material channel to gain energy and finally injected into the charge storage layer; (2) Keep the gate and source grounded, apply a positive pulse to the drain, and a large number of holes are accelerated from the drain to the source in the two-dimensional Dirac material channel to gain energy and finally injected into the charge storage layer.