Multi-FPGA module updating method based on XDMA in heterogeneous platform

Abstract

The invention provides a multi-FPGA (Field Programmable Gate Array) module updating method based on XDMA (Extensible Direct Memory Access) in a heterogeneous platform, which comprises a main control module as a receiving system task requirement and an FPGA module as a co-processing module, wherein the number of the FPGA modules can be zero or multiple. The method is realized based on a PCIe bus, the main control module is interconnected with the FPGA module through the PCIe bus, state information is acquired through a general purpose input / output (GPIO) signal, and according to different slot positions and function requirements, a single-block or multi-block FPGA program is updated under the condition that other functions of the whole machine are not influenced. The step of updating the FPGA module by the main control module under the task requirement is introduced in detail. The scheme is accurate and effective, the function of the FPGA module can be updated under the condition that the system function is not influenced, and the application function flexibility under the heterogeneous platform is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and particularly to a method for updating multiple FPGA modules based on XDMA in a heterogeneous platform. Background Art

[0002] In an embedded heterogeneous platform, the FPGA module, as a coprocessor module, can perform data reception, transmission, and preprocessing at the front end of the system. Based on the programmable characteristics of the FPGA, different functions can be implemented in the system. However, the FPGA update program needs to be updated online through JTAG or other main controllers, and the function takes effect after reset or restart. Therefore, in the system, it is inconvenient to change the function of the FPGA module after it is fixed. When there are multiple function requirements in the system, adding modules is mostly used, which will lead to problems such as increased cost and reduced reliability. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for updating multiple FPGA modules based on XDMA in a heterogeneous platform, which updates the functions of FPGA modules according to the slot numbers of different slots through the PCIe bus interconnected with the main control module.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] The present invention provides a method for updating multiple FPGA modules based on XDMA in a heterogeneous platform, including the following steps:

[0006] S1. When the FPGA function update requirement is obtained in the heterogeneous platform system, the actual number of FPGA modules in the heterogeneous platform system is obtained by repeatedly reading the FPGA GPIO flag;

[0007] S2. After obtaining the number of FPGA modules, check the slot numbers of each module, and update the programs of one or more to-be-determined FPGA modules according to the functions of the FPGA modules in each slot pre-allocated in the system and the application requirements of the heterogeneous platform system;

[0008] S3. The FPGA module is interconnected with the main control module through the PCle bus. Since the scale of the FPGA application program is small, the PCIe bus uses the 1x mode, and the main control module in the heterogeneous platform system updates the FPGA module program through the XDMA function;

[0009] S4. The FPGA module needs to build an ICAP layout dynamic reconfiguration IP core based on the PCIe bus, and after the program is updated, it is updated through the channel, and the new function can be run without restarting;

[0010] S5. In the heterogeneous platform system, the master control module stores multiple FPGA function programs in the memory, obtains the FPGA application program through the network channel, and updates the program according to requirements.

[0011] Furthermore, in S1, the actual number of FPGA modules is judged as follows: there are multiple subsystems in the heterogeneous platform system, each subsystem has multiple FPGA modules, and there are difficulties in maintenance and update. By judging the specific FPGA GPIO flag without disassembling the heterogeneous platform system, the number of modules in the heterogeneous platform system is judged.

[0012] Furthermore, after obtaining the FPGA GPIO flag, to prevent errors in single reading, multiple readings are performed to eliminate the transmission error code of the GPIO flag during the power-on process, and to prevent the PCIe bus from crashing due to incorrect update.

[0013] Furthermore, the master control module is interconnected with the FPGA module through 1xPCIe. Based on the PCIe bus, the program to be updated is sent to each FPGA module through the XDMA function.

[0014] Furthermore, in the FPGA module with the ICAP function pre-layout, after the program update is completed, no restart or reset operation is required. Without affecting the functions of the heterogeneous platform system, the functions of the FPGA module are updated and the module continues to run.

[0015] The beneficial effects of the present invention: It describes that the FPGA modules in the system are interconnected with the master control through the PCIe bus. Based on the XDMA function, the problem of system function interruption after the FPGA program is updated is solved.

[0016] This patent is applicable to a multi-FPGA module system. By identifying the location (slot) of each FPGA module and based on the system task requirements, the online update of multiple FPGA modules is completed without affecting the system functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of a multi-FPGA module update method based on XDMA in a heterogeneous platform;

[0018] Figure 2 It is a flowchart of the heterogeneous platform system;

[0019] Figure 3 It is a flowchart of the FPGA update program;

[0020] Figure 4 It is a flowchart of the FPGA module update during the working process. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] A method for updating multiple FPGA modules based on XDMA in a heterogeneous platform to make up for the deficiencies that in the case of multiple FPGAs, the update program takes a long time and the system needs to be powered off and restarted. The main control module accepts the system task requirements, determines what functions the FPGA needs to execute, judges the FLAG value in the system, and takes the FLAG value as a condition to determine whether to update 0 or multiple FPGA modules subsequently. When multiple FPGA updates are required, by judging the slot number, the update of the required function is executed. The work flow is as Figure 1 shown.

[0023] In the heterogeneous platform system, in addition to the PCIe interface, the FPGA module inside is interconnected with the main control module through the GPIO and UART interfaces. Inside the main control, it is transmitted to the main control CPU through the CPLD. The principle block diagram is as Figure 2 shown.

[0024] FPGA Module Quantity Judgment Mechanism

[0025] In complex system signal processing, it is possible that multiple modules all have FPGA chips. To solve the difficult situation of updating the FPGA logic function during system function upgrade, change or maintenance troubleshooting, an FPGA module quantity judgment mechanism is proposed;

[0026] In the heterogeneous platform system, there are multiple FPGA chips coexisting. In the system, by receiving the GPIO flag, the FPGA module quantity information is obtained. If an FPGA module is inserted, the FPGA module will set the interconnected GPIO signal to 1. The heterogeneous platform system interconnects the FPGA module and the main control module with multiple reserved GPIO signals for transmitting the presence signal. The main control module judges the number of FPGA modules in the system by reading the presence signal and checking the number of specific presence signals.

[0027] Multi-FPGA Module Program Update Mechanism

[0028] As Figure 3 shown, if there is a requirement to update the FPGA logic function in the system, the requirement is sent to the main control module. After receiving the requirement, the main control module reads the obtained number of FPGA GPIO flag signals. The main control module reads the GPIO flag multiple times to prevent misreading the quantity and causing the system to freeze during the update process.

[0029] When the GPIO flags are obtained consistently for multiple times, the number of FPGA chips obtained is reported to the heterogeneous platform system. After the heterogeneous platform system obtains the number of FPGAs, it determines whether the functional modules are in place. According to the different application function requirements of the system and the slot numbers, the main control module updates the programs of each FPGA through the PCIe bus.

[0030] Based on the XDMA function of PCIe and the local dynamic reconfiguration function of the FPGA module, new functions can be run without resetting or restarting.

[0031] FPGA module update mechanism during operation

[0032] Such as Figure 4 As shown, in the current functional situation, some FPGAs need to be temporarily used for other functions. In this case, power-off restart or reset operations cannot be performed.

[0033] To meet the need to update the functions of some FPGAs during operation, this method can update the programs of some idle or no-longer-needed FPGA functions based on the local dynamic reconfiguration technology of the FPGA by judging the number of FPGAs in place of each module without affecting the continuous operation function of the system.

[0034] During the operation of the system, if it is necessary to update the functions of some FPGAs, the system issues an update instruction. Based on the relevant information of judging the FPGA GPIO flags and slot numbers, the system performs function reconfiguration of the FPGA through the PCIe bus. After the update is completed, subsequent function execution can be seamlessly connected without power-off or reset.

[0035] The above embodiments only represent the implementation manners of the present invention, and the description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be based on the appended claims.

Claims

1. A multi-FPGA module update method based on XDMA in a heterogeneous platform, characterized in that: The following steps are involved: S1. When the FPGA function update requirement is obtained in the heterogeneous platform system, the actual number of FPGA modules in the heterogeneous platform system is obtained by reading the FPGA GPIO flag multiple times; S2. After obtaining the number of FPGA modules, check the slot numbers of each module, and update the programs of one or more FPGA modules to be determined according to the functions of the FPGA modules in each slot allocated in advance in the system and the application requirements of the heterogeneous platform system; S3, the FPGA module is interconnected with the main control module through the PCle bus. Due to the small scale of the FPGA application, the PCIe bus uses the 1x mode. In the heterogeneous platform system, the main control module updates the FPGA module program through the XDMA function; S4, FPGA module needs to build ICAP layout based on PCIe bus dynamic reconstruction IP core, update through the channel after updating the program, and run the new function without restarting; S5. In the heterogeneous platform system, the main control module stores a variety of FPGA function programs in the memory, obtains FPGA application programs through the network channel, and updates the programs according to needs.

2. The XDMA-based multi-FPGA module update method in a heterogeneous platform according to claim 1, characterized in that: In S1, the actual number of FPGA modules is determined as follows: there are multiple subsystems in the heterogeneous platform system, and there are multiple FPGA modules in the subsystems, which makes maintenance and updating difficult. By judging the specific FPGA GPIO flag, the number of modules in the heterogeneous platform system is determined without disassembling the heterogeneous platform system.

3. The XDMA-based multi-FPGA module update method in a heterogeneous platform according to claim 2, characterized in that: After obtaining the FPGA GPIO flag, prevent errors in a single read and eliminate GPIO flag transmission errors during the power-on process by reading multiple times to prevent erroneous updates from causing PCIe bus crashes.

4. The XDMA-based multi-FPGA module update method in a heterogeneous platform according to claim 3, characterized in that: The main control module and the FPGA module are interconnected through 1xPCIe. Based on the PCIe bus, the program to be updated is sent to each FPGA module through the XDMA function.

5. The XDMA-based multi-FPGA module update method in a heterogeneous platform according to claim 4, characterized in that: In the FPGA module with the ICAP function pre-arranged, after the program is updated, there is no need to restart or reset. The FPGA module function is updated and continues to run without affecting the heterogeneous platform system function.

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