Multi-protocol video signal quality analyzer equipment

Abstract

The invention discloses multi-protocol video signal quality analyzer equipment. The multi-protocol video signal quality analyzer equipment comprises an FPGA (Field Programmable Gate Array) Virtex subsystem, an FPGA ZYNQ subsystem, a multi-channel high-speed video signal acquisition subsystem, an analog video signal input module, a power supply module, a clock module and a PC (Personal Computer). According to the invention, consistency test, protocol analysis and signal quality analysis of various mainstream video protocols such as LVDS, HDMI, DisplayPort, FPD-LINK and RGB in an avionics display system are realized, static image analysis, video stream dynamic detection and physical layer signal integrity test are supported, and high-precision signal acquisition and multi-protocol compatibility analysis capabilities are realized. The system integrates the functions of a high-speed oscilloscope, a logic analyzer, a protocol analyzer and a video signal generator, achieves the integrated, standardized and self-loopback test of multi-protocol video equipment, remarkably improves the test efficiency and precision, and has important engineering application values for the research and development verification, production quality inspection and fault diagnosis of display equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed video signal testing, and particularly to a multi-protocol video signal quality analyzer device, aiming to achieve consistency testing, protocol parsing, and signal quality analysis of mainstream video protocols in an avionics display system, and at the same time support static image parsing, video flow dynamic detection, and physical layer signal integrity evaluation. Background Art

[0002] In the fields of avionics, industrial control, and medical imaging, video display systems need to support a variety of high-resolution video protocols and ensure the stability of signal transmission and image quality. Currently, the mainstream video protocols on the market include LVDS, HDMI, DisplayPort, FPD-LINK, and RGB video protocols. Traditional testing methods rely on the combination of discrete instruments (such as oscilloscopes, logic analyzers, protocol analyzers, etc.), which have problems such as equipment redundancy, complex operation, poor protocol compatibility, and are difficult to meet the requirements of avionics equipment for high-reliability and high-efficiency testing. In the prior art, single-function video analyzers usually only support limited protocols or lack the ability to jointly analyze physical layer signals and protocol layers, resulting in fragmented test data and unable to comprehensively evaluate the overall performance of the video system. In addition, the stringent requirements of avionics equipment for the anti-interference and real-time performance of the test environment further increase the testing difficulty. Therefore, there is an urgent need for an integrated test device that integrates multi-protocol support, high-precision signal acquisition, and intelligent analysis functions to solve the problems of low testing efficiency, insufficient compatibility, and incomplete data analysis in the prior art. Summary of the Invention

[0003] To solve the above technical problems, the present invention provides the following technical solutions: A multi-protocol video signal quality analyzer device, which includes a Virtex subsystem of FPGA programmable gate array, a ZYNQ subsystem of FPGA programmable gate array, a multi-channel high-speed video signal acquisition subsystem, an analog video signal input module, a power supply module, a clock module, and a PC; The FPGA programmable logic Virtex subsystem is respectively connected to the FPGA programmable gate array ZYNQ subsystem, the multi-channel high-speed video signal acquisition subsystem, the power supply module, the clock module, and the PC; the FPGA programmable logic Virtex subsystem and the FPGA programmable gate array ZYNQ subsystem are connected through GTY Serdes with a maximum support of 32.75 Gbps and LVDS data lines with a maximum support of 1.25 Gbps to achieve high-bandwidth high-definition video data transmission; the FPGA programmable logic Virtex subsystem and the multi-channel high-speed video signal acquisition subsystem are connected through the first FMC+ interface and the second FMC+ interface to support the transmission of digital signal data and control signals after 80-channel GTY Serdes analog-to-digital conversion; the FPGA programmable logic Virtex subsystem is connected to the power supply module to meet the power supply requirements of multiple power supply voltages and currents; the FPGA programmable logic Virtex subsystem is connected to the clock module to meet the multi-channel clock requirements of each interface; the FPGA programmable logic Virtex subsystem is connected to the PC to achieve the output of video protocol detection report results and user interaction control functions.

[0004] The FPGA programmable logic Virtex subsystem includes a Virtex chip, a 20GB 16bits DDR4 memory, a first Flash module, a first FMC+ interface, a QSFP+ interface, an RGB video input / output module, and an FPD-LINK video input / output module; The Virtex chip is respectively connected to the 20GB 16bits DDR4 memory, the first Flash module, the first FMC+ interface, the QSFP+ interface, the RGB video input / output module, and the FPD-LINK video input / output module; the Virtex chip realizes the analysis of analog video signal quality and the parsing of digital video protocols; the 20GB 16bits DDR4 memory realizes the storage of high-bandwidth and large-capacity analog video signals and digital video signals; the first Flash module realizes the storage of configuration data, and the user logic is automatically loaded after the Virtex chip is powered on; the first FMC+ interface is connected to the second FMC+ interface in the multi-channel high-speed video signal acquisition subsystem to realize the transmission of the analog video signal collected by the ADC in the multi-channel high-speed video signal acquisition subsystem; the QSFP+ interface is connected to the PC to realize the output of the analysis of analog video signal quality and the parsing results of digital video protocols and the transmission of user interaction control instructions; the RGB video input / output module and the FPD-LINK video input / output module respectively realize the reception, encoding / decoding, and output of RGB video and FPD-LINK video, and perform self-loop detection of standard test video data.

[0005] The FPGA programmable gate array ZYNQ subsystem is respectively connected to the FPGA programmable logic Virtex subsystem, the power supply module, and the clock module; the FPGA programmable gate array ZYNQ subsystem includes a ZYNQ chip, a 16GB 64bits DDR4 memory, an 8GB 64bits DDR4 memory, a second Flash module, an SD card module, a USB-UART module, an SFP+ interface, an HDMI video input / output module, an LVDS video input interface, an LVDS video output interface, and a DisplayPort video output interface; The ZYNQ chip is respectively connected to the Virtex chip, the 16GB 64bits DDR4 memory, the 8GB 64bits DDR4 memory, the second Flash module, the SD card module, the USB-UART module, the SFP+ interface, the HDMI video input / output module, the LVDS video input interface, the LVDS video output interface, and the DisplayPort video output interface; the ZYNQ chip implements the parsing of HDMI and LVDS digital video protocols and transmits the parsing results to the Virtex chip; the 16GB 64bits DDR4 memory implements the storage of high-definition digital video signals processed by the PL end of the ZYNQ chip; the 8GB 64bits DDR4 memory implements the storage of high-definition digital video signals processed by the PS end of the ZYNQ chip; the second Flash module and the SD card module implement the storage of configuration data, and the ZYNQ chip automatically loads user logic after power-on; the USB-UART module implements the conversion of USB signals to UART; the SFP+ interface implements the remote data transmission function; the HDMI video input / output module implements the reception, encoding / decoding, and output of HDMI video and performs self-loop detection of standard test video data; the LVDS video input interface implements the reception of LVDS video; the LVDS video output interface and the DisplayPort video output interface output standard LVDS and DisplayPort test video data.

[0006] The multi-channel high-speed video signal acquisition subsystem is respectively connected to the analog video signal input module, the power supply module, and the clock module; the multi-channel high-speed video signal acquisition subsystem includes an LVDS analog video signal conditioning module, a TMDS analog video signal conditioning module, an FPD-LINK analog video signal conditioning module, an RGB analog video signal conditioning module, a DP analog video signal conditioning module, an analog signal selection module, an ADC module, a second FMC+ interface, a subsystem clock module, a subsystem power supply module, and a configuration module; The subsystem power module is respectively connected to the LVDS analog video signal conditioning module, the TMDS analog video signal conditioning module, the FPD-LINK analog video signal conditioning module, the RGB analog video signal conditioning module, the DP analog video signal conditioning module, the analog signal selection module, the ADC module, the second FMC+ interface, the subsystem clock module and the configuration module, and supplies power to each module respectively; The configuration module is respectively connected to the LVDS analog video signal conditioning module, the TMDS analog video signal conditioning module, the FPD-LINK analog video signal conditioning module, the RGB analog video signal conditioning module, the DP analog video signal conditioning module, the analog signal selection module, the ADC module, the second FMC+ interface, and the subsystem clock module, and realizes the chip SPI or IIC parameter configuration function for each module; The LVDS analog video signal conditioning module, the TMDS analog video signal conditioning module, the FPD-LINK analog video signal conditioning module, the RGB analog video signal conditioning module, and the DP analog video signal conditioning module are connected to the analog signal selection module; the analog signal selection module is connected to the ADC module; the ADC module is connected to the second FMC+ interface; the second FMC+ interface is connected to the first FMC+ interface; each analog video signal conditioning module conditions the input analog video signal to the voltage range that meets the ADC input analog signal, and the analog signal selection module selects the analog video signal of one video protocol and inputs it to the ADC module; the ADC module converts the analog video signal into a digital signal and outputs it to the FMC+ interface.

[0007] The analog video signal input module includes an LVDS analog video signal input interface, an HDMI analog video signal input interface, an FPD-LINK analog video signal input interface, an RGB analog video signal input interface, a DP analog video signal input interface, and an SMA high-speed interface group; The LVDS analog video signal input interface, the HDMI analog video signal input interface, the FPD-LINK analog video signal input interface, the RGB analog video signal input interface, and the DP analog video signal input interface are respectively connected to the SMA high-speed interface group; the SMA high-speed interface group respectively transfers the input analog video signal to the LVDS analog video signal conditioning module, the TMDS analog video signal conditioning module, the FPD-LINK analog video signal conditioning module, the RGB analog video signal conditioning module, and the DP analog video signal conditioning module.

[0008] The power module is respectively connected to the FPGA programmable gate array Virtex subsystem, the FPGA programmable gate array ZYNQ subsystem, and the multi-channel high-speed video signal acquisition subsystem, meeting the power supply voltage and current requirements of each subsystem circuit.

[0009] The clock module is respectively connected to the Virtex subsystem of the FPGA programmable gate array, the ZYNQ subsystem of the FPGA programmable gate array, and the multi-channel high-speed video signal acquisition subsystem, meeting the circuit clock requirements of each subsystem.

[0010] The RGB video input / output module includes a first level conversion chip, a second level conversion chip, an RGB digital video signal input AD9882 chip, an RGB digital video signal output ADV7125 chip, an RGB digital video signal input interface, and an RGB digital video signal output interface; The RGB digital video signal input interface and the RGB digital video signal output interface are respectively connected to the RGB digital video signal input AD9882 chip and the RGB digital video signal output ADV7125 chip; the RGB digital video signal input AD9882 chip and the RGB digital video signal output ADV7125 chip are respectively connected to the first level conversion chip and the second level conversion chip; the first level conversion chip and the second level conversion chip are connected to the Virtex chip; the RGB digital video signal input AD9882 chip converts the RGB digital video signal with a 3.3V level standard into an RGB888 24-bit parallel video signal; the first level conversion chip converts the data with a 3.3V level standard into data with a 1.8V level standard and inputs it to the Virtex chip; the Virtex chip outputs an RGB888 24-bit parallel video signal with a 1.8V level standard, which is converted into a 3.3V level standard through the second level conversion chip; the RGB digital video signal output ADV7125 chip converts the parallel video data with a 3.3V level standard into an RGB digital video signal and outputs it through the RGB digital video signal output interface.

[0011] The FPD-LINK video input / output module includes an FPD-LINK digital video signal input deserialization chip DS92LV2422, an FPD-LINK digital video signal output deserialization chip DS92LV2422, an FPD-LINK digital video signal input interface, and an FPD-LINK digital video signal output interface; The FPD-LINK digital video signal input DS92LV2422 chip and the FPD-LINK digital video signal output DS92LV2422 chip are respectively connected to the FPD-LINK digital video signal input interface and the FPD-LINK digital video signal output interface; the FPD-LINK digital video signal input DS92LV2422 chip converts the LVDS differential signal into parallel RGB digital video data and inputs it to the Virtex chip; the FPD-LINK digital video signal output DS92LV2422 chip converts the parallel RGB digital video data into LVDS differential signals and outputs them to the FPD-LINK digital video signal output interface.

[0012] The HDMI video input and output module includes a 2K HDMI digital video signal input SiI7171 chip, a 2K HDMI digital video signal output SiI7170 chip, a first 4K HDMI digital video signal transceiver GSV2011 chip, a second 4K HDMI digital video signal transceiver GSV2011 chip, a 2K HDMI digital video signal input interface, a 2K HDMI digital video signal output interface, a 4K HDMI digital video signal input interface, and a 4K HDMI digital video signal output interface; The 2K HDMI digital video signal input interface, the 2K HDMI digital video signal output interface, the 4K HDMI digital video signal input interface, and the 4K HDMI digital video signal output interface are respectively connected to the 2K HDMI digital video signal input SiI7171 chip, the 2K HDMI digital video signal output SiI7170 chip, the first 4K HDMI digital video signal transceiver GSV2011 chip, and the second 4K HDMI digital video signal transceiver GSV2011 chip; the 2K HDMI digital video signal input SiI7171 chip converts the 2K HDMI digital video data into parallel RGB digital video data and inputs it to the Virtex chip; the 2K HDMI digital video signal output SiI7170 chip converts the parallel RGB digital video data into 2K HDMI digital video data and outputs it to the 2K HDMI digital video signal output interface; the first 4K HDMI digital video signal transceiver GSV2011 chip converts the 4K HDMI digital video data into parallel RGB digital video data and inputs it to the Virtex chip; the second 4K HDMI digital video signal transceiver GSV2011 chip converts the parallel RGB digital video data into 4K HDMI digital video data and outputs it to the 4K HDMI digital video signal output interface.

[0013] The ADC module uses the radio frequency sampling gigabit sampling analog-to-digital converter ADC12DJ5200RF chip.

[0014] The first FMC+ interface and the second FMC+ interface respectively use ASP-184330-01 and ASP-184329-01 connectors, and the two can be tightly connected to each other.

[0015] The PC uses C language to develop a multi-protocol video standardization test and automated report generation software program.

[0016] While the RGB video input / output module, FPD-LINK video input / output module, HDMI video input / output module, LVDS video input interface, LVDS video output interface, and DisplayPort video output interface support a resolution of 2K@60HZ, they also support input / output of multiple non-standard resolutions, including 1680x1050@60Hz and 1440x1050@60Hz resolutions.

[0017] The present invention not only supports external video signal input testing, but also can output standard video signals through the RGB video input / output module, FPD-LINK video input / output module, HDMI video input / output module, LVDS video output interface, and DisplayPort video output interface to perform multi-protocol standard video self-loop testing.

[0018] The advantages of the present invention are as follows: 1) The present invention has strong multi-protocol compatibility. The present invention can simultaneously support the testing and analysis of multiple mainstream video protocols such as HDMI, DisplayPort, and SDI, solving the problem of single protocol support of traditional testing equipment.

[0019] 2) The present invention provides an integrated, standardized, and self-loop testing platform for mainstream video protocols, integrating the functions of a high-speed oscilloscope, a logic analyzer, a protocol analyzer, and a video signal generator, providing a multi-protocol video standardization test process and automated report generation, realizing the integrated, standardized, and self-loop testing of multi-protocol video devices in the avionics field, significantly improving the testing efficiency and accuracy, reducing the equipment cost and operation complexity, and having important engineering application value for the R & D verification, production quality inspection, and fault diagnosis of display devices.

[0020] 3) The present invention has multiple analog sampling channels, a high analog sampling rate, and a high total sampling bandwidth. The present invention adopts a parallel sampling architecture of 10 10.4GSPS ADC chips ADC12DJ5200RF, and the total sampling bandwidth of the system reaches 104GSPS, which can accurately capture the nanosecond-level signal jitter in the avionics video signal and has a high sampling accuracy compared with traditional testing equipment; 4) The multi-channel synchronization accuracy of the present invention is high. Through the multi-level clock cascading technology, the present invention achieves a synchronization error of less than 100 fs for 10 ADCs, ensuring the ultra-high-precision synchronization of multi-channel video signals.

[0021] 5) While supporting the conventional 2K@60HZ resolution, the present invention also supports the input and output of a variety of non-standard resolutions, such as 1680x1050@60Hz and 1440x1050@60Hz resolutions, and is applicable to the testing of display devices in various scenarios.

[0022] 6) The present invention has an innovative architecture, high performance, and strong processing capabilities. The present invention adopts an innovative heterogeneous computing architecture based on two high-performance FPGA / SoC chips, namely Xilinx Zynq UltraScale+ ZU7EV and Xilinx Virtex UltraScale+ VU9P, to achieve excellent computing performance and data processing capabilities. Through the large-scale parallel computing architecture, the data throughput bottleneck is effectively broken through, and it has advantages such as super strong parallel processing capabilities, extremely low latency, and high-speed data stream processing, realizing high-performance computing, real-time signal processing, and high-bandwidth communication in the system.

[0023] 7) The user interface of the present invention is innovative. It adopts an integrated and professional testing software, providing functions such as automated testing processes, real-time data analysis, and visualization report generation, greatly enhancing the user experience.

[0024] 8) The present invention adopts a fully self-developed hardware system. Through high-density circuit layout and optimized wiring, signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMI) are ensured. Combined with an advanced heat dissipation design, the long-term stable operation of the system is guaranteed, realizing a high-performance and highly reliable hardware platform, which is applicable to high-bandwidth computing, real-time signal processing, and harsh industrial testing environments. Description of the Drawings

[0025] Figure 1 is the system block diagram of the present invention; Figure 2 is the circuit block diagram of the Virtex subsystem of the FPGA programmable gate array; Figure 3 is the circuit block diagram of the ZYNQ subsystem of the FPGA programmable gate array; Figure 4 is the circuit block diagram of the multi-channel high-speed video signal acquisition subsystem; Figure 5 is the circuit block diagram of the analog video signal input module; Figure 6 is the circuit block diagram of the RGB video input / output module; Figure 7 is the circuit block diagram of the FPD-LINK video input / output module; Figure 8 It is a circuit block diagram of the HDMI video input / output module; Figure 9 It is the circuit block diagram of Embodiment 1 of the present invention. Specific embodiments

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0027] Refer to Figure 1 , a multi-protocol video signal quality analyzer device of the present invention specifically includes: FPGA programmable gate array Virtex subsystem 1, FPGA programmable gate array ZYNQ subsystem 2, multi-channel high-speed video signal acquisition subsystem 3, analog video signal input module 4, power supply module 5, clock module 6 and PC 7; The FPGA programmable logic Virtex subsystem 1 is respectively connected to the FPGA programmable gate array ZYNQ subsystem 2, the multi-channel high-speed video signal acquisition subsystem 3, the power supply module 5, the clock module 6 and the PC 7; the FPGA programmable logic Virtex subsystem 1 and the FPGA programmable gate array ZYNQ subsystem 2 are connected through GTY Serdes with a maximum support of 32.75 Gbps and LVDS data lines with a maximum support of 1.25 Gbps to achieve high-bandwidth high-definition video data transmission; the FPGA programmable logic Virtex subsystem 1 and the multi-channel high-speed video signal acquisition subsystem 3 are connected through a high-density FMC connector to support the transmission of digital signal data and control signals after 80-channel GTY Serdes analog-to-digital conversion; the FPGA programmable logic Virtex subsystem 1 is connected to the power supply module 5 to meet the power supply voltage and current requirements of multiple channels; the FPGA programmable logic Virtex subsystem 1 is connected to the clock module 6 to meet the multi-channel clock requirements of each interface; the FPGA programmable logic Virtex subsystem 1 is connected to the PC 7 to achieve the output of video protocol detection report results and user interaction control functions; The FPGA programmable gate array ZYNQ subsystem 2 is respectively connected to the FPGA programmable logic Virtex subsystem 1, the power supply module 5, and the clock module 6; The multi-channel high-speed video signal acquisition subsystem 3 is respectively connected to the analog video signal input module 4, the power supply module 5, and the clock module 6; The power supply module 5 is respectively connected to the FPGA programmable gate array Virtex subsystem 1, the FPGA programmable gate array ZYNQ subsystem 2, and the multi-channel high-speed video signal acquisition subsystem 3 to meet the power supply voltage and current requirements of each subsystem circuit; The clock module 6 is respectively connected to the FPGA programmable gate array Virtex subsystem 1, the FPGA programmable gate array ZYNQ subsystem 2, and the multi-channel high-speed video signal acquisition subsystem 3 to meet the circuit clock requirements of each subsystem.

[0028] Refer to Figure 2 , the FPGA programmable logic Virtex subsystem 1 includes a Virtex chip 11, a 20GB 16-bit DDR4 memory 12, a first Flash module 13, a first FMC+ interface 14, a QSFP+ interface 15, an RGB video input / output module 16, and an FPD-LINK video input / output module 17; The Virtex chip 11 is respectively connected to the 20GB 16-bit DDR4 memory 12, the first Flash module 13, the first FMC+ interface 14, the QSFP+ interface 15, the RGB video input / output module 16, and the FPD-LINK video input / output module 17; The Virtex chip 11 is selected from the XILINX Virtex Ultrascale+ series XCVU9P-2FLGA2577I chip to implement analog video signal quality analysis and digital video protocol parsing. This chip has rich resources and can support up to 120 GTY transceivers; The 20GB 16-bit DDR4 memory 12 realizes the storage of high-bandwidth and large-capacity analog video signals and digital video signals; The first Flash module 13 realizes the storage of configuration data, and the Virtex chip 11 automatically loads user logic after power-on; The first FMC+ interface 14 is connected to the second FMC+ interface 38 in the multi-channel high-speed video signal acquisition subsystem 3 to realize the transmission of the analog video signal collected by the ADC in the multi-channel high-speed video signal acquisition subsystem 3; The QSFP+ interface 15 is connected to the PC 7 to realize the output of the analog video signal quality analysis and digital video protocol parsing results and the transmission of user interaction control instructions; The RGB video input / output module 16 and the FPD-LINK video input / output module 17 respectively realize the reception, encoding / decoding, and output of RGB video and FPD-LINK video, and perform self-loop detection of standard test video data.

[0029] Refer to Figure 3 , the FPGA programmable gate array ZYNQ subsystem 2 includes a ZYNQ chip 21, a 16GB 64-bit DDR4 memory 22, an 8GB 64-bit DDR4 memory 23, a second Flash module 24, an SD card module 25, a USB-UART module 26, an SFP+ interface 27, an HDMI video input / output module 28, an LVDS video input interface 29, an LVDS video output interface 210, and a DisplayPort video output interface 211; The ZYNQ chip 21 is respectively connected to the Virtex chip 11, the 16GB 64-bit DDR4 memory 22, the 8GB 64-bit DDR4 memory 23, the second Flash module 24, the SD card module 25, the USB-UART module 26, the SFP+ interface 27, the HDMI video input / output module 28, the LVDS video input interface 29, the LVDS video output interface 210, and the DisplayPort video output interface 211; The ZYNQ chip 21 selects the XILINX Ultrascale+ XCZU7EV-2FFVC1156I chip to implement the parsing of HDMI and LVDS digital video protocols and transmit the parsing results to the Virtex chip 11; The 16GB 64-bit DDR4 memory 22 stores the high-definition digital video signals processed by the PL side of the ZYNQ chip 21; The 8GB 64-bit DDR4 memory 23 stores the high-definition digital video signals processed by the PS side of the ZYNQ chip 21; The second Flash module 24 and the SD card module 25 store the configuration data, and the ZYNQ chip 21 automatically loads the user logic after power-on; The USB-UART module 26 converts the USB signal into a UART; The SFP+ interface 27 realizes the remote data transmission function; The HDMI video input / output module 28 receives, encodes / decodes, and outputs the HDMI video, and performs the self-loop detection of the standard test video data; The LVDS video input interface 29 receives the LVDS video; The LVDS video output interface 210 and the DisplayPort video output interface 211 output the standard LVDS and DisplayPort test video data.

[0030] Refer to Figure 4 , the multi-channel high-speed video signal acquisition subsystem 3 includes an LVDS analog video signal conditioning module 31, a TMDS analog video signal conditioning module 32, an FPD-LINK analog video signal conditioning module 33, an RGB analog video signal conditioning module 34, a DP analog video signal conditioning module 35, an analog signal selection module 36, an ADC module 37, a second FMC+ interface 38, a subsystem clock module 39, a subsystem power module 310, and a configuration module 311; The subsystem power module 310 is respectively connected to the LVDS analog video signal conditioning module 31, the TMDS analog video signal conditioning module 32, the FPD-LINK analog video signal conditioning module 33, the RGB analog video signal conditioning module 34, the DP analog video signal conditioning module 35, the analog signal selection module 36, the ADC module 37, the second FMC+ interface 38, the subsystem clock module 39, and the configuration module 311, and supplies power to each module respectively; The configuration module 311 is respectively connected to an LVDS analog video signal conditioning module 31, a TMDS analog video signal conditioning module 32, an FPD-LINK analog video signal conditioning module 33, an RGB analog video signal conditioning module 34, a DP analog video signal conditioning module 35, an analog signal selection module 36, an ADC module 37, a second FMC+ interface 38, and a subsystem clock module 39 to implement the chip SPI or IIC parameter configuration function for each module; The LVDS analog video signal conditioning module 31, the TMDS analog video signal conditioning module 32, the FPD-LINK analog video signal conditioning module 33, the RGB analog video signal conditioning module 34, and the DP analog video signal conditioning module 35 are connected to the analog signal selection module 36; the analog signal selection module 36 is connected to the ADC module 37; the ADC module 37 is connected to the second FMC+ interface 38; the second FMC+ interface 38 is connected to the first FMC+ interface 14; each analog video signal conditioning module conditions the input analog video signal to the voltage range that conforms to the ADC input analog signal, and the analog signal selection module 36 selects the analog video signal of one video protocol and inputs it to the ADC module 37; the ADC module 37 converts the analog video signal into a digital signal and outputs it to the FMC+ interface 38.

[0031] Refer to Figure 5 As shown in, the analog video signal input module 4 includes an LVDS analog video signal input interface 41, an HDMI analog video signal input interface 42, an FPD-LINK analog video signal input interface 43, an RGB analog video signal input interface 44, a DP analog video signal input interface 45, and an SMA high-speed interface group 46; The LVDS analog video signal input interface 41, the HDMI analog video signal input interface 42, the FPD-LINK analog video signal input interface 43, the RGB analog video signal input interface 44, and the DP analog video signal input interface 45 are respectively connected to the SMA high-speed interface group 46; the SMA high-speed interface group 46 respectively transfers the input analog video signal to the LVDS analog video signal conditioning module 31, the TMDS analog video signal conditioning module 32, the FPD-LINK analog video signal conditioning module 33, the RGB analog video signal conditioning module 34, and the DP analog video signal conditioning module 35.

[0032] Refer to Figure 6 As shown in, the RGB video input / output module 16 includes a first level conversion chip 161, a second level conversion chip 162, an RGB digital video signal input AD9882 chip 163, an RGB digital video signal output ADV7125 chip 164, an RGB digital video signal input interface 165, and an RGB digital video signal output interface 166; The RGB digital video signal input interface 165 and the RGB digital video signal output interface 166 are respectively connected to the RGB digital video signal input AD9882 chip 163 and the RGB digital video signal output ADV7125 chip 164; the RGB digital video signal input AD9882 chip 163 and the RGB digital video signal output ADV7125 chip 164 are respectively connected to the first level conversion chip 161 and the second level conversion chip 162; the first level conversion chip 161 and the second level conversion chip 162 are connected to the Virtex chip 11; the RGB digital video signal input AD9882 chip 163 is configured to convert the input RGB digital video signal with a 3.3V level standard into an RGB888 24-bit parallel video signal; the first level conversion chip 161 converts the data with a 3.3V level standard into data with a 1.8V level standard and inputs it to the Virtex chip 11; the Virtex chip 11 outputs an RGB888 24-bit parallel video signal with a 1.8V level standard, which is converted into a 3.3V level standard through the second level conversion chip 162; the RGB digital video signal output ADV7125 chip is configured to convert the parallel video data with a 3.3V level standard into an RGB digital video signal and output it through the RGB digital video signal output interface 166.

[0033] Refer to Figure 7 As shown, the FPD-LINK video input / output module 17 includes an FPD-LINK digital video signal input deserialization chip DS92LV2422 171, an FPD-LINK digital video signal output deserialization chip DS92LV2422 172, an FPD-LINK digital video signal input interface 173, and an FPD-LINK digital video signal output interface 174; The FPD-LINK digital video signal input DS92LV2422 chip 171 and the FPD-LINK digital video signal output DS92LV2422 chip 172 are respectively connected to the FPD-LINK digital video signal input interface 173 and the FPD-LINK digital video signal output interface 174; the FPD-LINK digital video signal input DS92LV2422 chip 171 converts the LVDS differential signal into parallel RGB digital video data and inputs it to the Virtex chip 11; the FPD-LINK digital video signal output DS92LV2422 chip 172 converts the parallel RGB digital video data into an LVDS differential signal and outputs it to the FPD-LINK digital video signal output interface 174.

[0034] Refer to Figure 8, the HDMI video input / output module 28 includes a 2K HDMI digital video signal input SiI7171 chip 281, a 2K HDMI digital video signal output SiI7170 chip 282, a first 4K HDMI digital video signal transceiver GSV2011 chip 283, a second 4K HDMI digital video signal transceiver GSV2011 chip 284, a 2K HDMI digital video signal input interface 285, a 2K HDMI digital video signal output interface 286, a 4K HDMI digital video signal input interface 287, and a 4K HDMI digital video signal output interface 288; The 2K HDMI digital video signal input interface 285, the 2K HDMI digital video signal output interface 286, the 4K HDMI digital video signal input interface 287, and the 4K HDMI digital video signal output interface 288 are respectively connected to the 2K HDMI digital video signal input SiI7171 chip 281, the 2K HDMI digital video signal output SiI7170 chip 282, the first 4K HDMI digital video signal transceiver GSV2011 chip 283, and the second 4K HDMI digital video signal transceiver GSV2011 chip 284; the 2K HDMI digital video signal input SiI7171 chip 281 converts 2K HDMI digital video data into parallel RGB digital video data and inputs it to the Virtex chip 11; the 2K HDMI digital video signal output SiI7170 chip 282 converts the parallel RGB digital video data into 2K HDMI digital video data and outputs it to the 2K HDMI digital video signal output interface 286; the first 4K HDMI digital video signal transceiver GSV2011 chip 283 converts 4K HDMI digital video data into parallel RGB digital video data and inputs it to the Virtex chip 11; the second 4K HDMI digital video signal transceiver GSV2011 chip 284 converts the parallel RGB digital video data into 4K HDMI digital video data and outputs it to the 4K HDMI digital video signal output interface 288. Embodiment

[0035] The module selection for this embodiment is as follows. The Virtex chip 11 in the Virtex subsystem 1 of the FPGA programmable gate array can be implemented using the Virtex Ultrascale+ series chips of Xilinx, which are rich in hardware resources, including multiple high-speed GTY transceivers and support the high-bandwidth requirements of multiple video protocols. The ZYNQ chip 21 in the ZYNQ subsystem of the FPGA programmable gate array can be implemented using the ZYNQ Ultrascale+ series chips of Xilinx, which have high processing performance and strong flexibility and support the optimal allocation of complex video protocol parsing tasks between the PL side and the PS side. The ADC module 37 in the multi-channel high-speed video signal acquisition subsystem 3 can be implemented using the radio frequency sampling gigabit sampling analog-to-digital converter ADC12DJ5200RF chip of TI, which can directly sample input frequencies from DC to above 10 GHz and support an available input frequency range of up to 10 GHz. The power supply module 5 can be implemented using the DC-DC and LDO power supply chips of TI to achieve the required working power levels and currents for each module. The clock module 6 can be implemented using the clock management chip of TI to achieve the required working clock. The PC 7 uses a multi-protocol video standardization test and automated report generation software program developed in C language on the PC.

[0036] Refer to Figure 9 , the present invention can constitute a multi-protocol video signal quality analyzer device. Using a shorting cap to select the Flash firmware or SD card firmware mode, when the device is powered on, the Virtex chip 11 reads the compiled code from the first Flash module, and the ZYNQ chip 21 reads the compiled code from the second Flash module 24 or the SD card module 25 according to the selected mode, and the system starts to work.

[0037] The specific process of the present invention for detecting analog video signals is as follows: The LVDS analog video signal input interface 41, HDMI analog video signal input interface 42, FPD-LINK analog video signal input interface 43, RGB analog video signal input interface 44, and DP analog video signal input interface 45 in the analog video signal input module 4 receive analog video signals, which are transferred to the SMA high-speed interface group 46 by a patch cable. After the multi-channel high-speed video signal acquisition subsystem 3 performs analog video signal conditioning, one of the analog video signals is selected and input to the ADC. After analog-to-digital conversion, the digital signal is input to the Virtex chip 11 through the FMC+ interface. The Virtex chip 11 preprocesses the data, sends it to the 20GB 16bits DDR4 memory 12 for caching, and then performs signal quality analysis on the data. The signal quality analysis result is transmitted to the PC 7 through the QSFP+ interface 15.

[0038] The specific process of the present invention for detecting digital video signals is as follows: RGB digital video signals, 2K HDMI digital video signals, 4K HDMI digital video signals, and FPD-LINK digital video signals are respectively input through the RGB digital video signal input interface 165, 2K HDMI digital video signal input interface 285, 4K HDMI digital video signal input interface 287, and FPD-LINK digital video signal input interface 173, and are respectively converted into parallel RGB digital video data by the RGB digital video signal input AD9882 chip 163, 2K HDMI digital video signal input SiI7171 chip 281, the first 4K HDMI digital video signal transceiver GSV2011 chip 283, and the FPD-LINK digital video signal input deserializer DS92LV2422 chip 171, and then input to the ZYNQ chip 21; the LVDS video signal is received through the LVDS video input interface 29 and input to the ZYNQ chip 21; the ZYNQ chip 21 preprocesses the 2K HDMI, 4K HDMI, and LVDS protocol parallel RGB digital video signals, extracts image data and timing information, sends them to the 16GB 64bits DDR4 memory 22 for caching, performs protocol parsing by the ZYNQ chip 21, and transmits the protocol parsing result to the Virtex chip 11, and then transmits it to the PC 7 through the QSFP+ interface 15; the Virtex chip 11 preprocesses the RGB and FPD-LINK protocol parallel RGB digital video signals, extracts image data and timing information, sends them to the 20GB 16bits DDR4 memory 12 for caching, and after performing protocol parsing, transmits the protocol parsing result to the PC 7 through the QSFP+ interface 15.

Claims

1. A multi-protocol video signal quality analyzer device, characterized in that: It includes an FPGA programmable gate array Virtex subsystem (1), an FPGA programmable gate array ZYNQ subsystem (2), a multi-channel high-speed video signal acquisition subsystem (3), an analog video signal input module (4), a power module (5), a clock module (6) and a PC (7); The FPGA programmable logic Virtex subsystem (1) is respectively connected to the FPGA programmable gate array ZYNQ subsystem (2), the multi-channel high-speed video signal acquisition subsystem (3), the power module (5), the clock module (6) and the PC (7); the FPGA programmable logic Virtex subsystem (1) is connected to the FPGA programmable gate array ZYNQ subsystem (2) via a GTYSerdes that can support up to 32.75 Gbps and a LVDS data line that can support up to 1.25 Gbps, thereby realizing high-bandwidth high-definition video data transmission; the FPGA programmable logic Virtex subsystem (1) is connected to the multi-channel high-speed video signal acquisition subsystem (3) via a first FMC+ interface (14) of the FPGA programmable logic Virtex subsystem (1) and a second FMC+ interface (38) of the multi-channel high-speed video signal acquisition subsystem (3), thereby supporting 80 channels of GTYSerdes. The digital signal data and control signal after analog-to-digital conversion are transmitted; the FPGA programmable logic Virtex subsystem (1) is connected to the power supply module (5) to meet the power supply requirements of multiple power supply voltages and currents; the FPGA programmable logic Virtex subsystem (1) is connected to the clock module (6) to meet the multiple clock requirements of each interface; the FPGA programmable logic Virtex subsystem (1) is connected to the PC (7) to realize the output of the video protocol detection report result and the user interaction control function; The FPGA programmable logic Virtex subsystem (1) comprises a Virtex chip (11), a 20GB 16-bit DDR4 memory (12), a first Flash module (13), a first FMC+ interface (14), a QSFP+ interface (15), an RGB video input and output module (16), and an FPD-LINK video input and output module (17); The Virtex chip (11) is respectively connected to the 20GB 16bits DDR4 memory (12), the first Flash module (13), the first FMC+ interface (14), the QSFP+ interface (15), the RGB video input and output module (16) and the FPD-LINK video input and output module (17); the Virtex chip (11) implements analog video signal quality analysis and digital video protocol analysis; the 20GB The 16-bit DDR4 memory (12) realizes the storage of high-bandwidth and large-capacity analog video signals and digital video signals; the first Flash module (13) realizes the storage of configuration data, and the Virtex chip (11) automatically loads the user logic after power-on; the first FMC+ interface (14) is connected to the second FMC+ interface (38) in the multi-channel high-speed video signal acquisition subsystem (3) to realize the transmission of the analog video signal acquired by the ADC in the multi-channel high-speed video signal acquisition subsystem (3); the QSFP+ interface (15) is connected to the PC (7) to realize the output of analog video signal quality analysis and digital video protocol analysis results and the transmission of user interactive control instructions; the RGB video input and output module (16) and the FPD-LINK video input and output module (17) respectively realize the reception, encoding, decoding and output of RGB video and FPD-LINK video, and perform standard test video data self-loop detection; The FPGA programmable gate array ZYNQ subsystem (2) is respectively connected to the FPGA programmable logic Virtex subsystem (1), the power module (5), and the clock module (6); the FPGA programmable gate array ZYNQ subsystem (2) comprises a ZYNQ chip (21), a 16GB 64bits DDR4 memory (22), an 8GB 64bits DDR4 memory (23), a second Flash module (24), an SD card module (25), a USB-UART module (26), an SFP+ interface (27), an HDMI video input and output module (28), an LVDS video input interface (29), an LVDS video output interface (210), and a DisplayPort video output interface (211); The ZYNQ chip (21) is respectively connected to the Virtex chip (11), the 16GB 64bits DDR4 memory (22), the 8GB 64bits DDR4 memory (23), the second Flash module (24), the SD card module (25), the USB-UART module (26), the SFP+ interface (27), the HDMI video input and output module (28), the LVDS video input interface (29), the LVDS video output interface (210) and the DisplayPort video output interface (211); the ZYNQ chip (21) implements HDMI and LVDS digital video protocol parsing and transmits the parsing results to the Virtex chip (11); the 16GB 64bits DDR4 memory (22) implements the storage of high-definition digital video signals processed by the PL end of the ZYNQ chip (21); the 8GB 64bits DDR4 memory (23) implements the storage of high-definition digital video signals processed by the PL end of the ZYNQ chip (21); The DDR4 memory (23) realizes the storage of the high-definition digital video signal processed by the PS end of the ZYNQ chip (21); the second Flash module (24) and the SD card module (25) realize the storage of configuration data, and the ZYNQ chip (21) automatically loads the user logic after power-on; the USB-UART module (26) realizes the conversion of USB signals into UART; the SFP+ interface (27) realizes the remote data transmission function; the HDMI video input and output module (28) realizes the reception, encoding, decoding and output of HDMI video, and performs self-loop detection of standard test video data; the LVDS video input interface (29) realizes the reception of LVDS video; the LVDS video output interface (210) and the DisplayPort video output interface (211) output standard LVDS and DisplayPort test video data; The multi-channel high-speed video signal acquisition subsystem (3) is respectively connected to the analog video signal input module (4), the power module (5) and the clock module (6); the multi-channel high-speed video signal acquisition subsystem (3) comprises an LVDS analog video signal conditioning module (31), a TMDS analog video signal conditioning module (32), an FPD-LINK analog video signal conditioning module (33), an RGB analog video signal conditioning module (34), a DP analog video signal conditioning module (35), an analog signal selection module (36), an ADC module (37), a second FMC+ interface (38), a subsystem clock module (39), a subsystem power module (310) and a configuration module (311); The subsystem power supply module (310) is respectively connected to the LVDS analog video signal conditioning module (31), the TMDS analog video signal conditioning module (32), the FPD-LINK analog video signal conditioning module (33), the RGB analog video signal conditioning module (34), the DP analog video signal conditioning module (35), the analog signal selection module (36), the ADC module (37), the second FMC+ interface (38), the subsystem clock module (39) and the configuration module (311), and supplies power to each module respectively; The configuration module (311) is respectively connected to the LVDS analog video signal conditioning module (31), the TMDS analog video signal conditioning module (32), the FPD-LINK analog video signal conditioning module (33), the RGB analog video signal conditioning module (34), the DP analog video signal conditioning module (35), the analog signal selection module (36), the ADC module (37), the second FMC+ interface (38), and the subsystem clock module (39), so as to realize the chip SPI or IIC parameter configuration function of each module; The LVDS analog video signal conditioning module (31), the TMDS analog video signal conditioning module (32), the FPD-LINK analog video signal conditioning module (33), the RGB analog video signal conditioning module (34), and the DP analog video signal conditioning module (35) are respectively connected to the analog signal selection module (36); the analog signal selection module (36) is connected to the ADC module (37); the ADC module (37) is connected to the second FMC+ interface (38); the second FMC+ interface (38) is connected to the first FMC+ interface (14); each analog video signal conditioning module conditions the input analog video signal to a voltage range that meets the ADC input analog signal; the analog signal selection module (36) selects an analog video signal of a video protocol and inputs it to the ADC module (37); the ADC module (37) converts the analog video signal into a digital signal and outputs it to the FMC+ interface (38); The analog video signal input module (4) comprises an LVDS analog video signal input interface (41), an HDMI analog video signal input interface (42), an FPD-LINK analog video signal input interface (43), an RGB analog video signal input interface (44), a DP analog video signal input interface (45) and an SMA high-speed interface group (46); The LVDS analog video signal input interface (41), the HDMI analog video signal input interface (42), the FPD-LINK analog video signal input interface (43), the RGB analog video signal input interface (44), and the DP analog video signal input interface (45) are respectively connected to the SMA high-speed interface group (46); the SMA high-speed interface group (46) transfers the input analog video signal to the LVDS analog video signal conditioning module (31), the TMDS analog video signal conditioning module (32), the FPD-LINK analog video signal conditioning module (33), the RGB analog video signal conditioning module (34), and the DP analog video signal conditioning module (35); The power supply module (5) is respectively connected to the FPGA programmable gate array Virtex subsystem (1), the FPGA programmable gate array ZYNQ subsystem (2) and the multi-channel high-speed video signal acquisition subsystem (3) to meet the power supply voltage and current requirements of the circuits of each subsystem; The clock module (6) is respectively connected to the FPGA programmable gate array Virtex subsystem (1), the FPGA programmable gate array ZYNQ subsystem (2) and the multi-channel high-speed video signal acquisition subsystem (3) to meet the circuit clock requirements of each subsystem.

2. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The RGB video input and output module (16) comprises a first level conversion chip (161), a second level conversion chip (162), an RGB digital video signal input AD9882 chip (163), an RGB digital video signal output ADV7125 chip (164), an RGB digital video signal input interface (165) and an RGB digital video signal output interface (166); The RGB digital video signal input interface (165) and the RGB digital video signal output interface (166) are respectively connected to the RGB digital video signal input AD9882 chip (163) and the RGB digital video signal output ADV7125 chip (164); the RGB digital video signal input AD9882 chip (163) and the RGB digital video signal output ADV7125 chip (164) are respectively connected to the first level conversion chip (161) and the second level conversion chip (162); the first level conversion chip (161) and the second level conversion chip (162) are respectively connected to the Virtex chip (11); the RGB digital video signal input AD9882 chip (163) converts the input 3.3V level standard RGB digital video signal into an RGB888 24-bit parallel video signal; the first level conversion chip (161) converts the 3.3V level standard data into 1.8V level standard data and inputs it into the Virtex chip (11); the Virtex chip (11) outputs the 1.8V level standard RGB888 The 24-bit parallel video signal is converted to a 3.3V level standard through a second level conversion chip (162); the RGB digital video signal output ADV7125 chip converts the parallel video data of the 3.3V level standard into an RGB digital video signal, which is output through an RGB digital video signal output interface (166).

3. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The FPD-LINK video input and output module (17) comprises an FPD-LINK digital video signal input deserializer DS92LV2422 chip (171), an FPD-LINK digital video signal output deserializer DS92LV2422 chip (172), an FPD-LINK digital video signal input interface (173) and an FPD-LINK digital video signal output interface (174); The FPD-LINK digital video signal input DS92LV2422 chip (171) and the FPD-LINK digital video signal output DS92LV2422 chip (172) are respectively connected to the FPD-LINK digital video signal input interface (173) and the FPD-LINK digital video signal output interface (174); the FPD-LINK digital video signal input DS92LV2422 chip (171) converts the LVDS differential signal into parallel RGB digital video data and inputs it into the Virtex chip (11); the FPD-LINK digital video signal output DS92LV2422 chip (172) converts the parallel RGB digital video data into LVDS differential signals and outputs it to the FPD-LINK digital video signal output interface (174).

4. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The HDMI video input and output module (28) comprises a 2K HDMI digital video signal input SiI7171 chip (281), a 2K HDMI digital video signal output SiI7170 ​​chip (282), a first 4K HDMI digital video signal transceiver GSV2011 chip (283), a second 4K HDMI digital video signal transceiver GSV2011 chip (284), a 2K HDMI digital video signal input interface (285), a 2K HDMI digital video signal output interface (286), a 4K HDMI digital video signal input interface (287) and a 4K HDMI digital video signal output interface (288); The 2K HDMI digital video signal input interface (285), the 2K HDMI digital video signal output interface (286), the 4KHDMI digital video signal input interface (287) and the 4K HDMI digital video signal output interface (288) are respectively connected to the 2K HDMI digital video signal input SiI7171 chip (281), the 2K HDMI digital video signal output SiI7170 ​​chip (282), the first 4K HDMI digital video signal transceiver GSV2011 chip (283) and the second 4K HDMI digital video signal transceiver GSV2011 chip (284); the 2K HDMI digital video signal input SiI7171 chip (281) converts the 2K HDMI digital video data into parallel RGB digital video data and inputs it into the Virtex chip (11); the 2K HDMI digital video signal output SiI7170 ​​chip (282) converts the parallel RGB digital video data into 2K HDMI digital video data and outputs it into the 2K HDMI digital video signal output interface (286); the first 4K The HDMI digital video signal transceiver GSV2011 chip (283) converts the 4K HDMI digital video data into parallel RGB digital video data and inputs it into the Virtex chip (11); the second 4K HDMI digital video signal transceiver GSV2011 chip (284) is connected to convert the parallel RGB digital video data into 4K HDMI digital video data and output it to the 4K HDMI digital video signal output interface (288).

5. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The ADC module (37) uses a radio frequency sampling giga-sampling analog-to-digital converter ADC12DJ5200RF chip.

6. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The first FMC+ interface (14) and the second FMC+ interface (38) respectively use ASP-184330-01 and ASP-184329-01 connectors, and the two are tightly connected to each other.

7. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: A multi-protocol video standardization test and automated report generation software program was developed using C language on a PC (7).

8. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: The RGB video input and output module (16), the FPD-LINK video input and output module (17), the HDMI video input and output module (28), the LVDS video input interface (29), the LVDS video output interface (210) and the DisplayPort video output interface (211) support 2K@60HZ resolution and also support input and output of a variety of non-standard resolutions, including 1680x1050@60Hz and 1440x1050@60Hz resolutions.

9. A multi-protocol video signal quality analyzer device according to claim 1, characterized in that: A multi-protocol standard video self-loop test is performed by outputting a standard video signal through the RGB video input and output module (16), the FPD-LINK video input and output module (17), the HDMI video input and output module (28), the LVDS video output interface (210) and the DisplayPort video output interface (211).

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