SiC UMOSFET device with stacked gate dielectric layer and preparation method of SiC UMOSFET device
By adopting a stacked gate dielectric layer structure in SiC UMOSFET devices and using HfO2 and SiO2 materials with high dielectric constants, the problem of insufficient voltage withstandability at the trench corners is solved, and higher voltage withstandability and reliability are achieved.
Patent Information
- Application Number
- CN202510293641.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2025-06-13
AI Technical Summary
The local high electric field of the existing SiC UMOSFET devices at the bottom corner of the trench causes the gate oxygen dielectric layer to be easily broken down, reducing the device's voltage resistance.
The structure of a stacked gate dielectric layer is adopted, wherein the second gate dielectric layer is filled in the U-shaped trench, is made of SiO2 material, and the first gate dielectric layer is stacked thereon using the High-κ material HfO2.
Through the stacking of HfO2 and SiO2 with high dielectric constant, the electric field strength can be effectively shared, the electric field stress in the gate dielectric layer is reduced, the device withstand voltage capability is improved, and the gate leakage current is suppressed, thereby improving the device reliability.
Smart Images
Figure CN120152336A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of transistors, and in particular to a SiC UMOSFET device with a stacked gate dielectric layer and a preparation method thereof. Background Art
[0002] Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a power device based on Silicon Carbide (SiC) material. Compared with traditional silicon (Si)-based MOSFETs, SiC MOSFETs have higher breakdown electric field strength, higher thermal conductivity, and wider bandgap, making them perform excellently in high-voltage, high-temperature, and high-frequency applications. SiC MOSFETs are currently widely used in new energy vehicles, industrial motor drives, and power electronics and other fields, and the market scale increases year by year.
[0003] U-shaped trench MOSFET (UMOSFET) is a common SiC MOSFET structure, which is characterized by etching a U-shaped trench on the SiC substrate and forming a gate, a gate dielectric layer, and a source in the trench. The main advantage of the UMOSFET structure lies in its lower on-resistance (R ds,on ) and higher switching speed, which benefits from the fact that the trench structure can effectively shorten the carrier transport path. However, due to the current concentration effect at the bottom corner of the trench, a local high electric field is introduced, making the gate oxide dielectric layer easily breakdown at the corner, reducing the breakdown voltage performance of the device. Summary of the Invention
[0004] Aiming at the deficiencies of the prior art, the present invention provides a SiC UMOSFET device with a stacked gate dielectric layer and a preparation method thereof. The present invention can effectively improve the breakdown voltage of the SiC UMOSFET device, suppress the gate leakage current, and improve the reliability of the SiC UMOSFET.
[0005] The technical solution of the present invention is: a SiC UMOSFET device with a stacked gate dielectric layer, including an N+ substrate region, an N- drift region, a P-well region, a P+ region, an N+ region, and a gate dielectric layer; the N- drift region is disposed above the N+ substrate region, and a P-well region is disposed on the N- drift region; corresponding P+ region and N+ region are disposed on the P-well region;
[0006] The middle parts of the N+ region and the P-well region are also etched with U-shaped grooves, and the U-shaped grooves penetrate downward through the N+ region and the P-well region and extend into the N-drift region; the U-shaped grooves are filled with a gate dielectric layer stacked by two oxides of different materials.
[0007] An electrode assembly is also provided on the N+ substrate region, the P+ region, the N+ region, and the gate dielectric layer.
[0008] Preferably, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer. The second gate dielectric layer is filled in the U-shaped groove and contacts the N+ region, the P-well region, and the N-drift region, and the first gate dielectric layer is provided on the second gate dielectric layer.
[0009] Preferably, the electrode assembly includes a metal drain provided at the bottom of the N+ substrate region, a metal source provided at the upper ends of the P+ region and the N+ region, and a gate electrode PolySi region provided on the first gate dielectric layer.
[0010] Preferably, the first gate dielectric layer is made of the High-κ material HfO 2 and the second gate dielectric layer is made of SiO 2 material.
[0011] Preferably, the doping types of the N+ substrate region, the N-drift region, and the N+ region are N-type doping, and the doping types of the P-well region and the P+ region are P-type doping.
[0012] Preferably, the materials of the N+ substrate region, the N-drift region, the P-well region, the P+ region, and the N+ region are all 4H-SiC.
[0013] Preferably, the present invention provides a method for manufacturing a SiC UMOSFET device with a stacked gate dielectric layer, including the following steps:
[0014] S1), Select a substrate and form an N-drift region on the substrate by epitaxial growth;
[0015] S2), Perform aluminum (Al) ion implantation on the surface of the N-drift region to form a P-well region;
[0016] S3), Perform nitrogen (N) ion implantation on the surface of the N-drift region to form the N+ region;
[0017] S4), Perform aluminum (Al) ion implantation on the surface of the N-drift region to form the P+ region;
[0018] S5), Use inductively coupled plasma etching technology to etch part of the N-drift region to form a U-shaped groove;
[0019] S6), deposit a thin layer of Si in the U-shaped groove, and then form SiO 2 oxide layer through thermal oxidation as the second gate dielectric layer, and deposit HfO 2 on the second gate dielectric layer to form the first gate dielectric layer stacked on the second gate dielectric layer;
[0020] S7), deposit PolySi on the first gate dielectric layer to prepare the gate electrode PolySi region, form a metal drain on the lower surface of the N+ substrate region, and form a metal source on the P+ region and the N+ region.
[0021] The beneficial effects of the present invention are as follows:
[0022] 1. The gate dielectric layer of the present invention is stacked by HfO 2 +SiO 2 , and the dielectric constant is about 25, which is much higher than the dielectric constant of the traditional SiO 2 (~3.9). The high dielectric constant allows a thicker physical layer to be used under the same equivalent oxide thickness (EOT), and can also effectively share the electric field intensity, reduce the electric field stress in the gate dielectric layer, and improve the breakdown voltage of the device; HfO 2 has good thermal stability at high temperatures and can withstand the higher temperatures during the operation of SiC devices;
[0023] 2. The stacked gate dielectric layer of the present invention can effectively suppress the gate leakage current, and at the same time improve the reliability and breakdown voltage performance of the device. The thin layer of SiO 2 in the stacked gate dielectric layer can increase its barrier height, inhibit the carriers from passing through the barrier, and reduce the gate leakage current;
[0024] 3. The thin layer of SiO 2 of the present invention is formed by first growing a thin layer of Si and then generating a thin layer of SiO 2 through thermal oxidation, which can improve the interface characteristics between SiC and SiO 2 , SiO 2 and HfO 2 , reduce the interface state density, and further improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a schematic structural diagram of the SiC UMOSFET device of the present invention;
[0026] In the figure, 1 - N+ substrate region; 2 - N- drift region; 3 - P-well region; 4 - P+ region; 5 - N+ region; 6 - second gate dielectric layer; 7 - first gate dielectric layer; 8 - metal source; 9 - gate electrode PolySi region; 10 - metal drain. DETAILED DESCRIPTION OF THE INVENTION
[0027] The following further describes the specific implementation manners of the present invention in conjunction with the accompanying drawings:
[0028] Embodiment 1
[0029] As Figure 1 shown, this embodiment provides a SiC UMOSFET device with a stacked gate dielectric layer. In this embodiment, the SiC UMOSFET device presents a symmetric structure. It includes an N+ substrate region 1, an N- drift region 2, a P-well region 3, a P+ region 4, an N+ region 5, and a gate dielectric layer; the N- drift region 2 is disposed above the N+ substrate region 1, and a P-well region 3 is provided on the N- drift region 2; corresponding P+ region 4 and N+ region 5 are provided on the P-well region 3;
[0030] A U-shaped trench is also etched in the middle of the N+ region 5 and the P-well region 3. The U-shaped trench penetrates downward through the N+ region 5 and the P-well region 3 and extends into the N- drift region 2; the U-shaped trench is filled with a gate dielectric layer stacked by two oxides of different materials.
[0031] An electrode assembly is further provided on the N+ substrate region 1, the P+ region 4, the N+ region 5, and the gate dielectric layer.
[0032] In this embodiment, the device is symmetric with respect to the U-shaped trench, and the P+ region 4, the N+ region 5, and the P-well region 3 are symmetrically arranged on both sides of the U-shaped trench respectively.
[0033] Preferably in this embodiment, the gate dielectric layer includes a first gate dielectric layer 6 and a second gate dielectric layer 7. The second gate dielectric layer 7 is filled in the U-shaped trench and contacts the N+ region 4, the P-well region 3, and the N- drift region 5, and a first gate dielectric layer 6 is provided on the second gate dielectric layer 7.
[0034] Preferably in this embodiment, the electrode assembly includes a metal drain 10 disposed at the bottom of the N+ substrate region 1, a metal source 8 disposed at the upper ends of the P+ region 4 and the N+ region 5, and a gate electrode PolySi region 9 disposed on the first gate dielectric layer 7. In this embodiment, the metal source 8 is in ohmic contact with the P+ region 4, and the short circuit of the P+ region 4 and the metal source 8 inhibits the turn-on of the parasitic triode formed by the N+ region 5, the P-well region 3, and the N- drift region 2, further improving the device performance.
[0035] In this embodiment, the depth of the U-shaped groove is greater than the sum of the thicknesses of the N+ region 5 and the P-well region 3. This is because the conductive inversion layer of the SiC UMOSFET device is formed on the side of the P-well region 3 close to the inner gate electrode PolySi region 9 of the U-shaped groove. Due to the effect of the gate voltage, the positive gate voltage attracts electrons to the semiconductor surface, that is, a conductive inversion layer composed of electrons is formed on the side of the P-well region 3 close to the inner gate electrode PolySi region 9 of the groove. Therefore, the gate needs to cover the channel of the P-well region 3.
[0036] Preferably, in this embodiment, the first gate dielectric layer 7 is made of the High-κ material HfO 2 and the second gate dielectric layer 6 is made of SiO 2 material.
[0037] Preferably, in this embodiment, the doping types of the N+ substrate region 1, the N-drift region 2, and the N+ region 5 are N-type doping, and the doping types of the P-well region 3 and the P+ region 4 are P-type doping.
[0038] Preferably, in this embodiment, the materials of the N+ substrate region 1, the N-drift region 2, the P-well region 3, the P+ region 4, and the N+ region 5 are all 4H-SiC.
[0039] Preferably, in this embodiment, the thickness of the P+ region 4 is less than the thickness of the P-well region 3; the thickness of the P-well region 3 is less than the thickness of the gate electrode PolySi region 9.
[0040] Preferably, in this embodiment, the width of the metal source electrode 8 is less than the sum of the widths of the P+ region 4 and the N+ region 5. In this embodiment, the metal source electrode 8 is disposed on the upper surfaces of a part of the P+ region 4 and a part of the N+ region 5.
[0041] Preferably, in this embodiment, the doping concentration of the N+ substrate region 1 is greater than the doping concentration of the N-drift region 2.
[0042] Preferably, in this embodiment, the doping concentration of the N+ region 5 is greater than the doping concentration of the N-drift region 2. The high doping concentration of the N+ region 5 can reduce the width of the Schottky barrier, promote the tunneling effect of carriers, further reduce the contact resistance, and thus significantly reduce the contact resistance between the metal source electrode 8 and the N+ region 5, which helps to form a good ohmic contact; in addition, the high doping concentration of the N+ region 5 can increase the carrier concentration, so that more carriers can be quickly injected into the conductive inversion layer in the on state, enhancing the current driving ability of the device and making the device more suitable for high-power and high-frequency applications.
[0043] Preferably in this embodiment, the doping concentration of the P+ region 4 is greater than that of the P-well region 3. The high doping concentration of the P+ region 4 can reduce the width of the Schottky barrier, promote the tunneling effect of carriers, further reduce the contact resistance, and thus significantly reduce the contact resistance between the metal source electrode 8 and the P+ region 4, which helps to form a good ohmic contact.
[0044] Preferably in this embodiment, the width of the P+ region 4 is smaller than that of the P-well region 3.
[0045] Preferably in this embodiment, the thickness of the N+ substrate region 1 is 1 - 50 μm; more preferably, the thickness of the N+ substrate region 1 is 3 μm, and the doping concentration is 1×10 19 cm -3 。
[0046] Preferably in this embodiment, the thickness of the N- drift region 2 is 5 - 65 μm; more preferably, the thickness of the N- drift region 2 is 6.2 μm, and the doping concentration is 2×10 15 cm -3 。
[0047] Preferably in this embodiment, the thickness of the P-well region 3 is 0.7 μm, the width is 1.85 μm, and the doping concentration is 2×10 17 cm -3 ;
[0048] Preferably in this embodiment, the thickness of the P+ region 4 is 0.5 - 2 μm; more preferably, the thickness of the P+ region 4 is 0.5 μm, the width is 1 μm, and the doping concentration is 2×10 18 cm -3 。
[0049] Preferably in this embodiment, the thickness of the N+ region 5 is 0.5 - 2 μm; more preferably, the thickness of the N+ region 5 is 0.5 μm, the width is 0.85 μm, and the doping concentration is 1×10 19 cm -3 。
[0050] Preferably in this embodiment, the thickness of the gate electrode PolySi region 9 is 0.5 - 3 μm; more preferably, the thickness of the gate electrode PolySi region 9 is 1.8 μm, and the width is 1.5 μm.
[0051] Preferably in this embodiment, the total thickness of the stacked gate dielectric layers around the gate electrode PolySi region 9 is 0.1 - 3 μm; wherein, the thickness of the first gate dielectric layer 7 is 0.5 μm, and the thickness of the second gate dielectric layer 6 is 2 nm.
[0052] Preferably in this embodiment, the metal materials of the metal source electrode 8 and the metal drain electrode 10 are one or more of titanium (Ti), nickel (Ni), or gold (Au).
[0053] Embodiment 2
[0054] This embodiment provides a preparation method for a stacked gate dielectric layer SiC UMOSFET device, including the following steps:
[0055] S1), select the N+ substrate region 1, where the N+ substrate region 1 is N+-doped 4H-SiC with a thickness of 3 μm and a doping concentration of 1×10 19 cm -3 , and perform RCA standard cleaning on the N+ substrate region 1; then epitaxially grow an N-drift region 2 with a thickness of 6.2 μm and a doping concentration of 2×10 15 cm -3 on the N+ substrate region 1.
[0056] S2), perform aluminum (Al) ion implantation on the surface of the N-drift region 2 to form a P-well region 3; specifically:
[0057] First, deposit a layer of SiO 2 oxide layer on the surface of the N-drift region 2, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, perform aluminum (Al) ion implantation on the N-drift region 2 with an implantation depth of 0.7 μm, a width of 1.85 μm, and a doping concentration of 2×10 17 cm -3 . After the implantation is completed, annealing is performed, and then the SiO 2 oxide layer is removed, and finally a P-well region 3 is formed on the upper surface of the N-drift region 2;
[0058] S3), perform nitrogen (N) ion implantation on the surface of the N-drift region 2 to form the N+ region 5; specifically:
[0059] First, deposit a layer of SiO 2 oxide layer on the surface of the N-drift region 2, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, perform nitrogen (N) ion implantation on the N-drift region 2 with an implantation depth of 0.5 μm, a width of 0.85 μm, and a doping concentration of 1×10 19 cm -3 . After the implantation is completed, annealing is performed, and then the SiO 2 oxide layer is removed, and finally an N+ region 5 is formed on the upper surface of the N-drift region 2;
[0060] S4), perform aluminum (Al) ion implantation on the surface of the N-drift region 2 to form the P+ region 4; specifically:
[0061] Deposit a layer of SiO 2 oxide layer on the surface of the N-drift region 2, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, perform aluminum (Al) ion implantation on the N-drift region 2. The implantation depth is 0.5 μm, the width is 1 μm, and the doping concentration is 2×10 18 cm -3 . After the implantation is completed, annealing is carried out, and then the SiO 2 oxide layer is removed, and finally the P+ region 4 is formed on the upper surface of the N-drift region 2;
[0062] S5), use inductively coupled plasma plasma etching technology to etch part of the N-drift region 2 to form a U-shaped groove; specifically:
[0063] Deposit a layer of SiO 2 oxide layer on the surface of the N-drift region 2, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, etch the middle region of the N-drift region 2 downward by 1.8 μm, and then remove the SiO 2 oxide layer to form a U-shaped groove;
[0064] S6), deposit a thin layer of Si in the U-shaped groove, and then form a SiO 2 oxide layer by thermal oxidation as the second gate dielectric layer 6, and deposit HfO 2 on the second gate dielectric layer 6 to form the first gate dielectric layer 7 stacked on the second gate dielectric layer 6; specifically:
[0065] Based on the U-shaped groove, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, expose the groove, then deposit a thin layer of Si in the groove, perform thermal oxidation to form a SiO 2 oxide layer, and then deposit a HfO 2 layer to form a stacked gate dielectric layer (the first gate dielectric layer 7 and the second gate dielectric layer 6);
[0066] S7), deposit PolySi on the first gate dielectric layer 7 to prepare the gate electrode PolySi region 9, specifically:
[0067] Based on the stacked gate dielectric layer, coat photoresist, cover a mask on the N-drift region 2, and after processes such as exposure, development, etching, and resist stripping, expose the stacked gate dielectric layer (the first gate dielectric layer 7 and the second gate dielectric layer 6), deposit PolySi in the groove of the stacked gate dielectric layer, and finally form the gate electrode PolySi region 9;
[0068] A metal drain 10 is formed on the lower surface of the N+ substrate region 1, and a metal source 8 is formed on the P+ region 4 and the N+ region 5.
[0069] In this embodiment, the surface of the device is cleaned by plasma cleaning. Subsequently, titanium (Ti) metal is deposited on the lower surface of the N+ substrate region 1. Ti reacts with SiC to form titanium carbide (TiC), improving the contact performance. At the same time, Ti serves as an adhesion layer to enhance the adhesion of the metal to SiC. Nickel (Ni) and gold (Au) are deposited in sequence, and a metal drain 10 is formed after high-temperature annealing. The contact between the metal drain 10 and the N+ substrate region 1 is an ohmic contact. Titanium (Ti), nickel (Ni), and gold (Au) are deposited in sequence on the upper surfaces of the P+ region 4 and the N+ region 5, and a metallized source 8 is formed after high-temperature annealing. The contact between the metal source 8 and the P+ region 4 and the N+ region 5 is an ohmic contact. Finally, a surface planarization process is performed to complete the process design and complete the preparation of the SiC UMOSFET device.
[0070] The above embodiments and descriptions in the specification only illustrate the principles and the best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the claimed invention.
Claims
1. A SiC UMOSFET device with a stacked gate dielectric layer, characterized in that: The invention comprises an N+ substrate region (1), an N-drift region (2), a P-well region (3), a P+ region (4), an N+ region (5), and a gate dielectric layer; the N-drift region (2) is arranged above the N+ substrate region (1), the P-well region (3) is arranged on the N-drift region (2); and the P-well region (3) is arranged with corresponding P+ region (4) and N+ region (5); A U-shaped groove is also etched in the middle of the N+ region (5) and the P-well region (3), and the U-shaped groove penetrates downwardly through the N+ region (5) and the P-well region (3) and extends into the N-drift region (2); two gate dielectric layers formed by stacking oxides of different materials are arranged in the U-shaped groove; Electrode components are also arranged on the N+ substrate region (1), the P+ region (4), the N+ region (5) and the gate dielectric layer.
2. A SiC UMOSFET device with stacked gate dielectric layers according to claim 1, characterized in that: The gate dielectric layer comprises a first gate dielectric layer (7) and a second gate dielectric layer (6), wherein the second gate dielectric layer (6) is filled in the U-shaped groove and is in contact with the N+ region (5), the P-well region (3) and the N-drift region (2), and the first gate dielectric layer (7) is arranged on the second gate dielectric layer (6).
3. The SiC UMOSFET device with stacked gate dielectric layers according to claim 2, characterized in that: The first gate dielectric layer (7) is made of High-κ material HfO2, and the second gate dielectric layer (6) is made of SiO2 material.
4. The SiC UMOSFET device with stacked gate dielectric layers according to claim 3, characterized in that: The thickness of the gate dielectric layer is 0.1-3 μm, wherein the thickness of the first gate dielectric layer (7) is 0.5 μm; and the thickness of the second gate dielectric layer (6) is 2 nm.
5. The SiC UMOSFET device with stacked gate dielectric layers according to claim 1, characterized in that: The electrode assembly comprises a metal drain (10) arranged at the bottom of an N+ substrate region (1), a metal source (8) arranged at the top of a P+ region (4) and an N+ region (5), and a gate electrode PolySi region (9) arranged on a first gate dielectric layer (7).
6. The SiC UMOSFET device with stacked gate dielectric layers according to claim 1, characterized in that: The doping types of the N+ substrate region (1), the N-drift region (2) and the N+ region (5) are N-type doping, and the doping types of the P-well region (3) and the P+ region (4) are P-type doping.
7. The SiC UMOSFET device with stacked gate dielectric layers according to claim 6, characterized in that: The doping concentration of the N+ substrate region (1) is greater than the doping concentration of the N-drift region (2); the doping concentration of the N+ region (5) is greater than the doping concentration of the N-drift region (2); and the doping concentration of the P+ region (4) is greater than the doping concentration of the P-well region (3).
8. The SiC UMOSFET device with stacked gate dielectric layers according to claim 6, characterized in that: The materials of the N+ substrate region (1), the N-drift region (2), the P-well region (3), the P+ region (4), and the N+ region (5) are all 4H-SiC.
9. The SiC UMOSFET device with stacked gate dielectric layers according to claim 1, characterized in that: The depth of the U-shaped groove is greater than the sum of the thicknesses of the N+ region (5) and the P-well region (3), and the conductive inversion layer of the SiC UMOSFET device is formed on the side of the P-well region (3) close to the gate electrode PolySi region (9) in the U-shaped groove.
10. A method for preparing a SiC UMOSFET device having a stacked gate dielectric layer according to any one of claims 1 to 9, characterized in that: The method comprises the following steps: S1), selecting an N+ substrate region (1), and forming an N-drift region (2) on the N+ substrate region (1) by epitaxial growth; S2), implanting aluminum (Al) ions on the surface of the N-drift region (2) to form a P-well region (3); S3), performing nitrogen (N) ion implantation on the surface of the N-drift region (2) to form the N+ region (5); S4), implanting aluminum (Al) ions on the surface of the N-drift region (2) to form the P+ region (4); S5), etching part of the N-drift region (2) using an inductively coupled plasma etching technique to form a U-shaped groove; S6), depositing a thin layer of Si in the U-shaped groove, and then forming a SiO2 oxide layer by thermal oxidation as a second gate dielectric layer (6), and depositing HfO2 on the second gate dielectric layer (6) to form a first gate dielectric layer (7) stacked on the second gate dielectric layer (6); S7), depositing PolySi on the first gate dielectric layer (7) to prepare a gate electrode PolySi region (9), forming a metal drain (10) on the lower surface of the N+ substrate region (1), and forming a metal source (8) on the P+ region (4) and the N+ region (5).