A recessed MIS structure transistor with a toothed p-GaN buried layer

Abstract

A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate, a nucleation layer, a first GaN buffer layer, a source-drain p-GaN buried layer, a second GaN buffer layer, a GaN layer, and an AlGaN barrier layer. A drain electrode and a source electrode are respectively provided on both sides of the AlGaN barrier layer, and a gate electrode trench is provided on the side of the AlGaN barrier layer near the drain electrode. Toothed protrusions and grooves matching the protrusions are distributed on the opposite side of the first and second GaN buffer layers. The toothed source-drain junction between the first and second GaN buffer layers... The buried p-GaN layer improves the electric field distribution between the gate and drain, the gate and source, and the source and drain of the device, reducing the average electric field magnitude. Compared with previous methods, this invention has a better effect on electric field mitigation, increases the breakdown voltage of the device, and makes the device more difficult to break down. In addition, by etching the barrier layer in the region below the gate to form a gate electrode trench, depositing a p-GaN layer on top of the gate electrode trench, and growing a gate dielectric layer between the p-GaN layer in the gate electrode trench and the gate electrode, a high threshold voltage and a large current are obtained, reducing the gate leakage current of the device, while improving the gate's withstand voltage capability, increasing the switching speed of the device, and improving the reliability of the device operation.

Description

Technical Field

[0001] This invention relates to the field of wide bandgap semiconductor materials and devices, and in particular to a grooved MIS structure transistor with a toothed p-GaN buried layer. Background Technology

[0002] Gallium nitride (GaN) material possesses wide bandgap and high-temperature resistance, enabling AlGaN / GaN HEMT devices to operate normally in environments with high temperatures, strong electric fields, and high frequencies and high power without affecting device characteristics. It has already seen significant development in fields such as new energy, electric vehicles, and 5G communications.

[0003] p-GaN gate HEMT devices achieve enhancement-mode functionality by growing a p-type doped GaN layer between the gate electrode and the AlGaN barrier layer, resulting in a positive threshold voltage. They offer advantages such as simple fabrication and minimal etching damage. However, their excessively low threshold voltage and low breakdown voltage during device shutdown necessitate the design of specialized drive circuits to ensure proper device operation. Therefore, improving the threshold voltage and breakdown voltage, increasing the device current, and enhancing the reliability of p-GaN HEMT devices remain ongoing challenges.

[0004] In existing technologies, GaN HEMT devices can employ methods such as field plate technology, ion implantation technology, and gate edge etching technology to improve the breakdown voltage of the device, while groove structures can improve the threshold voltage characteristics of the device. Patent application CN107170671A discloses a GaN power device based on ion implantation and its manufacturing method. However, its gate edge etching technology and field plate technology can only alleviate the local peak electric field at the edge of the gate electrode, but cannot alleviate the overall electric field variation and average electric field between the source and drain of the device, thus offering limited improvement in the device's breakdown voltage. Furthermore, ion implantation technology can damage the channel layer of the device, thereby affecting its breakdown voltage performance, reducing its reliability, and limiting its overall performance. Summary of the Invention

[0005] To overcome the shortcomings of the existing technology, the present invention aims to provide a grooved MIS structure transistor with a toothed p-GaN buried layer. By setting a toothed p-GaN buried layer between the source and drain in the GaN buffer layer, the electric field distribution between the gate and drain, between the gate and source, and between the source and drain can be improved, reducing the average electric field magnitude. Compared with previous methods, the present invention has a better effect on electric field mitigation, increases the breakdown voltage of the device, and makes the device more difficult to break down. Secondly, a groove structure is formed by etching the barrier layer in the region below the gate, a p-GaN layer is deposited above the groove, and a gate dielectric layer is grown between the grooved p-GaN layer and the gate electrode to obtain a high threshold voltage and large current, reduce the gate leakage current, improve the gate withstand voltage, increase the switching speed of the device, and improve the reliability of the device operation.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0008] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are square, arc-shaped, conical, trapezoidal, or stepped; the thickness of the source-drain inter-p-GaN buried layer 4 is 150nm to 300nm.

[0009] The cone's tip angle is 30° to 60°, the trapezoid's inclination angle is 45° to 90°, and the stepped shape's step inclination angle is 45° to 60°.

[0010] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0011] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are formed by integral solidification of Ti, Al, Ni and Au from bottom to top. Among them, Ti metal is the barrier layer metal. Ti diffuses into the AlGaN barrier layer 7 to form TiN with low work function and generate nitrogen vacancies, thereby forming an ohmic contact.

[0012] The depth of the gate electrode groove 8 is 20nm to 25nm.

[0013] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 3e. 16 cm -3 ~8e 17 cm -3 The p-type doping concentration in p-GaN layer 9 is 5e⁻¹. 17 cm -3 ~7e 17 cm -3 .

[0014] The nucleation layer 2 is composed of an AlGaN layer with a gradually changing Al composition, ranging from 150 nm to 200 nm in thickness from bottom to top. 0.2 Ga 0.8 N, 150nm~200nm thick Al 0.5 Ga 0.5 N and 150nm~200nm thick Al 0.8 Ga 0.2 N.

[0015] The gate electrode 11 is 3.5 to 4.0 μm long, the distance between the source electrode and the drain electrode is 10 to 15 μm, the distance between the gate electrode and the source electrode is 1 to 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm to 10 μm.

[0016] The gate dielectric layer 10 is made of a high dielectric constant dielectric material, including Al2O3 and AlN.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention provides a toothed p-GaN buried layer 4 between the source and drain in the GaN buffer layer, which can improve the electric field distribution between the gate and drain, between the gate and source, and between the source and drain of the device, and reduce the average electric field magnitude. Compared with the previous method, the present invention has a better effect on electric field mitigation, increases the breakdown voltage of the device, and makes the device more difficult to break down.

[0019] 2. By setting a toothed p-GaN buried layer 4 between the source and drain in the first GaN buffer layer, the carrier concentration can be increased, lattice defects reduced, lattice quality improved, and carrier mobility enhanced. This improves the electric field distribution between the gate and drain, between the gate and source, and between the source and drain, thereby reducing the average electric field magnitude. Compared to techniques such as gate edge technology, this method can alleviate the electric field distribution of the entire device, with a better electric field mitigation effect, which is beneficial to increasing the breakdown voltage of the device and making the device more difficult to break down. Compared with conventional p-GaN gate HEMT devices without the p-GaN buried layer 4 structure between the source and drain, the breakdown voltage of the device of this invention can reach 1421V, which greatly improves the device breakdown voltage. Secondly, by etching the barrier layer in the region below the gate to form a groove structure, a p-GaN layer is deposited on the groove to better deplete the two-dimensional electron gas (2DEG) below, thereby obtaining an enhancement-mode device.

[0020] 3. This invention forms a groove structure by etching the AlGaN barrier layer 7 in the region below the gate, and deposits a p-GaN layer 9 above the gate electrode groove 8 to better deplete the underlying two-dimensional electron gas (2DEG), resulting in an enhancement-mode device. A gate dielectric layer 10 grown between the groove p-GaN layer 9 and the gate electrode 11 provides a high threshold voltage and high current, reduces gate leakage current, improves gate withstand voltage, increases switching speed, and enhances device reliability. Compared to conventional devices, the breakdown voltage of this invention can reach 1421V, simplifying the fabrication process and reducing manufacturing costs.

[0021] 4. In the fabrication process of this invention, a gate dielectric layer 10 is used between the p-GaN layer 9 in the groove and the gate electrode 11 to obtain a high threshold voltage and a large current, reduce the gate leakage current of the device, improve the withstand voltage of the gate electrode, improve the switching speed of the device, and thus improve the reliability of the device during operation.

[0022] 5. The nucleation layer 2 of this invention is composed of an AlGaN layer with a graded Al composition; this avoids problems such as lattice mismatch and dislocation defects that occur when GaN layers are grown directly on the substrate, which affect the epitaxial effect of subsequent GaN layers; by adding an AlGaN layer with a graded Al composition as the nucleation layer, this invention improves the wettability between the GaN buffer layer and the substrate, reduces lattice mismatch, and reduces defects such as dislocations, thereby obtaining a high-quality GaN epitaxial layer. This can minimize lattice mismatch and stress problems during the material epitaxy process, which is beneficial for controlling the quality and stress of the GaN epitaxial layer.

[0023] In summary, the present invention has the advantages of increasing the breakdown voltage of the device, reducing the leakage current of the device, significantly increasing the threshold voltage of the device, obtaining a large current, suppressing the gate leakage phenomenon of the device, and improving the withstand voltage capability of the gate electrode and the switching speed of the device, thereby improving the reliability of the device. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the device structure of Embodiment 1 of the present invention.

[0025] Figure 2 This is a schematic diagram of the concentration distribution of two different p-GaN buried layers 4 in Embodiment 1 of the present invention.

[0026] Figure 3 This is a schematic diagram of the formation of a grooved MIS structure transistor with a toothed p-GaN buried layer according to the present invention.

[0027] Figure 4 This is a schematic diagram of the device structure in Embodiment 2 of the present invention.

[0028] Figure 5 This is a schematic diagram of the device structure in Embodiment 3 of the present invention.

[0029] Figure 6 This is a schematic diagram of the device structure in Embodiment 4 of the present invention.

[0030] Figure 7 This is a schematic diagram of the device structure in Embodiment 5 of the present invention.

[0031] Figure 8 This is a schematic diagram of the breakdown characteristics of the transistor with a grooved MIS structure containing a toothed p-GaN buried layer according to the present invention.

[0032] In the figure: 1. Substrate; 2. Nucleation layer; 3. First GaN buffer layer; 4. Source-drain p-GaN buried layer; 5. Second GaN buffer layer; 6. GaN layer; 7. AlGaN barrier layer; 8. Gate electrode trench; 9. p-GaN layer; 10. Gate dielectric layer; 11. Gate electrode; 12. Source electrode; 13. Drain electrode. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings.

[0034] Example 1

[0035] like Figure 1As shown, a grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to the shape of their contact surfaces.

[0036] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are square; the thickness of the source-drain inter-p-GaN buried layer 4 is 200 nm.

[0037] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 200nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0038] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0039] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0040] The depth of the gate electrode groove 8 is 25 nm.

[0041] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 3e. 16 cm -3 The p-type doping concentration in p-GaN layer 9 is 5e⁻¹.17 cm -3 .

[0042] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0043] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0044] The gate dielectric layer 10 is made of Al2O3.

[0045] like Figure 2 As shown, increasing the thickness of the p-GaN buried layer 4 between the source and drain and the p-type doping concentration (uniform concentration, high doping step concentration) at different locations can improve the overall performance of the device, including improving the electric field distribution, increasing the breakdown voltage, and reducing leakage current.

[0046] like Figure 3 The diagram illustrates the fabrication process of the device of the present invention. A substrate 1 is provided, and a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7 are sequentially deposited on the substrate 1. The toothed contact surfaces of the first GaN buffer layer 3, the source-drain p-GaN buried layer 4, and the second GaN buffer layer 5 are formed by etching. A gate electrode trench 8, a source electrode region, and a drain electrode region are etched on the AlGaN barrier layer 7. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are sequentially deposited in the gate electrode trench 8. The source electrode region and the drain electrode region are integrally solidified from bottom to top using Ti, Al, Ni, and Au.

[0047] Example 2

[0048] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0049] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are square; the thickness of the source-drain inter-p-GaN buried layer 4 is 250 nm.

[0050] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 250nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0051] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0052] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0053] The depth of the gate electrode groove 8 is 20 nm.

[0054] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 8e. 17 cm -3 The p-type doping concentration in p-GaN layer 9 is 7e. 17cm -3 .

[0055] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0056] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0057] The gate dielectric layer 10 is made of AlN.

[0058] Example 3

[0059] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0060] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are arc-shaped; the thickness of the source-drain inter-p-GaN buried layer 4 is 300 nm.

[0061] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 300nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0062] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0063] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0064] The depth of the gate electrode groove 8 is 25 nm.

[0065] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 3e. 16 cm -3 The p-type doping concentration in p-GaN layer 9 is 5e⁻¹. 17 cm -3 .

[0066] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0067] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0068] The gate dielectric layer 10 is made of Al2O3.

[0069] like Figure 4 As shown, the difference between this example and Examples 1 and 2 is that the p-GaN buried layer 4 between the source and drain in this example is an arc-shaped strip structure. The arc-shaped strip structure is closer to the electric field distribution below the gate electrode, both of which are divergent, which helps to reduce the overall electric field peak between the gate and drain, improve the electric field distribution, and help to improve the breakdown voltage.

[0070] Example 4

[0071] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0072] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are trapezoidal; the thickness of the source-drain inter-p-GaN buried layer 4 is 250 nm.

[0073] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 250nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0074] The trapezoid has an inclination angle of 75°.

[0075] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0076] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0077] The depth of the gate electrode groove 8 is 25 nm.

[0078] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 8e. 17 cm -3 The p-type doping concentration in p-GaN layer 9 is 7e. 17 cm -3 .

[0079] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0080] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0081] The gate dielectric layer 10 is made of AlN.

[0082] like Figure 5 As shown, the difference between this example and Example 1 is that the p-GaN buried layer 4 between the source and drain in this example has a trapezoidal strip structure, with each p-GaN layer spaced 1 μm apart. The thickness of the p-GaN buried layer 4 between the source and drain is 250 nm, and the trapezoidal tilt angle is 75°. The trapezoidal strip structure alleviates the electric field accumulation effect between the gate and source, improves the breakdown characteristics of the device, and enhances the reliability of the device.

[0083] Example 5

[0084] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0085] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are conical; the thickness of the source-drain inter-p-GaN buried layer 4 is 300 nm.

[0086] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 300nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0087] The cone's tip angle is 60°.

[0088] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0089] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0090] The depth of the gate electrode groove 8 is 20 nm.

[0091] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 3e. 16 cm -3 The p-type doping concentration in p-GaN layer 9 is 5e⁻¹. 17 cm -3 .

[0092] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0093] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0094] The gate dielectric layer 10 is made of Al2O3.

[0095] like Figure 6 As shown, the difference between this example and Example 1 is that the p-GaN buried layer 4 between the source and drain in this example is a conical strip structure with a spacing of 0.8 μm between each p-GaN block and an angle of 60° at the tip of the cone. The structure of this example can increase the breakdown voltage of the device, improve the surface electric field of the GaN HEMT device, reduce the average electric field distribution between the gate and drain, and make the surface electric field distribution of the device more uniform and the withstand voltage stronger.

[0096] Example 6

[0097] A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate 1, a nucleation layer 2, a first GaN buffer layer 3, a source-drain p-GaN buried layer 4, a second GaN buffer layer 5, a GaN layer 6, and an AlGaN barrier layer 7. A drain electrode 13 and a source electrode 12 are respectively provided on both sides of the AlGaN barrier layer 7. A gate electrode groove 8 is provided on the side of the AlGaN barrier layer 7 near the drain electrode 13. A p-GaN layer 9, a gate dielectric layer 10, and a gate electrode 11 are disposed in the gate electrode groove 8 from bottom to top. Toothed protrusions and grooves adapted to the protrusions are distributed on the opposite side of the first GaN buffer layer 3 and the second GaN buffer layer 5. The source-drain p-GaN buried layer 4 is located between the first GaN buffer layer 3 and the second GaN buffer layer 5, and the shape of the contact surface between the source-drain p-GaN buried layer 4 and the first GaN buffer layer 3 and the second GaN buffer layer 5 is adapted to each other.

[0098] The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer 3 and the second GaN buffer layer 5 are stepped; the thickness of the source-drain inter-p-GaN buried layer 4 is 200 nm.

[0099] The first GaN buffer layer is 3mm thick and 5μm thick, the p-GaN buried layer between the source and drain is 4mm thick and 200nm thick, the second GaN buffer layer is 5mm thick and 45μm thick, the GaN layer is 6mm thick and 100nm thick, the AlGaN barrier layer is 7mm thick and 60nm thick, the p-GaN layer is 9mm thick and 120nm thick, and the gate dielectric layer is 10mm thick and 20nm thick.

[0100] The stepped shape has a step inclination angle of 45°.

[0101] The gate electrode 11 is a Schottky contact, and the source electrode 12 and the drain electrode 13 are respectively in contact with the AlGaN barrier layer 7, and the source electrode 12 and the drain electrode 13 are not connected to each other.

[0102] Both the source electrode 12 and the drain electrode 13 use Ti as the base metal, and are integrally solidified from bottom to top as Ti, Al, Ni, and Au. Ti metal serves as the barrier layer metal, diffusing into the AlGaN barrier layer 7 to form TiN with a low work function and generating a large number of nitrogen vacancies, thus forming an ohmic contact. The thicknesses of Ti, Al, Ni, and Au are 40 nm, 80 nm, 40 nm, and 120 nm, respectively. Al metal acts as a capping layer metal, acting as a catalyst to promote the formation of TiN from nitrogen in GaN. Ni and Au are capping layer metals; Ni prevents the upper Au from diffusing downwards, while Au provides protection against oxidation of the underlying metal.

[0103] The depth of the gate electrode groove 8 is 25 nm.

[0104] The p-type doping concentration of the p-GaN buried layer 4 between the source and drain is 8e. 17 cm -3 The p-type doping concentration in p-GaN layer 9 is 7e. 17 cm -3 .

[0105] The nucleation layer 2 is composed of AlGaN with a gradually changing Al composition, consisting of 200 nm thick Al layers from bottom to top. 0.2 Ga 0.8 N, 200nm thick Al 0.5 Ga 0.5 N and 200nm thick Al 0.8 Ga 0.2 N; This nucleation layer can minimize lattice mismatch and stress problems during the epitaxial process, which is beneficial for controlling the quality and stress of GaN epitaxial layers.

[0106] The gate electrode 11 is 3.5 μm long, the distance between the source electrode and the drain electrode is 15 μm, the distance between the gate electrode and the source electrode is 2.5 μm, and the distance between the gate electrode and the drain electrode is 8.5 μm.

[0107] The gate dielectric layer 10 is made of AlN.

[0108] like Figure 7 As shown, the difference between this example and Example 1 is that the p-GaN buried layer 4 between the source and drain in this example has a stepped structure between the gate and source, with each small p-GaN block having a lateral distance of 1 μm and a step tilt angle of 45°. This stepped p-GaN buried layer between the gate and source in this example improves the electric field distribution at the source end of the gate electrode, making the electric field distribution at the drain end of the gate electrode more uniform and approaching the critical breakdown electric field, thereby increasing the breakdown voltage of the device and reducing leakage current at the gate electrode.

[0109] like Figure 8The figure shows a comparison of the breakdown characteristics of the present invention and conventional devices. The conventional device refers to a standard p-GaN HEMT device without a p-GaN buried layer. It can be seen that conventional p-GaN HEMT devices break down at around 400V, limiting their application in high-voltage scenarios. The transistor of the present invention incorporates a toothed p-GaN buried layer between the source and drain in the GaN buffer layer, improving the overall electric field distribution and providing better electric field mitigation. This enhances the breakdown voltage, exceeding 1400V, thus improving the device's reliability and enabling its application in high-voltage, high-power applications.

[0110] The above are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A grooved MIS structure transistor with a toothed p-GaN buried layer, comprising, from bottom to top, a substrate (1), a nucleation layer (2), a first GaN buffer layer (3), a source-drain inter-p-GaN buried layer (4), a second GaN buffer layer (5), a GaN layer (6), and an AlGaN barrier layer (7); characterized in that, The AlGaN barrier layer (7) has a drain electrode (13) and a source electrode (12) on both sides. A gate electrode groove (8) is provided on the side of the AlGaN barrier layer (7) near the drain electrode (13). A p-GaN layer (9), a gate dielectric layer (10) and a gate electrode (11) are arranged from bottom to top in the gate electrode groove (8). The first GaN buffer layer (3) and the second GaN buffer layer (5) have tooth-shaped protrusions and grooves that match the protrusions on their opposite sides. The p-GaN buried layer (4) between the source and drain is located between the first GaN buffer layer (3) and the second GaN buffer layer (5). The p-GaN buried layer (4) between the source and drain is adapted to the shape of the contact surface between the first GaN buffer layer (3) and the second GaN buffer layer (5).

2. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The tooth-like protrusions and grooves on the opposite surfaces of the first GaN buffer layer (3) and the second GaN buffer layer (5) are square, arc-shaped, conical, trapezoidal or stepped; the thickness of the source-drain inter-p-GaN buried layer (4) is 150nm~300nm.

3. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 2, characterized in that, The cone's tip angle is 30°~60°, the trapezoid's inclination angle is 45°~90°, and the stepped shape's step inclination angle is 45°~60°.

4. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The gate electrode (11) is a Schottky contact, and the source electrode (12) and drain electrode (13) are respectively in contact with the AlGaN barrier layer (7), and the source electrode (12) and drain electrode (13) are not connected to each other.

5. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1 or 4, characterized in that, The source electrode (12) and drain electrode (13) are both made of Ti as the base metal. From bottom to top, Ti, Al, Ni and Au are solidified as a whole. Among them, Ti metal is the barrier layer metal. Ti diffuses into the AlGaN barrier layer (7) to form TiN with low work function and generate nitrogen vacancies, thereby forming an ohmic contact.

6. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The depth of the gate electrode groove (8) is 20nm~25nm.

7. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The p-type doping concentration of the p-GaN buried layer (4) between the source and drain is 3e16cm. -3 ~8e17cm -3 The p-type doping concentration in the p-GaN layer (9) is 5e17cm. -3 ~7e17cm -3 .

8. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The nucleation layer (2) is composed of AlGaN with a gradually changing Al composition, and consists of Al layers with a thickness of 150nm~200nm from bottom to top. 0.2 Ga 0.8 N, 150nm~200nm thick Al 0.5 Ga 0.5 N and 150nm~200nm thick Al 0.8 Ga 0.2 N.

9. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The gate electrode (11) is 3.5~4.0μm long, the distance between the source electrode and the drain electrode is 10~15μm, the distance between the gate electrode and the source electrode is 1~2.5μm, and the distance between the gate electrode and the drain electrode is 8.5μm-10μm.

10. A grooved MIS structure transistor with a toothed p-GaN buried layer according to claim 1, characterized in that, The gate dielectric layer (10) is made of Al2O3 or AlN.

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