Semiconductor device and electronic equipment

Abstract

According to the semiconductor device and the electronic equipment provided by the invention, Schottky contact and ohmic contact exist on the interface of the grid electrode, that is, a JFET-like equivalent structure is formed on the grid electrode, so that the advantages of low grid leakage of a Schottky contact type P-GaN grid device and stable threshold voltage of an ohmic contact type P-GaN grid device can be combined; the problem that the threshold voltage is unstable due to the fact that the potential of the P-GaN cap layer in a traditional Schottky contact type P-GaN gate relatively floats is solved. According to the P-GaN ohmic island structure with the P-type lightly-doped GaN layer and the P-type heavily-doped GaN layer, self-clamping of gate leakage current can be achieved; and at least one row of dispersed P-type doped GaN structures are arranged along the second direction, a channel pinch-off effect is optimized into a pinch-off effect in a two-dimensional direction by utilizing a curvature effect, and the dispersed P-type doped GaN structures can realize a gate leakage self-clamping effect of the device with a wider P-GaN ohmic island size.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) based on AlGaN / GaN heterostructures can meet the requirements of power electronic systems in terms of high temperature, high voltage, high frequency, and miniaturization, and have become one of the best candidates for realizing next-generation high power density power systems. P-GaN gates, as the mainstream scheme for realizing enhancement-mode GaN HEMT power devices, have been a research hotspot in recent years.

[0003] Based on the different contact methods between the gate metal and the P-GaN layer, P-GaN HEMT devices can be divided into two categories: ohmic contact type and Schottky contact type. Ohmic contact P-GaN HEMT devices are current-driven, exhibiting large gate leakage current and limited gate swing; while Schottky contact P-GaN HEMT devices are voltage-driven, characterized by suppressed leakage current and larger gate swing. However, due to the relatively fluctuating potential of the P-GaN layer, the threshold voltage stability of Schottky contact P-GaN HEMT devices remains a concern. Therefore, realizing normally-off devices with low gate leakage current and good gate stability is ideal and crucial. Summary of the Invention

[0004] This disclosure provides a semiconductor device and an electronic device that solves the problem of unstable threshold voltage caused by the relative fluctuation of the P-GaN layer potential in traditional Schottky contact P-GaN HEMT devices, and can achieve a self-clamping effect for gate leakage, greatly improving the reliability of P-GaN HEMT devices.

[0005] The specific plan disclosed herein is as follows: On one hand, embodiments of this disclosure provide a semiconductor device, including: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. At least one row of P-type doped GaN structures are arranged at intervals along a second direction on the side of the P-GaN cap layer away from the substrate, the second direction being perpendicular to the first direction and parallel to the substrate; each P-type doped GaN structure includes: a lightly doped P-type GaN layer on the P-GaN cap layer, and a heavily doped P-type GaN layer on the lightly doped P-type GaN layer; wherein the cross-sectional width of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction. The gate is located on the side of the P-GaN cap layer away from the substrate and covers each of the P-type doped GaN structures. The interface between the gate and the P-GaN cap layer and the lightly doped P-type GaN layer is a Schottky contact, and the interface between the gate and the heavily doped P-type GaN layer is an ohmic contact.

[0006] In some embodiments, the semiconductor device provided in the present disclosure includes multiple rows of P-type doped GaN structures spaced apart along the second direction, and each P-type doped GaN structure is distributed in a lattice.

[0007] In some embodiments, in the semiconductor device provided in the present disclosure, the doping concentration of the P-GaN cap layer is between the doping concentration of the lightly doped P-type GaN layer and the doping concentration of the heavily doped P-type GaN layer.

[0008] In some embodiments, in the semiconductor device provided in this disclosure, the doping concentration of the heavily doped P-type GaN layer is 1×10⁻⁶. 20 ~5×10 20 cm -3 The doping concentration of the lightly doped P-type GaN layer is 1×10⁻⁶. 17 ~5×10 18 cm -3 The doping concentration of the P-GaN cap layer is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 .

[0009] In some embodiments, in the semiconductor device provided in the present disclosure, the thickness of the P-type heavily doped GaN layer is 5~30 nm, the thickness of the P-type lightly doped GaN layer is 10~200 nm, and the thickness of the P-GaN cap layer is 50~120 nm.

[0010] In some embodiments, in the semiconductor device provided in the present disclosure, the gate completely encapsulates each of the P-type doped GaN structures, and the cross-sectional width of the gate along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction.

[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the cross-sectional widths of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer are equal along the first direction.

[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the orthographic projection of the lightly doped P-type GaN layer on the substrate and the orthographic projection of the heavily doped P-type GaN layer on the substrate coincide.

[0013] In some embodiments, in the semiconductor device provided in the present disclosure, the orthographic projection shape of the P-type doped GaN structure on the substrate includes at least one of a circle, a square, and a hexagon.

[0014] Accordingly, this disclosure also provides an electronic device, including any of the semiconductor devices described above in this disclosure.

[0015] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device and electronic device in which the gate interface contains both Schottky and ohmic contacts, forming a JFET-like structure at the gate. This combines the advantages of low gate leakage current of Schottky contact P-GaN gate devices and stable threshold voltage of ohmic contact P-GaN gate devices, solving the problem of unstable threshold voltage caused by the relatively fluctuating potential of the P-GaN cap layer in traditional Schottky contact P-GaN gates. Furthermore, by adding a lightly doped P-type GaN layer between the heavily doped P-type GaN layer and the P-GaN cap layer, a lower hole density distribution is achieved from the heavily doped P-type GaN layer to the P-GaN cap layer with weaker doping, adjusting the size of the "leakage path" and making the JFET-like structure easier to turn off under high gate voltage conditions, effectively "pinching off" the "leakage path" of the ohmic island. Devices with ohmic island structures solve the threshold instability problem caused by net charge accumulation in Schottky contact P-GaN gate devices at lower gate voltages due to the presence of a "discharge" channel. Simultaneously, at higher gate voltages, the "discharge" channel of this type of JFET is "pinched off," clamping the gate leakage current and resolving the problem of excessive gate leakage in ohmic contact P-GaN gate devices. Furthermore, this disclosure optimizes the channel pinch-off effect into a two-dimensional effect by providing at least one row of dispersed P-type doped GaN structures along a second direction, utilizing the curvature effect. The dispersed P-type doped GaN structures can achieve gate leakage self-clamping effects with a wider range of P-GaN ohmic island sizes. Attached Figure Description

[0016] Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A cross-sectional schematic diagram; Figure 3 for Figure 1 A top-view plan view; Figure 4 for Figure 3 Schematic diagram of the corresponding channel clamping effect; Figure 5 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 6 for Figure 5 A cross-sectional schematic diagram; Figure 7 for Figure 5 A top-view plan view; Figure 8 A type of I corresponding to the conventional fin-shaped ohmic island device and the dispersed columnar ohmic island device disclosed herein. DS -V GS Line graph; Figure 9 This is another type of I corresponding to the traditional fin-shaped ohmic island device and the dispersed columnar ohmic island device disclosed herein. DS -V GS Line graph. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0018] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0019] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0020] This disclosure provides a semiconductor device, such as... Figures 1-3 As shown, Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A cross-sectional schematic diagram, Figure 3 for Figure 1 The schematic diagram is shown in the top view. The semiconductor device includes: a substrate 1, a channel layer 2, and a barrier layer 3 stacked sequentially. Specifically, the channel layer 2 and the barrier layer 3 form a heterojunction. The heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects, that is, a 2DEG channel is formed. The source electrode 4 and the drain electrode 5 are spaced apart and located on the side of the barrier layer 3 and / or the channel layer 2 away from the substrate 1. For example, the source electrode 4 and the drain electrode 5 may both be located on the side of the barrier layer 3 away from the substrate 1, or the source electrode 4 and the drain electrode 5 may both be in contact with the channel layer 2 through vias penetrating the barrier layer 3 (i.e., the source electrode 4 and the drain electrode 5 may both be located on the side of the channel layer 2 away from the substrate 1), or a portion of the source electrode 4 and the drain electrode 5 may be located on the side of the barrier layer 3 away from the substrate 1, and the other portion may be in contact with the channel layer 2 through vias penetrating the barrier layer 3. Specifically, the source electrode 4 and the drain electrode 5 form an ohmic contact with the barrier layer 3 and the channel layer 2. The P-GaN cap layer 6 is located on the side of the barrier layer 3 away from the substrate 1, and is situated between the source 4 and the drain 5. The source 4, the P-GaN cap layer 6, and the drain 5 are arranged sequentially along the first direction X, which is parallel to the substrate 1. The P-GaN cap layer 6 is used to ensure the threshold stability of the device. At least one row of P-type doped GaN structures 7 are arranged at intervals along the second direction Y (i.e., the extension direction of the source and drain) on the side of the P-GaN cap layer 6 away from the substrate 1. The second direction Y is perpendicular to the first direction X and parallel to the substrate 1. In this embodiment, a row of P-type doped GaN structures 7 arranged at intervals along the second direction Y is used as an example. Each P-type doped GaN structure 7 includes: a lightly doped P-type GaN layer 71 on the P-GaN cap layer 6, and a heavily doped P-type GaN layer 72 (i.e., P++ GaN layer) on the lightly doped P-type GaN layer 71. The cross-sectional widths of the heavily doped P-type GaN layer 72 and the lightly doped P-type GaN layer 71 along the first direction X are both smaller than the cross-sectional width of the P-GaN cap layer 6 along the first direction X. Gate 8 is located on the side of P-GaN cap layer 6 away from substrate 1 and covers each P-type doped GaN structure 7. The interface between gate 8 and P-GaN cap layer 6 and lightly doped P-type GaN layer 71 is a Schottky contact, and the interface between gate 8 and heavily doped P-type GaN layer 72 is an ohmic contact, which is a P-type ohmic contact.

[0021] The semiconductor device provided in this disclosure provides at least one row of P-type doped GaN structures (i.e., P-GaN ohmic islands) arranged at intervals along a second direction on the side of the P-GaN cap layer away from the substrate. That is, multiple P-type doped GaN structures are dispersed on the P-GaN cap layer. The interfaces between the lightly doped P-type GaN layer and the P-GaN cap layer in the P-type doped GaN structure and the gate are Schottky contacts, while the interfaces between the heavily doped P-type GaN layer and the gate are ohmic contacts. In other words, the gate interface has both Schottky and ohmic contacts, forming a JFET-like equivalent structure on the gate. This combines the advantages of low gate leakage of Schottky contact P-GaN gate devices and stable threshold voltage of ohmic contact P-GaN gate devices, solving the problem of unstable threshold voltage caused by the relative fluctuation of the P-GaN cap layer potential in traditional Schottky contact P-GaN gates. While realizing enhancement-mode HEMT power devices, it greatly improves the gate reliability of P-GaN gate enhancement-mode HEMT power devices. Furthermore, by adding a lightly doped P-type GaN layer between the heavily doped P-type GaN layer and the P-GaN cap layer, a lower hole density distribution is achieved from the heavily doped P-type GaN layer to the P-GaN cap layer with weaker doping, thus adjusting the size of the "leakage path" and making the JFET-like structure easier to turn off under high gate voltage conditions, effectively "pinching off" the "leakage path" of the ohmic island. Devices with an ohmic island structure, due to the "leakage path" at lower gate voltages, solve the threshold instability problem caused by net charge accumulation in Schottky contact P-GaN gate devices. Simultaneously, at higher gate voltages, the "leakage path" of this type of JFET is "pinched off," clamping the gate leakage current. That is, once the gate voltage is sufficiently high, the gate leakage current is clamped and no longer increases, solving the problem of excessive gate leakage in ohmic contact P-GaN gate devices. Moreover, this disclosure optimizes the channel pinch-off effect into a two-dimensional pinch-off effect by setting at least one row of dispersed P-type doped GaN structures along the second direction, utilizing the curvature effect, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of the channel pinch-off effect. The solid black arrows indicate the pinch-off effect in the two-dimensional direction. Therefore, the dispersed P-type doped GaN structure can achieve the gate leakage self-clamping effect of the device with a wider range of P-GaN ohmic island sizes.

[0022] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2As shown, the cross-sectional widths of the heavily doped P-type GaN layer 72 and the lightly doped P-type GaN layer 71 along the first direction X are equal. This simplifies the fabrication process and improves the gate reliability of P-GaN gate enhancement-mode HEMT power devices. Of course, the cross-sectional widths of the heavily doped P-type GaN layer 72 and the lightly doped P-type GaN layer 71 are not limited to being equal; for example, the cross-sectional width of the lightly doped P-type GaN layer 71 can be greater than that of the heavily doped P-type GaN layer 72.

[0023] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projections of the lightly doped P-type GaN layer 71 and the heavily doped P-type GaN layer 72 on substrate 1 coincide. This further simplifies the fabrication process and improves the gate reliability of P-GaN gate enhancement-type HEMT power devices. Of course, the orthographic projections of the lightly doped P-type GaN layer 71 and the heavily doped P-type GaN layer 72 on substrate 1 are not limited to coinciding; for example, the orthographic projection area of ​​the lightly doped P-type GaN layer 71 on substrate 1 can be larger than that of the heavily doped P-type GaN layer 72 on substrate 1.

[0024] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projection shape of the P-type doped GaN structure 7 on the substrate 1 includes at least one of a circle, a square, and a hexagon. In this embodiment, a circle is used as an example, that is, the P-type doped GaN structure 7 of this disclosure is a columnar Ohm island. Through the columnar structure design, the curvature effect is utilized to further optimize the gate leakage self-clamping effect.

[0025] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, in implementing both ohmic and Schottky contacts between the gate and the P-type doped GaN structure 7, after forming the P-type doped GaN structure 7, a low work function metal can be directly used to form the gate, followed by high-temperature annealing. The portion in contact with the heavily doped P-type GaN layer 72 in the P-type doped GaN structure 7 forms an ohmic contact, while the portion in contact with the lightly doped P-type GaN layer 71 in the P-type doped GaN structure 7 forms a Schottky contact. Of course, other methods can also be used, and this disclosure does not limit this approach.

[0026] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 5-7 As shown, Figure 5 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 6 for Figure 5 A cross-sectional schematic diagram, Figure 7 for Figure 5 A top-view plan view, this embodiment and Figures 1-3 The difference lies in that the semiconductor device in this embodiment includes multiple rows of P-type doped GaN structures 7 spaced apart along the second direction Y. This embodiment takes three rows of P-type doped GaN structures 7 spaced apart along the second direction Y as an example, but it is not limited to this; for example, it can also be two rows, four rows, etc. Each P-type doped GaN structure 7 is distributed in a lattice. Through the lattice structure design, the curvature effect is utilized to further optimize the gate leakage self-clamping effect. Specifically, the lattice distribution can be orthogonal, hexagonal, etc. This embodiment takes an orthogonal distribution as an example, that is, it is distributed in an array along the first direction X and the second direction Y. The distribution density and size of each P-type doped GaN structure 7 can be designed as needed, and this disclosure does not limit this.

[0027] In some embodiments, such as Figures 1-7 As shown, the columnar P-type doped GaN structure 7 of this disclosure, compared with the conventional Schottky P-type gate GaN device, has a P-type ohmic contact formed between the gate 8 and the heavily P-type doped GaN layer 72, which provides a discharge channel for holes generated by the irradiation effect. Therefore, the semiconductor device of this disclosure has an irradiation hardening effect.

[0028] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-7 As shown, the doping concentration of the P-GaN cap layer 6 can be between the doping concentration of the lightly doped P-type GaN layer 71 and the doping concentration of the heavily doped P-type GaN layer 72. In some embodiments, the doping concentration of the heavily doped P-type GaN layer 72 is 1 × 10⁻⁶. 20 ~5×10 20 cm -3 For example, 1×10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 and 5×10 20 cm -3 The doping concentration of the lightly doped p-type GaN layer 71 is 1 × 10⁻⁶. 17 ~5×10 18 cm -3 For example, 1×10 17 cm -3 2×10 17 cm -3 3×10 17 cm -3 4×10 17 cm-3 5×10 17 cm -3 6×10 17 cm -3 7×10 17 cm -3 8×10 17 cm -3 9×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 and 5×10 18 cm -3 etc.; the doping concentration of P-GaN cap layer 6 is 5×10⁶. 18 ~5×10 19 cm -3 For example, 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 and 5×10 19 cm -3 The doping concentration of the lightly doped P-type GaN layer 71 and the doping concentration of the P-GaN cap layer 6 can be the same or different.

[0029] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-7As shown, the thickness of the heavily doped P-type GaN layer 72 can be 5~30 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc.; the thickness of the lightly doped P-type GaN layer 71 can be 10~200 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.; and the thickness of the P-GaN cap layer 6 can be 50~120 nm, such as 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc. This can further improve the problem of threshold instability caused by the relatively fluctuating potential of the P-GaN cap layer in traditional Schottky contact P-GaN gates, and further optimize the gate leakage self-clamping effect.

[0030] In some embodiments, such as Figures 1-7 As shown, the area of ​​the P-type ohmic contact of the overall device can be adjusted by adjusting the size of the P-type doped GaN structure 7, further balancing the problems of large gate leakage current and unstable threshold of the traditional P-GaN gate device ohmic contact and Schottky contact.

[0031] In some embodiments, such as Figures 1-7 As shown, by adjusting parameters such as the height, radius, and doping concentration of the columnar P-type doped GaN structure 7, the columnar structure can more easily achieve gate leakage self-clamping effect, enabling the device to achieve lower gate leakage under the effect of threshold stability.

[0032] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-7 As shown, the gate 8 completely encapsulates each P-type doped GaN structure 7, and the cross-sectional width of the gate 8 along the first direction X is smaller than the cross-sectional width of the P-GaN cap layer 6 along the first direction X. This can further improve device performance.

[0033] In some embodiments, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the semiconductor device provided in this embodiment of the present disclosure further includes a dielectric layer (not shown in this disclosure) filled between the source, drain and gate, and the material of the dielectric layer may be SiO2, SiNx, AlN, etc.

[0034] In some embodiments, the substrate 1 of this disclosure may be a Si, SiC, GaN, sapphire, diamond, SOI, QST composite substrate, etc., and this disclosure does not limit it.

[0035] In some embodiments, the channel layer 2 of this disclosure may be made of GaN; the barrier layer 3 may be made of Al(In,Ga)N. For example, the barrier layer 3 may be an AlN binary alloy layer, an AlGaN, AlInN, or InGaN ternary alloy layer, or an AlInGaN quaternary alloy layer.

[0036] In some embodiments, the P-GaN cap layer 6 of this disclosure may be GaN doped with at least one of magnesium (Mg), iron (Fe), zinc (Zn) and carbon (C).

[0037] In some embodiments, the material of the source 4 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; the material of the drain 5 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; and the material of the gate 8 of this disclosure may be one or more combinations of Ti, Al, Ni, and Au.

[0038] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, it also includes a buffer layer 9 located between the substrate 1 and the channel layer 2, and the material of the buffer layer 9 includes at least one of AlN, AlGaN and GaN.

[0039] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, it may also include a nucleation layer 10 located between the substrate 1 and the buffer layer 9. The nucleation layer 10 can avoid the problem of cracks in the buffer layer 9 caused by lattice mismatch and thermal mismatch when the buffer layer 9 is formed directly on the substrate 1, which would lead to a decrease in crystal quality. The material of the nucleation layer 10 can be one or more combinations of AlN, GaN, and AlGaN.

[0040] The inventors of this disclosure Figure 1 Taking the semiconductor device shown as an example, its gate leakage self-clamping effect is demonstrated through 3D simulation. Figure 8 and Figure 9 As shown, Figure 8 and Figure 9 All of these correspond to the traditional fin-shaped ohmic island device and the dispersed columnar ohmic island device disclosed herein. DS -V GS A curve graph, in which, Figure 8 The height (t) of the traditional fin-shaped ohm islands and the columnar p-type doped GaN structure disclosed herein IOBoth are 180 nm. Figure 9 The height (t) of the traditional fin-shaped ohm islands and the columnar p-type doped GaN structure disclosed herein IO Both are 350 nm. Figure 8 and Figure 9 The radii of both the fin-shaped ohmic islands and the columnar p-type doped GaN structure 7 are 150 nm. Figure 8 and Figure 9 Curve A in the figure represents the I of a traditional finned ohm island device. DS -V GS curve, Figure 8 and Figure 9 Curve B in the figure represents the I of the dispersed columnar ohmic island device disclosed herein. DS -V GS The curve shows that, for the same Ohm island height and length / radius, the device disclosed herein exhibits a higher gate-source voltage Vo. GS As it continues to increase, the source-drain current I DS The current tends to be flat and relatively low, while the source-drain current I of traditional devices... DS The columnar P-type doped GaN structure 7 (Ohm Island) used in this disclosure has a more obvious gate leakage self-clamping effect due to its continuous increasing trend and relatively large size.

[0041] To better understand the semiconductor devices provided in the embodiments of this disclosure, the fabrication process of the semiconductor devices is described in detail.

[0042] In some embodiments, the fabrication process of the semiconductor device disclosed herein may specifically include the following steps: (1) Using methods such as MOCVD, nucleation layer, buffer layer, channel layer and barrier layer are grown on the substrate.

[0043] (2) A P-type material layer is formed on the barrier layer. According to the strength of P-type doping, it is divided into three layers, from bottom to top: a P-GaN cap layer, a lightly doped P-type GaN layer, and a heavily doped P-type GaN layer, which are used to form the threshold voltage of the device.

[0044] (3) Partially etch the P-type material layer to the P-GaN cap layer to define the columnar P-type doped GaN structure; then etch the P-GaN cap layer to the barrier layer to define the P-GaN cap layer.

[0045] (4) A source and a drain are formed on the barrier layer and the channel layer, wherein the source and the drain are in ohmic contact with the barrier layer and the channel layer.

[0046] (5) A gate is formed on the barrier layer and around the P-type doped GaN structure, wherein the gate forms a Schottky contact with the P-GaN cap layer and the lightly doped P-type GaN layer, and an ohmic contact with the heavily doped P-type GaN layer. The cross-sectional width of the gate along the first direction (i.e., the arrangement direction of the source, P-GaN cap layer and drain) is smaller than the cross-sectional width of the P-GaN cap layer along the first direction, and the gate completely encloses the P-type doped GaN structure.

[0047] (6) A dielectric layer is formed between the source and the gate and between the drain and the gate, located above the barrier layer.

[0048] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.

[0049] In some embodiments, the electronic device provided in this disclosure can be a power supply, a photovoltaic system, an industrial motor, or an electric vehicle, etc. The disclosed embodiments do not impose any special limitations on the specific form of the electronic device.

[0050] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0051] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. At least one row of P-type doped GaN structures are located on the side of the P-GaN cap layer away from the substrate and are spaced apart along a second direction, wherein the second direction is perpendicular to the first direction and parallel to the substrate. Each of the P-type doped GaN structures includes: a lightly doped P-type GaN layer on the P-GaN cap layer, and a heavily doped P-type GaN layer on the lightly doped P-type GaN layer; wherein the cross-sectional width of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction. The gate is located on the side of the P-GaN cap layer away from the substrate and covers each of the P-type doped GaN structures. The interface between the gate and the P-GaN cap layer and the lightly doped P-type GaN layer is a Schottky contact, and the interface between the gate and the heavily doped P-type GaN layer is an ohmic contact.

2. The semiconductor device as claimed in claim 1, characterized in that, It includes multiple rows of P-type doped GaN structures spaced apart along the second direction, with each P-type doped GaN structure arranged in a lattice pattern.

3. The semiconductor device as described in claim 1, characterized in that, The doping concentration of the P-GaN cap layer is between that of the lightly doped P-type GaN layer and the heavily doped P-type GaN layer.

4. The semiconductor device as described in claim 3, characterized in that, The doping concentration of the p-type heavily doped GaN layer is 1×10⁻⁶. 20 ~5×10 20 cm -3 The doping concentration of the lightly doped P-type GaN layer is 1×10⁻⁶. 17 ~5×10 18 cm -3 The doping concentration of the P-GaN cap layer is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 .

5. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the heavily doped P-type GaN layer is 5~30 nm, the thickness of the lightly doped P-type GaN layer is 10~200 nm, and the thickness of the P-GaN cap layer is 50~120 nm.

6. The semiconductor device as claimed in claim 1, characterized in that, The gate completely encloses each of the P-type doped GaN structures, and the cross-sectional width of the gate along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction.

7. The semiconductor device as claimed in claim 1, characterized in that, The cross-sectional widths of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer are equal along the first direction.

8. The semiconductor device as claimed in claim 7, characterized in that, The orthographic projection of the lightly doped P-type GaN layer on the substrate and the orthographic projection of the heavily doped P-type GaN layer on the substrate coincide.

9. The semiconductor device as claimed in claim 8, characterized in that, The orthographic projection shape of the P-type doped GaN structure on the substrate includes at least one of a circle, a square, and a hexagon.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1-9.

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