On-chip network interface automatic matching method and system based on hierarchical mark driving

Abstract

The invention is suitable for the technical field of chips, and provides an on-chip network interface automatic matching method and system based on hierarchical mark driving, and the method comprises the steps: extracting module definition, a port list and interface signal information from a module Verilog file; performing layered marking on the interface signals based on a naming rule; customizing a connection rule; executing an automatic matching algorithm according to the mark information, and determining a connection relation between the signals; generating a complete top-layer Verilog code according to a matching result; and a visual interaction interface can be provided, a hierarchical tree view display interface state is provided, and screening, grouping and highlight display are supported. The system is specially designed for a large complex chip with NoC as the center, efficient and accurate automatic signal connection is achieved by systematically analyzing structural information contained in a signal naming rule, a hierarchical visual interface is provided, and a user is helped to rapidly position and solve the connection problem.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and particularly relates to an on-chip network interface automatic matching method and system based on hierarchical marking drive. Background Art

[0002] With the exponential growth of the scale and complexity of integrated circuit design, the number of functional modules and interface signals included in modern chip design has reached an unprecedented scale. In the design of large-scale system-on-chip (SoC), NoC (Network-on-Chip) is widely used to construct the top-level topology of the chip. All Agent modules communicate through the NoC, resulting in a large number of module instantiations at the top level. Its interface scale is huge and the structure is complex, but it has obvious hierarchical characteristics, and the proportion of standard bus interfaces usually exceeds 95%. Existing tools lack a dedicated optimization mechanism for such architectures.

[0003] Currently, during the design process, the number of interconnection signal lines that design engineers need to manually write often reaches thousands. The top-level topology may need to go through hundreds of iterations of modification. Manual connection work not only consumes a large amount of engineering time, but also is extremely prone to introducing errors, affecting the design reliability.

[0004] Although existing automatic wiring technologies attempt to achieve the automatic generation of top-level files to reduce manual intervention by manually writing configuration files or templates to define module levels and interface information. However, when the number of modules exceeds one hundred levels or the interface complexity increases, the maintenance cost of the configuration file increases exponentially. It is necessary to manually synchronize and update module names, port names, and parameters. The operation is time-consuming and prone to spelling mistakes or parameter omissions, resulting in low design iteration efficiency.

[0005] In addition, the matching mechanism based on common interface names or keywords cannot handle the signal-level matching requirements of complex bus protocols such as AXI (Advanced eXtensible Interface) / AHB (Advanced High-performance Bus) / APB (Advanced Peripheral Bus). Signals with the same name in multiple modules may cause incorrect connections due to differences in bit width or protocol type. Existing technologies lack protocol awareness, resulting in signal timing errors that require manual secondary debugging. Although some tools allow users to customize connection relationships, they lack an intelligent conflict detection mechanism. After manual modification by users, the implicit dependency relationships between modules may be damaged, and the bit width matching or direction consistency cannot be automatically verified, resulting in abnormal functions after synthesis.

[0006] There are also defects in the visual interface design. When the module interfaces exceed one hundred levels, the signal groups are not effectively folded or status marked. Users need to manually expand a large number of signals, and it is difficult to quickly identify the key connection status, resulting in a sharp drop in debugging efficiency.

[0007] The protocol version adaptation limitations of the naming rules further exacerbate the maintenance difficulty. When a module needs to support multiple protocols or protocol upgrades, all relevant modules need to be modified for naming conflicts, and compatibility problems occur frequently. Moreover, the systematic lack of a verification mechanism makes potential problems such as bit-width mismatch and asynchronous clock domains only discovered during synthesis or simulation, and manual line-by-line troubleshooting is time-consuming and laborious. The fundamental contradiction lies in that the existing technologies overly rely on manual input and general matching rules, fail to solve the imbalance between the automation level and design complexity in large-scale chip design, and lack intelligent matching with protocol awareness, dynamic priority management, and in-depth verification capabilities.

[0008] Therefore, generally speaking, the existing interface matching methods for on-chip networks have problems such as low interface matching efficiency, high connection complexity of on-chip network architectures, inability to uniformly process diverse standard interfaces, insufficient visualization of interface connection status, and difficulties in coordinating user-defined rules and automatic matching. Summary of the Invention

[0009] In view of the above problems, the purpose of the present invention is to provide an on-chip network interface automatic matching method and system based on hierarchical tag driving, aiming to solve the above technical problems.

[0010] The present invention adopts the following technical solutions: On the one hand, the on-chip network interface automatic matching method based on hierarchical tag driving includes the following steps: Step S1: Read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and the Agent module file and all interface signals through syntax parsing; Step S2: Hierarchically tag the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all tag information into a hierarchical structure; Step S3: If the user provides a custom configuration file, obtain the custom connection relationship between interfaces according to the configuration file; Step S4: Perform automatic matching using a multi-dimensional interface matching algorithm according to the tag information to obtain the automatic matching connection relationship between interfaces, where the priority of the custom connection relationship is higher than that of the automatic matching connection relationship; finally, merge the custom connection relationship and the automatic matching connection relationship to form a complete connection relationship table; Step S5: Generate the complete top-level Verilog code according to the connection relationship table.

[0011] Further, the method further includes the following steps: Step S6: Display the interface status in a hierarchical and collapsible visual tree view, and perform filtering, grouping, or highlighting according to operation instructions.

[0012] On the other hand, the on-chip network interface automatic matching system based on hierarchical tag driving includes: A parsing unit, which is used to read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and the Agent module file and all interface signals through syntax parsing; A hierarchical tagging unit, which is used to hierarchically tag the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all the tag information into a hierarchical structure; A user-defined processing unit, which is used to obtain the user-defined connection relationship between interfaces according to the configuration file if the user provides a custom configuration file; An automatic matching unit, which is used to perform automatic matching according to the tag information by using a multi-dimensional interface matching algorithm to obtain the automatic matching connection relationship between interfaces, where the priority of the user-defined connection relationship is higher than that of the automatic matching connection relationship; finally, the user-defined connection relationship and the automatic matching connection relationship are merged to form a complete connection relationship table; An integrated generation unit, which is used to generate the complete top-level Verilog code according to the connection relationship table.

[0013] Furthermore, the system further includes: A GUI unit, which is used to display the interface status in a hierarchical and collapsible visual tree view, and perform filtering, grouping or highlighting according to operation instructions The beneficial effects of the present invention are as follows: The present invention provides a method and system for automatically matching on-chip network interfaces based on hierarchical tag driving. The technical solution of the present invention is specifically aimed at the design of large and complex chips centered on NoC. By systematically analyzing the structural information contained in the signal naming rules, efficient and accurate automatic signal connection is realized, and a hierarchical visual interface is provided to help users quickly locate and solve connection problems.

[0014] Specifically: First, the present invention proposes a multi-dimensional interface matching algorithm based on the characteristics of the NoC architecture, which significantly improves the connection accuracy through standardized naming rules and hierarchical tag structures; secondly, a flexible user-defined connection rule is designed, and a clear priority mechanism is established to ensure the coordinated work of automatic matching and user-defined specified connections; at the same time, a hierarchical visual expression is constructed to intuitively display the connection status from modules to signals in a multi-level folding form, and the success / partial success / failure status is distinguished by color marking; in addition, a multi-mode operation engine supporting command line and graphical interface is developed, and different development environment requirements are adapted through a unified backend processing logic.

[0015] The technology of the present invention breaks through the generality limitation of traditional automatic wiring tools, provides a professional solution for the characteristics of the NoC architecture, and effectively solves the core problems such as low interface matching efficiency, high error rate, and difficult debugging in complex chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flowchart of an automatic matching method for on-chip network interfaces based on hierarchical tag driving provided by the first embodiment of the present invention; Figure 2 is a detailed flowchart of step S2; Figure 3 is a detailed flowchart of step S3; Figure 4 is a detailed flowchart of step S4; Figure 5 is a detailed flowchart of step S5; Figure 6 is an example diagram of a display interface; Figure 7 is a schematic block diagram of an automatic matching system for on-chip network interfaces based on hierarchical tag driving provided by the second embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] The present invention provides an automatic matching method and system for on-chip network interfaces based on hierarchical tag driving, which fully utilizes the characteristic of modern chips to build interconnections centered around NoC. Based on the automatic analysis of NoC module interfaces, hierarchical tags are extracted, the standard interface connection relationships between NoC and all Agent modules are identified, and matching connections are automatically established. Traditional interface matching methods usually rely on the input of a connection relationship file predefined by the user without considering the specific requirements of modern chip design. In contrast, the present invention utilizes the characteristics of NoC, without the need for user predefinition, only the input of code files is required to automatically complete the connection of all standard interfaces. Moreover, the user can obtain the connected top-level file without any intervention. Through a graphical interface optimized for NoC characteristics, the user can quickly discover unconnected non-standard interface signals among thousands of connections. The present invention also designs a user-defined connection function. When there are unconnected non-standard interface signals, it supports importing user-defined connection configurations to complete the automatic connection of the remaining non-standard signals. In order to illustrate the technical solutions described in the present invention, the following will be described through specific embodiments.

[0019] Embodiment 1: As Figure 1 shown, this embodiment provides an on-chip network interface automatic matching method based on hierarchical marking drive, including the following steps: Step S1: Read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and the Agent module file and all interface signals through syntax parsing.

[0020] First, input all the Verilog files of the modules to be connected, including the NoC module file and the Agent module file, or specify the directory containing these files. The user can specify the input file or directory through command-line parameters or a graphical interface. Then use the Verilog parser to read and parse all input files and extract key information.

[0021] First, read the Verilog file of the NoC module, and extract the NoC module definition and all port signals through syntax parsing, including information such as signal name, direction (input / output), and bit width. At the same time, similar to the processing of the NoC module, read the Verilog files of each Agent module and extract all interface signals.

[0022] Step S2: Hierarchically mark the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all the marking information into a hierarchical structure.

[0023] In this step, apply hierarchical marking to the extracted interface signals, identify and mark the standard interfaces, and mark and classify all interface signals. As Figure 2 shown, the specific process of hierarchical marking is as follows: S21: For each interface signal of the NoC module, identify the standard interface type to which the interface signal belongs by analyzing the keywords and structural features in the signal name.

[0024] For the NoC module, in this step, each interface signal is identified by naming to identify the standard interface type to which it belongs. The interface signal naming has its naming rules. In this embodiment, specifically analyze the keywords and structural features in the signal name to judge the standard interface type to which the signal belongs, such as ACE (AXI Coherency Extensions), AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), etc. ACE, AXI, AHB, and APB are all on-chip bus protocols launched by ARM to achieve high-speed data transmission and communication between different modules inside the chip.

[0025] S22. Extract the target module name and interface sequence number of the target Agent module included in the signal name, and extract the channel and specific signal type to which the interface signal belongs.

[0026] For example, extract "ddrc" as the target module name from "ddrc_0_aw_ready", indicating that this signal needs to be connected to the DDR controller module. Extract "0" as the interface sequence number from "ddrc_0_aw_ready", indicating that this is the first group of interfaces.

[0027] For example, for the AXI interface, extract the channel information (such as the AXI interface has five independent channels, namely the read address channel, read data channel, write address channel, write data channel, and write response channel) and signal types (such as valid signal VALID, ready signal READY, data signal DATA, etc. The VALID and READY signals together constitute the handshake signal, which is used for synchronization and coordination between the master and slave devices to ensure the accuracy and stability of data transmission).

[0028] For interfaces such as AHB and APB, extract the corresponding signal types as well.

[0029] S23. Create multi-level tags for each interface signal, including interface type, target module name, interface sequence number, channel, and signal type.

[0030] Here, based on the information extracted in the previous steps, create tags for each signal that include multiple dimensions such as the target module name, interface type, interface sequence number, channel, and signal type.

[0031] S24. For each interface signal of the Agent module, identify the standard interface type to which the interface signal belongs, extract the interface sequence number included in the signal name, and create corresponding multi-level tags, including interface type and interface sequence number.

[0032] Similarly, identify the interface signals of the Agent module according to similar naming rules. Different from the NoC module, the signal naming of the Agent module usually does not include the target module name, but focuses on the interface sequence number and interface type. Then create corresponding multi-level tags for each interface signal of the Agent module.

[0033] S25. Integrate and organize all the tag information of the NoC module and the Agent module into a tree-like hierarchical structure.

[0034] In this step, integrate and organize all the tag information of the NoC module and the Agent module into a tree-like hierarchical structure for subsequent matching operations.

[0035] Step S3: If the user provides a custom configuration file, obtain the custom connection relationships between interfaces according to the configuration file.

[0036] This step is for custom matching, mainly for non-standard signal connection relationships that need to be intervened and cannot be automatically matched. If the user provides custom configuration files for custom connections, apply the rules of these configuration files and give priority to processing the connection rules specified by the user through the configuration files. The priority of custom matching is higher than that of automatic matching.

[0037] As Figure 3 shown, the specific process of step S3 is as follows: S31: Parse the custom configuration file provided by the user, and extract each connection rule from it, including the source module, source signal, target module, and target signal.

[0038] For example, it can read the Excel sheet or other format of configuration file provided by the user, obtain the user-defined connection relationships, and then extract each connection rule from the configuration file, including information such as the source module, source signal, target module, and target signal.

[0039] S32: Convert the extracted connection rules into custom connection relationships compatible with the automatically matched connection relationships.

[0040] This step converts the extracted connection rules into an internal representation form compatible with automatic matching. It should be noted that before the automatic matching algorithm, these custom connections are applied first, and the connection rules defined by the user are processed preferentially to ensure that these connections are established according to the user's intention. Moreover, the interface signals that have been connected through custom rules are marked to avoid their influence on the subsequent automatic matching process. When performing automatic matching, it will check whether the interface signal has been connected by custom rules. If so, the signal will be skipped.

[0041] Step S4: Adopt a multi-dimensional interface matching algorithm for automatic matching according to the marking information to obtain the automatically matched connection relationships between interfaces, where the priority of the custom connection relationships is higher than that of the automatically matched connection relationships; finally, merge the custom connection relationships and the automatically matched connection relationships to form a complete connection relationship table.

[0042] Based on the above hierarchical marking, this step adopts a multi-dimensional interface matching algorithm for automatic matching, comprehensively considering information such as module names, interface types, and interface numbers, and realizes high-precision interface matching. As Figure 4 shown, the specific process is as follows: S41: Group all the marking information of the NoC modules according to the target module names to obtain each target module group.

[0043] S42. For each target module group, further group them according to the interface type and interface serial number.

[0044] S43. For each target module group, search for the module with the same name as the target module name in the parsed Agent module, and select the corresponding interface type and interface serial number.

[0045] For the above automatic matching process, first group all the marking information of the NoC module by the target module name to facilitate subsequent matching for specific modules. Within each target module group, subdivide the signals according to the interface type and interface serial number to form a more refined grouping. Then search for the module with the same name in the Agent module and select the matching interface type and interface serial number.

[0046] S44. Conduct a preliminary two-way signal matching between the NoC module interface signals and the Agent module signals, then perform an exact match according to the function of the signals in the interface, and finally verify whether the signal bit widths of both sides of the match are consistent. If they are inconsistent, mark them as potential problems.

[0047] Finally, match the interface signals in the selected NoC interface group and Agent interface group. First, conduct a preliminary match according to the signal direction (the input of the NoC module corresponds to the output of the Agent module, and vice versa), then perform an exact match according to the function of the interface signals in the interface, and finally verify whether the bit widths of the matching signals are consistent. If they are inconsistent, mark them as potential problems.

[0048] S45. Establish a connection relationship for the successfully matched interface signal pairs and update the connection status, that is, automatically match the connection relationship, and record the signals that have not been successfully matched for subsequent processing or reminder.

[0049] Record each pair of successfully matched signals and update their connection status to prepare for subsequent code generation. For signals for which no match is found, they will be recorded and displayed in the graphical interface for the user to further process.

[0050] It should be noted that the priority of the custom connection relationship is higher than that of the automatic matching connection relationship. First, process the custom connection relationship of the custom connection rules and mark the signals of the custom connection relationship. When performing automatic matching, skip the signals with the marked custom connection relationship.

[0051] Therefore, this automatic matching method combines multiple dimensions (module name, interface type, interface serial number, signal function, etc.) for comprehensive judgment, rather than simple string matching, which greatly improves the accuracy of matching.

[0052] S46. Merge the custom connection relationship and the automatic matching connection relationship to generate the final complete connection relationship table.

[0053] Finally, the custom connection relationship and the automatically matched connection relationship are merged to form a complete connection relationship table, preparing for subsequent code generation. Therefore, through this mechanism, designers are allowed to flexibly handle special cases, such as signals with non-standard names, interfaces that require special processing, or connection methods different from automatic matching.

[0054] Step S5: Generate the complete top-level Verilog code according to the connection relationship table.

[0055] Based on the previously determined connection relationship, this step can automatically generate the complete top-level Verilog code, including module instantiation, signal declarations, and connection statements. As Figure 5 shown, the specific process of step S5 is as follows: S51: Generate the top-level module declaration: Create the Verilog code framework for the top-level module, including the module name and all required input / output interfaces.

[0056] S52: Generate internal wire declarations: Generate wire declarations with corresponding widths for each pair of matched signal pairs, and at the same time process unconnected signals according to the preset, such as floating or connecting to default values. In Verilog, the wire type is generally used to connect signals in combinational logic circuits, such as connections between modules and input / outputs of gate-level circuits.

[0057] S53: Generate the instantiation code for the NoC module: Create the instantiation statement for the NoC module, including the module name, instance name, and all interface-to-wire mapping relationships.

[0058] S54: Generate the instantiation code for each Agent module: Create the instantiation statement for each Agent module, also including the module name, instance name, and all interface-to-wire mapping relationships.

[0059] S55: Write the generated complete top-level Verilog code to the specified output file.

[0060] The code generated in this way has good readability and structure, facilitating subsequent manual adjustment or modification. For signals that are not successfully connected, clear comments and default processing methods are provided to avoid leaving potential design problems. The connection results are displayed through a graphical interface, facilitating user verification and debugging. And it supports users to adjust the configuration or manually modify the connection relationship according to the verification results. The finally determined top-level code is output to the specified file, completing the entire automatic wiring process.

[0061] Step S6: Display the interface status in a hierarchical and collapsible visual tree view, and perform filtering, grouping, or highlighting according to operation instructions.

[0062] To help designers visually view and verify the connection results, the steps of this embodiment provide a hierarchical folding visualization interface.

[0063] As Figure 6 shown in an interface example, the interface tree of the NoC module is displayed on the left side of the interface, organized hierarchically by target module name, interface type, and interface serial number, facilitating users to quickly locate specific interfaces. The interface tree of the Agent module is displayed on the right side of the interface, and users can choose to display a single or multiple Agent modules, facilitating comparison and analysis. Statistical information on the connection status is displayed for each node, showing the statistical information on the connection status, such as "10 / 12 signals connected", allowing users to clearly understand the connection completion at a glance.

[0064] And the connection status is displayed using color coding. For example, green indicates that all connections are successful, yellow indicates that some connections are successful, and red indicates that all connections fail, visually reflecting the connection status through colors; node expansion / folding is supported, allowing users to expand or fold any node, facilitating quick navigation between different levels, especially suitable for handling a large number of signals in large-scale designs. In addition, a global filtering function is provided, allowing users to only display unconnected signals and quickly locate problem areas. A filtering function based on conditions such as module name and interface type is also provided to help users focus on specific modules or interfaces.

[0065] This visual design greatly simplifies the connection verification process, enabling designers to quickly locate connection problems and improve debugging efficiency. The entire process supports both command-line mode and graphical interface mode, adapting to different usage scenarios and user preferences. The command-line mode is suitable for integration into automation scripts, while the graphical interface mode provides more intuitive operations and feedback, especially suitable for interactive design and debugging.

[0066] The method of this embodiment of the invention realizes the complete process from inputting a Verilog file to generating top-level wiring code, solving the top-level wiring problem in large-scale system chip design.

[0067] Embodiment 2: This embodiment provides an on-chip network interface automatic matching system based on hierarchical marking driving, as Figure 7 shown, the system includes: A parsing unit 100, configured to separately read the NoC module file and the Agent module file, and extract the definitions of the NoC module and the Agent module file and all interface signals through syntax parsing; A hierarchical marking unit 200, configured to hierarchically mark the NoC module interface signals and the Agent module interface signals according to naming rules, and organize all marking information into a hierarchical structure; A user-defined processing unit 300, which is used to obtain the user-defined connection relationship between interfaces according to the configuration file if the user provides a custom configuration file; An automatic matching unit 400, which is used to perform automatic matching according to the marking information by using a multi-dimensional interface matching algorithm to obtain the automatic matching connection relationship between interfaces, wherein the priority of the user-defined connection relationship is higher than that of the automatic matching connection relationship; finally, the user-defined connection relationship and the automatic matching connection relationship are merged to form a complete connection relationship table; An integrated generation unit 500, which is used to generate a complete top-level Verilog code according to the connection relationship table.

[0068] Furthermore, the system further includes: A GUI unit 600, which is used to display the interface status in a hierarchical and collapsible visual tree view manner, and perform filtering, grouping, or highlighting according to the operation instructions.

[0069] Each functional unit in this embodiment correspondingly implements steps S1-S6 in Embodiment 1. Each functional unit has clear responsibilities and clear interaction relationships. The parsing unit is responsible for extracting module definitions, port lists, and interface signal information from the Verilog file; the hierarchical marking unit block implements hierarchical marking of interface signals based on naming rules; the user-defined processing unit manages user-defined connection rules; the automatic matching unit executes an automatic matching algorithm according to the marking information to determine the connection relationship between signals; the integrated generation unit generates a complete top-level Verilog code according to the matching result; the GUI unit provides a visual interaction interface, provides a hierarchical tree view to display the interface status, and supports filtering, grouping, and highlighting. These functional units work together to implement the complete process from inputting the Verilog file to generating the top-level wiring code.

[0070] The functional units in this embodiment adopt a modular design, which has good scalability and maintainability while maintaining the core functions. Each unit interacts through clearly defined interfaces, enabling the system to easily add new functions or support new interface types. For example, the system can be extended to support more types of standard bus protocols, or more complex matching algorithms can be added to handle special cases.

[0071] On the one hand, the present invention does not require the user to provide additional input. By utilizing the NoC structured naming rule system, through extracting and matching the multi-dimensional hierarchical tags of "module name + interface type + interface serial number", it identifies the target Agent module, interface type, and interface serial number to which each interface signal is to be connected, and specifically realizes the efficient matching of the full-system interfaces based on the NoC architecture. Compared with the traditional interface identification and matching methods, the present invention is more in line with the actual requirements of large-scale chip design, has stronger pertinence, breaks through the limitations of the traditional general matching method in theory, and significantly improves the matching accuracy and processing efficiency.

[0072] On the other hand, the present invention not only designs an efficient automatic matching algorithm for the automatic connection of standard interface types according to the actual application, but also introduces a user-defined rule priority mechanism. By constructing a complete user-defined rule system, it allows the user to define specific connection relationships through an external configuration file and implement a rule application strategy based on priority during the automatic matching process, effectively solving the problems of special connection requirements and exception handling.

[0073] In summary, the technical solution of the present invention is applicable to all chip designs interconnected based on NoC. Without the need for user intervention, it can automatically match and connect standard interface signals and complete more than 95% of the signal connections at the top layer. The user only needs to intervene in the remaining 5% of the non-standard signal connection relationships to complete the complete top-level file, which will greatly reduce the workload of the user and improve the efficiency of chip design iteration.

[0074] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for automatically matching network-on-chip interfaces based on hierarchical tag driving, characterized in that: The method comprises the following steps: Step S1, read the NoC module file and the Agent module file respectively, and extract the definition of the NoC module and the Agent module file and all interface signals through syntax parsing; Step S2: hierarchically label the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all label information into a hierarchical structure; Step S3: If the user provides a custom configuration file, the custom connection relationship between interfaces is obtained according to the configuration file; Step S4: automatically match the interfaces using a multi-dimensional interface matching algorithm according to the tag information to obtain an automatic matching connection relationship between interfaces, wherein the priority of the custom connection relationship is higher than the priority of the automatic matching connection relationship; finally, merge the custom connection relationship and the automatic matching connection relationship to form a complete connection relationship table; Step S5: Generate a complete top-level Verilog code according to the connection relationship table.

2. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving according to claim 1, characterized in that: The method further comprises the steps of: Step S6: Display the interface status in a hierarchical, folded, and visualized tree view, and filter, group, or highlight according to the operation instructions.

3. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving as claimed in claim 2, characterized in that: The specific process in step S2 is as follows: S21, for each interface signal of the NoC module, identifying the standard interface type to which the interface signal belongs by analyzing the keywords and structural features in the signal name; S22, extracting the target module name and interface serial number of the target Agent module contained in the signal name, and extracting the channel and specific signal type to which the interface signal belongs; S23, creating a multi-level tag for each interface signal, including interface type, target module name, interface serial number, channel and signal type; S24, for each interface signal of the Agent module, identifying the standard interface type to which the interface signal belongs, extracting the interface serial number contained in the signal name, and creating a corresponding multi-level tag including the interface type and the interface serial number; S25, integrating and organizing all the tag information of the NoC module and the Agent module into a tree-like hierarchical structure.

4. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving as claimed in claim 3, characterized in that: The specific process of step S3 is as follows: S31, parsing the custom configuration file provided by the user, and extracting each connection rule therefrom, including a source module, a source signal, a target module, and a target signal; S32. Convert the extracted connection rules into custom connection relationships that are compatible with the automatic matching connection relationship.

5. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving as claimed in claim 4, characterized in that: The specific process in step S4 is as follows: S41, grouping all tag information of the NoC modules according to the target module names to obtain target module groups; S42, further grouping each target module group according to interface type and interface serial number; S43, for each target module group, search for the target module name in the resolved Agent module Modules with the same name, and select the corresponding interface type and interface number; S44, performing a preliminary bidirectional signal match between the NoC module interface signal and the Agent module signal, and then performing an accurate match according to the function of the signal in the interface, and finally verifying whether the bit widths of the signals of the two matching parties are consistent, and if they are inconsistent, marking them as potential problems; S45, establishing a connection relationship for the successfully matched interface signal pair and updating the connection status, that is, automatically matching the connection relationship, and recording the unsuccessfully matched signals for subsequent processing or reminder; wherein the priority of the custom connection relationship is higher than the priority of the automatically matched connection relationship, the custom connection relationship of the custom connection rule is processed first, and the signal of the custom connection relationship is marked, and during automatic matching, the signal of the marked custom connection relationship is skipped; S46. Merge the custom connection relationship and the automatic matching connection relationship to generate a final complete connection relationship table.

6. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving as claimed in claim 5, characterized in that: The specific process of step S5 is as follows: S51, generate top-level module declaration: create a Verilog code framework of the top-level module; S52, generating internal wire declarations: generating wire declarations of corresponding widths for each pair of matched signals, and processing unconnected signals according to presets; S53, generating instantiation code of the NoC module; S54, generating instantiation codes of each Agent module; S55. Write the generated complete top-level Verilog code into a specified output file.

7. An automatic matching system for network-on-chip interfaces based on hierarchical tag driving, characterized in that: The system comprises: A parsing unit, used for reading the NoC module file and the Agent module file respectively, and extracting the definition of the NoC module and the Agent module file and all interface signals through syntax parsing; A hierarchical marking unit is used to hierarchically mark NoC module interface signals and Agent module interface signals according to naming rules, and organize all marking information into a hierarchical structure; A user-defined processing unit, used for obtaining a customized connection relationship between interfaces according to a customized configuration file if the user provides the customized configuration file; The automatic matching unit is used to automatically match according to the tag information using a multi-dimensional interface matching algorithm to obtain an automatic matching connection relationship between interfaces, wherein the priority of the custom connection relationship is higher than the priority of the automatic matching connection relationship; finally, the custom connection relationship and the automatic matching connection relationship are merged to form a complete connection relationship table; An integrated generation unit is used to generate complete top-level Verilog code based on the connection relationship table.

8. The on-chip network interface automatic matching system based on hierarchical tag driving as claimed in claim 7, characterized in that: The system further comprises: GUI unit, used to display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to operation instructions.

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