Built-in self-test system of memory

Abstract

The invention provides a built-in self-test system of a memory, and belongs to the field of integrated circuits. The memory of the present invention comprises: a memory array including a plurality of memory cells for storing data; the controller is electrically connected with the storage array through the multiplexer and is electrically connected with the test machine table through a bus; the built-in self-test system comprises a built-in self-test circuit which is electrically connected with the controller and is electrically connected with the storage array through the multiplexer, and the built-in self-test circuit is used for testing the storage array; the page buffer is electrically connected with the controller and the built-in self-test circuit, and is used for caching the written data when the data is written into the storage array and temporarily storing a test result when the BIST is carried out on the storage array; and the one-time programmable memory is electrically connected with the controller and is used for finally storing the test result. According to the BIST system of the memory, the occupied area of a chip can be reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a built-in self-test system for a memory. Background Art

[0002] During the manufacturing process of a memory, especially a phase change memory (PCM), it is necessary to test the PCM. When testing the PCM, generally data is written into the storage cells of the PCM, and after a period of time, the data is read out from the storage cells of the PCM, and then the written data is compared with the read data to determine which storage cells in the PCM are abnormal.

[0003] Built-In-SelfTest (BIST) is a common testing method. Figure 3 The BIST system of a memory in the prior art is shown. As Figure 3 shown, the memory 900 in the prior art includes: a storage array 91, a controller 92, a MUX (Multiplexer) 93, a BIST circuit 96, a page buffer 97, an eFuse (one-time programmable memory) 98, and a storage circuit 99. When testing, the test station 95 sends a test command to the controller 92 through the bus 94, the controller 92 controls the BIST circuit 96 to test the storage array 91, after the test is completed, the BIST circuit 96 temporarily stores the test result in the storage circuit 99, then the controller 92 sends the test result temporarily stored in the storage circuit 99 to the test station 95 through the bus 94, finally the test station 95 sends the test result to the controller 92 through the bus 94, and the controller 92 writes the test result into the one-time programmable memory 98.

[0004] Among them, the storage circuit 99 is usually a register or an SRAM (Static Random Access Memory), and both the register and the SRAM occupy a relatively large chip area and consume a large amount of power, which is not conducive to the miniaturization of the chip and will also increase the test cost of the chip. Therefore, there is an urgent need in the industry for a BIST system for a memory that occupies a small chip area and has low power consumption. Summary of the Invention

[0005] The present invention aims to provide a BIST system for a memory and a testing method thereof that occupy a small area and have low power consumption.

[0006] The present invention discloses a BIST system for a memory. The memory includes: a storage array including a plurality of storage units for storing data; a controller electrically connected to the storage array through a multiplexer and electrically connected to a test station through a bus. The built-in self-test system includes: a built-in self-test circuit electrically connected to the controller and electrically connected to the storage array through a multiplexer, where the built-in self-test circuit is used to test the storage array; a page buffer electrically connected to the controller and the built-in self-test circuit, used to cache the written data when writing data to the storage array, and used to temporarily store the test result after the test of the storage array ends; a one-time programmable memory electrically connected to the controller, used to finally store the test result. When performing built-in self-test, the test station sends a test command to the controller through the bus, the controller controls the built-in self-test circuit to test the storage array. After the test is completed, the built-in self-test circuit temporarily stores the test result in the page buffer, then the controller sends the test result temporarily stored in the page buffer to the test station through the bus, and finally the test station sends the test result to the controller through the bus, and the controller writes the test result into the one-time programmable memory.

[0007] Through the BIST system and its test method for the memory of the present invention, the chip occupied area can be reduced, the power consumption can be lowered, which is beneficial to the miniaturization of the chip, and also the test cost of the chip can be reduced. Description of the Drawings

[0008] Figure 1 is a schematic block diagram of the BIST system for the memory of the present invention.

[0009] Figure 2 is a flowchart of the test method for the BIST system of the memory of the present invention.

[0010] Figure 3 is a schematic block diagram of the BIST system for the memory of the prior art.

[0011] Marking Description

[0012] 100, 900 Memory

[0013] 1, 91 Storage Array

[0014] 2, 92 Controller

[0015] 3, 93 MUX

[0016] 4, 94 Bus

[0017] 5, 95 Test Station

[0018] 6, 96 BIST Circuit

[0019] 7, 97 Page Buffer

[0020] 8, 98 One-Time Programmable Memory

[0021] 99 Storage Circuit Detailed Embodiment

[0022] The BIST system and its testing method of the memory of the present invention will be specifically described below with reference to the accompanying drawings. Figure 1 is a schematic block diagram of the BIST system of the memory of the present invention. As Figure 1 shown, the memory 100 of the present invention includes: a storage array 1, which includes a plurality of storage units for storing data; a controller 2, which is electrically connected to the storage array 1 through a MUX 3 and is electrically connected to a test station 5 through a bus 4. The BIST system includes: a BIST circuit 6, which is electrically connected to the controller 2 and is electrically connected to the storage array 1 through the MUX 3. The BIST circuit 6 is used to test the storage array 1; a page buffer 7, which is electrically connected to the controller 2 and the BIST circuit 6, and is used to cache the data to be written when writing data to the storage array 1, and is also used to temporarily store the test results when performing BIST on the storage array 1; a one-time programmable memory (eFuse) 8, which is electrically connected to the controller 2 and is used to finally store the test results.

[0023] When performing BIST, the test station 5 sends a test command to the controller 2 through the bus 4. The controller 2 controls the BIST circuit 6 to test the storage array 1. After the test is completed, the BIST circuit 6 temporarily stores the test results in the page buffer 7. Then the controller 2 sends the test results temporarily stored in the page buffer 7 to the test station 5 through the bus 4. Finally, the test station 5 sends the test results to the controller 2 through the bus 4, and the controller 2 writes the test results into the one-time programmable memory 8.

[0024] In the memories of the prior art, the function of the page buffer is usually to cache the data to be written when writing data to the storage array. Specifically, when writing data to the storage array, the data to be written is first transmitted to the controller through the bus, and then the controller writes these data into the storage array. However, the speed of sending data by the bus is usually greater than the speed of writing data. To solve this problem, usually the bus first sends the data to the controller, and the controller then temporarily stores the data in the page buffer. After all the data is sent, the controller retrieves these data from the page buffer and then writes them into the storage array.

[0025] That is to say, in the memory of the prior art, the page buffer is only used when writing data to the storage array and is not used during BIST. However, in the present invention, the page buffer 7 is reused, and during the BIST process, the page buffer 7 is used to temporarily store the test results. Therefore, there is no need to set up a separate storage circuit to temporarily store the test results. This saves space, thereby reducing the chip occupation area of the entire memory, and also reduces power consumption. Therefore, it is beneficial to the miniaturization of the chip and can also reduce the test cost of the chip.

[0026] In addition, the page buffer 7 is a volatile memory, and the data temporarily stored in the page buffer 7 will not be retained after power-off. Therefore, after the BIST is completed, there will be no data stored in the page buffer 7. Therefore, after the BIST is completed, when the memory 100 is put into use and data needs to be written to the storage array 1, it will not affect the data writing.

[0027] Next, the test method of the BIST system of the memory of the present invention will be described. Figure 2 is the flowchart of the test method of the BIST system of the memory of the present invention. As Figure 2 shown, the test method of the BIST system of the memory of the present invention includes:

[0028] S001, page buffer test step. The test machine 5 sends a page buffer test command to the controller 2 through the bus 4, and the controller 2 controls the BIST circuit 6 to test the page buffer 7 to confirm whether the page buffer 7 is damaged. If so, it is determined that the memory 100 cannot be used. If not, proceed to the next step.

[0029] Among them, any commonly used method in the art can be used to test the page buffer 7, which will not be elaborated here. In the test method of the BIST system of the memory of the present invention, the page buffer 7 is used to store the test results in the subsequent steps of testing the storage array 1. Therefore, if the page buffer 7 itself is damaged, then the subsequent tests cannot be carried out, and the memory 100 cannot be used.

[0030] S002, storage array test step. The test machine 5 sends a storage array test command to the controller 2 through the bus 4, and the controller 2 controls the BIST circuit 6 to test the storage array 1.

[0031] In this embodiment, when performing BIST, the MUX 3 outputs the signal from the BIST circuit 6, so that the BIST circuit 6 tests the memory array 1. The BIST circuit 6 writes data to each memory cell in the memory array 1. After a period of time, the data is read out from these memory cells, and then it is compared whether the written data is the same as the read data, so as to determine whether the memory cell is abnormal. Any commonly used BIST method in the art can be used for testing, which will not be elaborated here.

[0032] S003, determination step. The BIST circuit 6 determines whether the memory array 1 is repairable. If there are too many abnormal memory cells in the memory array 1 and they cannot be replaced by redundant memory cells, it is determined to be irreparable and the memory 100 cannot be used. Otherwise, it is determined to be repairable and the next step is performed.

[0033] S004, temporary storage step. After the test is completed, the BIST circuit 6 temporarily stores the test results in the page buffer 7. In this embodiment, the test results include: data such as the addresses of abnormal memory cells and the enable signals of redundant memory cells replacing the abnormal memory cells.

[0034] S005, writing step. The controller 2 sends the test results temporarily stored in the page buffer 7 to the test machine 5 through the bus 4. The test machine 5 sends the test results to the controller 2 through the bus 4, and the controller 2 writes the test results into the one-time programmable memory 8.

[0035] After BIST is completed, when the memory 100 is put into use and data needs to be written into the memory array 1, first, after the chip is powered on, the controller 2 reads the previously stored test results (data such as the addresses of abnormal memory cells and the enable signals of redundant memory cells replacing the abnormal memory cells) from the one-time programmable memory 8 and loads them into the internal register of the controller 2. Then, the data to be written and the starting address of the memory cell are sent to the controller 2 through the bus 4. The controller 2 first temporarily stores the data to be written in the page buffer 7, and then makes the MUX 3 output the signal from the controller 2. The controller 2 then retrieves the data to be written from the page buffer 7 and writes it into the corresponding memory cell in the memory array 1. Here, the bus 4 only sends the starting address to the controller 2, and other addresses are generated by the controller 2. The generated addresses are sent to the comparator in the controller 2, and the comparator compares the generated addresses with the addresses of abnormal memory cells loaded in the internal register. If the generated address is exactly the address of an abnormal memory cell, the controller 2 retrieves the enable signal of the redundant memory cell replacing the abnormal memory cell from the internal register, pulls up the enable signal, and writes the data to be written into the redundant memory cell.

[0036] Through the BIST system and its test method of the memory of the present invention, the chip occupation area of the memory can be reduced, and the power consumption can be lowered. Therefore, it is beneficial to the miniaturization of the chip, and the test cost of the chip can also be reduced.

[0037] Although the present invention has been disclosed above in the form of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A memory built-in self-test system, characterized in that: The memory (100) comprises: A storage array (1) comprising a plurality of storage cells for storing data; A controller (2) electrically connected to the storage array (1) via a multiplexer (3) and electrically connected to a test machine (5) via a bus (4); The built-in self-test system comprises: A built-in self-test circuit (6) is electrically connected to the controller (2) and is electrically connected to the storage array (1) via a multiplexer (3), wherein the built-in self-test circuit (6) is used to test the storage array (1); A page buffer (7) electrically connected to the controller (2) and the built-in self-test circuit (6), used for caching the written data when writing data to the storage array (1), and for temporarily storing the test results when performing a built-in self-test on the storage array (1); A one-time programmable memory (8), which is electrically connected to the controller (2) and is used to finally store the test result; When performing a built-in self-test, the test machine (5) sends a test command to the controller (2) via the bus (4), and the controller (2) controls the built-in self-test circuit (6) to test the storage array (1). After the test is completed, the built-in self-test circuit (6) temporarily stores the test result in the page buffer (7), and then the controller (2) sends the test result temporarily stored in the page buffer (7) to the test machine (5) via the bus (4). Finally, the test machine (5) sends the test result to the controller (2) via the bus (4), and the controller (2) writes the test result into the one-time programmable memory (8).

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