Power conversion system parallel architecture and synchronous control method thereof

Abstract

The invention provides a power conversion system parallel architecture and a synchronous control method thereof. In a plurality of corresponding PCS controllers of a parallel architecture of a power conversion system (PCS), when a target PCS controller in the PCS controllers sends a synchronization signal on a synchronization signal busbar as soon as possible to obtain a master control right, the synchronization signal sent by the target PCS controller obtaining the master control right is used as a system synchronization signal; the other PCS controllers which do not obtain the master control right refer to the system synchronization signal to synchronize with the system synchronization signal.

Description

Technical Field

[0001] The present invention relates to a parallel architecture of a power conversion system (PCS) and a synchronization control method therefor. Background Art

[0002] To meet future challenges such as energy security and net-zero carbon emissions, countries around the world are actively involved in the research and development and application of renewable energy. Accordingly, relevant regions have set goals for 2025, including achieving a renewable energy installation capacity of 27 GW and a renewable energy power generation ratio of 20%.

[0003] However, with the popularization of renewable energy, the impact of intermittent power generation on the power grid has gradually become prominent, and traditional power systems are facing challenges in stability. To address this situation, power companies in various countries need to introduce emerging technology resources to ensure stable power supply to the power grid.

[0004] Battery energy storage is one of the most widely used energy storage systems at present. By controlling the charging and discharging of energy storage batteries through a power conversion system (PCS), the goal of grid stability is achieved. To improve the application flexibility of the energy storage system, the mainstream products in the market are PCSs that can be expanded by multi-machine parallel connection.

[0005] In addition, in response to the field of large-power renewable energy grid connection, multiple PCSs may exist simultaneously in the same area. In the prior art, modular stacked power conversion technology is used for module series-parallel combination, which can increase the application flexibility of system voltage and capacity and quickly be compatible with renewable energy systems with different voltage levels and different application requirements.

[0006] However, when multiple PCSs are connected in parallel, each PCS performs its own PWM output and phase-locking operation with respect to the mains phase, which may lead to errors in the output signals, and further cause problems such as circulating current, oscillation, and control instability.

[0007] To solve the above problems, the present invention proposes a phase and pulse synchronization control method for multiple power conversion systems connected in parallel. The present invention can synchronize the pulse width modulation (PWM) signals of multiple PCSs with the (AC) mains signal, so that the output of each PCS is synchronized, thereby improving the stability of the system. Summary of the Invention

[0008] The present invention relates to a parallel architecture of a power conversion system (PCS). For an architecture in which multiple PCSs operate in parallel, a phase and pulse synchronization control method is proposed, which can make the pulse width modulation (PWM) signals provided by multiple PCSs synchronized with the AC mains signal to ensure the synchronous operation of the outputs of each PCS. The present invention solves problems such as circulating current and interference that may occur in the system, and significantly improves the stability of the overall system.

[0009] According to a first aspect of the present invention, a parallel architecture of a power conversion system (PCS) is proposed, including: multiple PCSs, which are mutually coupled through a synchronization signal bus to achieve synchronization with each other, and each of these PCSs is further coupled to an AC mains and a DC power supply. Each of these PCSs includes a PCS controller. Among these PCS controllers, when a target PCS controller among these PCS controllers issues a synchronization signal on the synchronization signal bus fastest to obtain a master control right, the synchronization signal issued by the target PCS controller that obtains the master control right is regarded as a system synchronization signal, and other PCS controllers that do not obtain the master control right refer to the system synchronization signal to synchronize with the system synchronization signal.

[0010] According to a second aspect of the present invention, a synchronization control method for a parallel architecture of a power conversion system (PCS) is proposed. The parallel architecture of the power conversion system (PCS) includes: multiple PCSs, which are mutually coupled through a synchronization signal bus to achieve synchronization with each other, and each of these PCSs includes a PCS controller to execute the synchronization control method: Among these PCS controllers, when a target PCS controller among these PCS controllers issues a synchronization signal on the synchronization signal bus fastest to obtain a master control right, the synchronization signal issued by the target PCS controller that obtains the master control right is regarded as a system synchronization signal, and other PCS controllers that do not obtain the master control right refer to the system synchronization signal to synchronize with the system synchronization signal.

[0011] In order to further understand the above and other aspects of the present invention, specific embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0012] Figure 1 It is a diagram of the PCS parallel architecture according to an embodiment of the present invention.

[0013] Figure 2 It is a functional block diagram of a PCS according to an embodiment of the present invention.

[0014] Figure 3 It is a schematic diagram of realizing synchronization control through a two-wire synchronization signal bus according to an embodiment of the present invention.

[0015] Figure 4 The operation process of the multi-module synchronization control module according to an embodiment of the present invention.

[0016] Figure 5 The flow chart showing the synchronization judgment by the synchronization signal control unit according to an embodiment of the present invention.

[0017] Figure 6 The circuit embodiment of the synchronization control unit according to an embodiment of the present invention.

[0018] Figure 7 The schematic diagram showing the synchronization control achieved through a single-wire synchronization signal bus according to an embodiment of the present invention.

[0019] Figure 8 The operation process of pulse synchronization and phase synchronization of a single synchronization signal bus according to an embodiment of the present invention.

[0020] Figure 9 The circuit schematic diagram of the synchronization signal control and analysis unit according to an embodiment of the present invention.

[0021] In the above drawings, the meanings of the reference numerals are as follows:

[0022] 100: Parallel architecture of the power conversion system (PCS)

[0023] 110: Power conversion system (PCS)

[0024] 120: Mains power

[0025] 130: DC power supply

[0026] 210: Power unit

[0027] 220: PCS controller

[0028] 230: Voltage and current detection unit

[0029] 240: AC signal interception unit

[0030] 221: Multi-module synchronization control module

[0031] 270: Synchronization signal bus

[0032] 280: Power line

[0033] 310: Synchronization signal control unit

[0034] 320: Pulse (PWM) synchronization signal generator

[0035] 330: Mains phase synchronization signal generator

[0036] 360: Phase synchronization signal bus

[0037] 370: Pulse Synchronization Signal Bus

[0038] 410 - 460: Steps

[0039] 510 - 560: Steps

[0040] 610 and 620: Buffers

[0041] 630 and 640: Inverters

[0042] SW1 and SW2: Switches

[0043] R1 and R2: Resistors

[0044] 710: Synchronization Signal Control and Analysis Unit

[0045] 720: Pulse Synchronization Signal Generator

[0046] 730: Mains Phase Synchronization Signal Generator

[0047] 750: Synchronization Signal Bus

[0048] 810 - 870: Steps

[0049] 910: OR Logic Gate

[0050] 920: Synchronization Signal Analysis Unit

[0051] 931 and 932: Inverters

[0052] SW91 - SW94: Switches

[0053] R91 - R94: Resistors

[0054] 921 and 922: Counting Comparators Detailed Implementation Manner

[0055] The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the explanations of these terms shall prevail according to the explanations or definitions in this specification. Each embodiment of the present invention has one or more technical features. On the premise of possible implementation, those of ordinary skill in the art can selectively implement some or all of the technical features in any one embodiment, or selectively combine some or all of the technical features in these embodiments.

[0056] The present invention provides an architecture for parallel operation of multiple power conversion systems (PCS) and related synchronization control methods, and solves errors such as phase and / or pulse asynchronization that may occur between the respective PWM output signals of these PCSs and the AC mains signal. Phase and / or pulse asynchronization errors may cause problems such as system circulating current, oscillation, and uncontrollability.

[0057] In the PCS parallel architecture disclosed in an embodiment of the present invention, phase and pulse synchronization control can be performed. In this PCS parallel architecture, the multi-module synchronization control module in the PCS controllers of these parallel PCSs can send phase / pulse synchronization signals on the synchronization signal bus, and lock the PCS that emits the phase / pulse synchronization signal earliest or fastest as the phase / pulse synchronization reference source for other PCSs. In the embodiments of the present invention, the systems, modules, and units exemplified are all physical circuits and cooperate with firmware and software programs to achieve synchronization control.

[0058] Figure 1 It is a PCS parallel architecture according to an embodiment of the present invention. The PCS parallel architecture 100 includes multiple parallel PCSs 110, and these parallel PCSs 110 are also coupled to the mains 120. The mains 120 is an AC mains. With this configuration, the PCS parallel architecture 100 uses multiple sets of PCSs 110 to control the energy absorption and output of the power grid.

[0059] Figure 2 It is a functional block diagram of a PCS according to an embodiment of the present invention. The PCS 110 is also coupled to a DC power supply 130, where the DC power supply 130 can also be a storage battery. These PCSs 110 are electrically coupled to each other and in parallel through a synchronization signal bus 270. In addition, these PCSs 110 are also coupled to the mains 120 (or an AC electronic device) through a power line 280.

[0060] The PCS 110 includes: a power unit 210, a PCS controller 220, a voltage and current detection unit 230, and an AC signal extraction unit 240. The PCS controller 220 includes a multi-module synchronization control module 221 and other components (not shown).

[0061] The power unit 210 includes semiconductor switching elements.

[0062] The PCS controller 220 can be implemented by a hardware circuit in cooperation with a software program. For example, but not limited to, the PCS controller 220 can be implemented using a field programmable gate array (FPGA) or a microcontroller (MCU).

[0063] The PCS controller 220 extracts parameters from the voltage and current detection unit 230, and then captures the frequency signal of the AC mains 120 through the AC signal interception unit 240 to achieve synchronous control of the phase with the mains.

[0064] Next, the PCS controller 220 compares and controls the preset reference current according to the current signal intercepted by the voltage and current detection unit 230, and finally provides a pulse signal to the power unit 210 composed of semiconductor switching elements to achieve AC / DC energy conversion and power regulation.

[0065] However, in the prior art, when multiple PCSs operate in parallel, there may be phase / pulse asynchronization errors between the respective PWM output signals of the multiple PCSs and the AC mains, resulting in phenomena such as circulating current, oscillation, and even uncontrollability in the system.

[0066] Therefore, in an embodiment of the present invention, to ensure the stability of the PCS parallel architecture 100, the PCS parallel architecture 100 connects all the PCSs 110 together through the synchronization signal busbar 270, and performs phase and pulse synchronization control through the multi-module synchronization control module 221 of the PCS controller 220 to keep the outputs of all the PCSs 110 synchronized.

[0067] In an embodiment of the present invention, the synchronous control can be achieved through a two-wire synchronization signal busbar. In another embodiment of the present invention, the synchronous control can be achieved through a single-wire synchronization signal busbar. The following will be described separately.

[0068] Figure 3 It is a schematic diagram of realizing synchronous control through a two-wire synchronization signal busbar according to an embodiment of the present invention. The multi-module synchronization control module 221 of an embodiment of the present invention includes: a synchronization signal control unit 310, a pulse (PWM) synchronization signal generator 320, and a mains phase synchronization signal generator 330.

[0069] These multi-module synchronization control modules 221 are coupled and communicate with each other through the phase synchronization signal busbar 360 and the pulse synchronization signal busbar 370. That is, the synchronization signal busbar 270 includes the phase synchronization signal busbar 360 and the pulse synchronization signal busbar 370.

[0070] The multi-module synchronization control module 221 is responsible for generating and processing synchronous control signals to achieve phase signal synchronization and pulse signal synchronization between multiple PCSs 110.

[0071] The phase synchronization signal bus 360 and the pulse synchronization signal bus 370 are connected to all multi-module synchronization control modules 221 of all PCS controllers 220. The phase synchronization signal bus 360 and the pulse synchronization signal bus 370 are respectively used to transmit and receive the phase synchronization signal and the pulse synchronization signal to and from each other. The synchronization signal control unit 310, the pulse synchronization signal generator 320, and the mains phase synchronization signal generator 330 of the multi-module synchronization control module 221 are used to transmit / receive the phase synchronization signal and the pulse synchronization signal, and lock the phase synchronization signal and the pulse synchronization signal. The pulse synchronization signal generator 320 is used to calculate the pulse synchronization signal. The mains phase synchronization signal generator 330 is used to calculate the mains phase synchronization signal.

[0072] Figure 4 It is the operation flow of the multi-module synchronization control module according to an embodiment of the present invention.

[0073] As Figure 4 shown, the pulse synchronization signal generator 320 and the mains phase synchronization signal generator 330 of the multi-module synchronization control module 221 respectively calculate the pulse synchronization signal and the phase synchronization signal, as in steps 410 and 420. The synchronization signal control unit 310 determines whether the phase and / or pulse has been preempted by the output of the multi-module synchronization control module 221 of other PCSs 110. If the pulse synchronization signal bus 370 has received and locked the pulse synchronization before the pulse synchronization signal generator 320 of itself outputs the pulse synchronization signal, the synchronization signal control unit 310 determines that the pulse has been synchronized, as in step 430, and ends this operation flow. If no other signal is transmitted to the synchronization signal control unit 310 through the pulse synchronization signal bus 370 and locked before the pulse synchronization signal generator 320 outputs the pulse synchronization signal, the synchronization signal control unit 310 determines that the pulse has not been synchronized. At this time, the synchronization signal control unit 310 locks the pulse synchronization signal generated by itself to become the system pulse synchronization signal as the reference for pulse synchronization, and outputs the pulse synchronization signal generated by itself to the pulse synchronization signal bus 370 (as in step 450), and then ends the process.

[0074] The operating principle of phase synchronization is the same as that of pulse synchronization. If the phase synchronization signal bus 360 has received and locked the phase synchronization before the mains phase synchronization signal generator 330 outputs the phase synchronization signal, the synchronization signal control unit 310 determines that the phase is synchronized (step 440) and ends this operation process. If no other signal is transmitted through the phase synchronization signal bus 360 to the synchronization signal control unit 310 and locked before the mains phase synchronization signal generator 330 outputs the phase synchronization signal, the synchronization signal control unit 310 determines that the phase is not synchronized. At this time, the synchronization signal control unit 310 locks the phase synchronization signal generated by itself as the system phase synchronization signal to be used as the reference for phase synchronization, and outputs the phase synchronization signal generated by itself to the phase synchronization signal bus 360 (as in step 460), and then ends the process.

[0075] Figure 5 It is a flow chart for the synchronization signal control unit 310 to perform synchronization judgment according to an embodiment of the present invention. After the pulse synchronization signal bus 370 receives the pulse synchronization signal (step 510), the synchronization signal control unit 310 first checks whether the received pulse synchronization signal is the signal sent by itself (step 530). If the answer to step 530 is yes, the synchronization signal control unit 310 does not perform any action. If the answer to step 530 is no, the synchronization signal control unit 310 locks the received pulse synchronization signal as the reference signal for pulse synchronization (step 550), and sends a pulse signal lock flag, indicating that its own pulse has been locked.

[0076] Similarly, after the phase synchronization signal bus 360 receives the phase synchronization signal (step 520), the synchronization signal control unit 310 first checks whether the received phase synchronization signal is the signal sent by itself (step 540). If the answer to step 540 is yes, the synchronization signal control unit 310 does not perform any action. If the answer to step 540 is no, the synchronization signal control unit 310 locks the received phase synchronization signal as the reference signal for phase synchronization (step 560), and sends a phase signal lock flag, indicating that its own phase has been locked.

[0077] Figure 6 It is a circuit embodiment of the synchronization control unit 310 according to an embodiment of the present invention. The synchronization control unit 310 includes buffers 610 and 620, as well as inverters 630 and 640, switches SW1 and SW2, and resistors R1 and R2. The resistors R1 and R2 are coupled to the switches SW1 and SW2.

[0078] When the synchronization control unit 310 generates a phase synchronization signal and / or a pulse synchronization signal, if there is no other signal input to the phase synchronization signal bus 360 and / or the pulse synchronization signal bus 370, the phase synchronization signal and / or the pulse synchronization signal generated by the synchronization control unit 310 will be output to the phase synchronization signal bus 360 and / or the pulse synchronization signal bus 370 through the buffers 610 and / or 620 (hereinafter, the phase synchronization signal bus 360 and the pulse synchronization signal bus 370 may also be collectively referred to as the synchronization signal bus), serving as the master control signal (which may also be referred to as the system phase synchronization signal and / or the system pulse synchronization signal) of the synchronization control unit 310 of all the PCSs 110. At the same time, the phase synchronization signal and / or the pulse synchronization signal generated by the synchronization control unit 310 causes the switches SW1 and / or SW2 to be turned off through the inverters 630 and / or 640, pulling the phase synchronization intercept pin and / or the pulse synchronization intercept pin to a low level to prevent the synchronization control unit 310 of itself from receiving the signals of the synchronization signal bus (the phase synchronization signal bus 360 and / or the pulse synchronization signal bus 370) in order to obtain the synchronization master control right. When another synchronization control unit 310 generates a phase synchronization signal and / or a pulse synchronization signal (i.e., the system phase synchronization signal and / or the system pulse synchronization signal) earlier through the synchronization signal bus, i.e., the phase synchronization signal bus 360 and / or the pulse synchronization signal bus 370, the system phase synchronization signal and / or the system pulse synchronization signal generated by the other synchronization control unit 310 is input to the phase synchronization intercept pin and / or the pulse synchronization intercept pin through the synchronization signal bus, and the synchronization control unit 310 takes the system phase synchronization signal and / or the system pulse synchronization signal generated by the other synchronization control unit 310 as the reference for phase synchronization and / or pulse synchronization.

[0079] Figure 7 FIG. is a schematic diagram of implementing synchronization control through a single-wire synchronization signal bus according to an embodiment of the present invention. Similarly, in Figure 7 a multi-module synchronization control module 221 according to an embodiment of the present invention includes: a synchronization signal control and analysis unit 710, a pulse (PWM) synchronization signal generator 720, and a mains phase synchronization signal generator 730. The pulse synchronization signal generator 720 and the mains phase synchronization signal generator 730 are basically the same as or similar to Figure 3 the pulse synchronization signal generator 320 and the mains phase synchronization signal generator 330 in

[0080] The synchronization signal control and analysis unit 710, pulse synchronization signal generator 720, and mains power phase synchronization signal generator 730 of the multi-module synchronization control module 221 are used to transmit / receive phase synchronization signals and pulse synchronization signals, and lock the phase synchronization signals and pulse synchronization signals. The pulse synchronization signal generator 720 is used to calculate the pulse synchronization signal. The mains power phase synchronization signal generator 730 is used to calculate the mains power phase synchronization signal.

[0081] The synchronization signal control and analysis unit 710 is used to transmit and / or receive synchronization control signals, and analyze the transmitted and / or received synchronization signals into phase synchronization signals and / or pulse synchronization signals, and then lock the phase synchronization signals and / or pulse synchronization signals.

[0082] Now, the operation of pulse synchronization and phase synchronization of a single synchronization signal busbar according to an embodiment of the present invention will be described. The pulse synchronization signal generator 720 calculates and generates a pulse synchronization signal. The mains power phase synchronization signal generator 730 calculates and generates a phase synchronization signal. The synchronization signal control and analysis unit 710 performs pulse signal synchronization judgment and phase signal synchronization judgment. If the pulse synchronization signal and / or phase synchronization signal has been received and locked by the synchronization signal busbar 750 before the pulse synchronization signal generator 720 and / or the mains power phase synchronization signal generator 730 outputs the pulse synchronization signal and / or phase synchronization signal, it is determined that the pulse and / or phase is synchronized.

[0083] If, before the pulse synchronization signal generator 720 and / or the mains power phase synchronization signal generator 730 outputs the pulse synchronization signal and / or phase synchronization signal, the pulse synchronization signal and / or phase synchronization signal generated by other PCS 110 has not been transmitted to the synchronization signal control and analysis unit 710 through the synchronization signal busbar 750 and locked, it is determined that the pulse and / or phase has not been synchronized. At this time, the synchronization signal control and analysis unit 710 locks its own generated pulse synchronization signal and / or phase synchronization signal as the pulse synchronization / phase synchronization reference, and outputs its own generated pulse synchronization signal and / or phase synchronization signal to the synchronization signal busbar 750, and then ends the process.

[0084] Figure 8The operation process of pulse synchronization and phase synchronization for a single synchronous signal bus according to an embodiment of the present invention. In step 810, the synchronization signal control and analysis unit 710 receives a synchronization signal, and then performs signal analysis to determine whether the received synchronization signal is a pulse synchronization signal or a phase synchronization signal (steps 820 and 830). If the received synchronization signal is a pulse synchronization signal, it is determined whether the received synchronization signal is sent by itself (step 840). If step 840 is yes, the process ends. If the received synchronization signal is not a signal sent by itself (step 840 is no), the received synchronization signal is locked as the reference signal for pulse synchronization (step 860), and a pulse signal locked flag is issued.

[0085] Similarly, if the received synchronization signal is a phase synchronization signal, it is determined whether the received synchronization signal is sent by itself (step 850). If step 850 is yes, the process ends. If the received synchronization signal is not a signal sent by itself (step 850 is no), the received synchronization signal is locked as the reference signal for phase synchronization (step 870), and a phase signal locked flag is issued.

[0086] In an embodiment of the present invention, the order of determining whether the received synchronization signal is a pulse synchronization signal or a phase synchronization signal can be swapped. That is, it is also possible to first determine whether the received synchronization signal is a phase synchronization signal, and then determine whether the received synchronization signal is a pulse synchronization signal.

[0087] Figure 9 The circuit schematic diagram of the synchronization signal control and analysis unit 710 according to an embodiment of the present invention. The synchronization signal control and analysis unit 710 includes: an OR logic gate 910, a synchronization signal analysis unit 920, inverters 931 and 932, switches SW91~SW94, and resistors R91~R94. The resistors R91~R94 are coupled to the switches SW91~SW94. The synchronization signal analysis unit 920 further includes counting comparators 921 and 922.

[0088] After the synchronization signal control and analysis unit 710 generates the phase synchronization signal and / or the pulse synchronization signal, the generated phase synchronization signal and / or pulse synchronization signal are output to the synchronization signal bus 750 through the OR logic gate 910, and the phase synchronization signal and / or pulse synchronization signal generated by itself are regarded as the system phase synchronization signal and / or the system pulse synchronization signal. In addition, the generated phase synchronization signal and / or pulse synchronization signal pass through the inverters 931 and 932 to disconnect SW91 and / or SW93, so that the phase synchronization intercept pin and / or the pulse synchronization intercept pin are pulled down to a low level. Then, the synchronization signal control and analysis unit 710 of itself does not receive the synchronization signal from the synchronization signal bus 750. Therefore, the synchronization signal control and analysis unit 710 of itself obtains the synchronization master control right.

[0089] If the synchronization signal control and analysis unit 710 receives the synchronization signal transmitted from other synchronization signal control and analysis units 710, the synchronization signal control and analysis unit 710 loads the received synchronization signal. The counting comparators 921 and 922 refer to the phase synchronization signal time reference value and / or the pulse synchronization signal time reference value to perform signal analysis (counting and comparison). After the analysis is completed, it is confirmed whether the corresponding synchronization signal has been locked. If the corresponding synchronization signal has been locked, no action is taken; if it has not been locked yet, the synchronization signal analysis unit 920 outputs the phase synchronization trigger signal and / or the pulse synchronization trigger signal, and selects the corresponding switch SW92 and / or SW94 according to whether the synchronization signal is a phase synchronization signal or a pulse synchronization signal, and raises the level of the phase synchronization intercept pin and / or the pulse synchronization intercept pin as a reference for which synchronization has been triggered, so that the multi-module synchronization control module 221 can correctly judge and lock the signal.

[0090] In an embodiment of the present invention, the multi-module synchronization control module implemented by a single-chip (MCU) software can generate and process synchronization signals to achieve the purpose of phase signal synchronization and pulse signal synchronization between multiple multi-module synchronization control modules. The single-wire synchronization signal bus or the double-wire synchronization signal bus (including the phase synchronization signal bus and the pulse synchronization bus) connects all the multi-module synchronization control modules to transmit and receive the pulse synchronization signal and the phase synchronization signal between these multi-module synchronization control modules. The parallel architecture of the power conversion system (PCS) with a single-wire synchronization signal bus can also be called a single-wire synchronization signal bus architecture; and the parallel architecture of the power conversion system (PCS) with a double-wire synchronization signal bus can also be called a double-wire synchronization signal bus architecture.

[0091] In a dual-line synchronous signal bus architecture, the multi-module synchronous control module includes: a pulse synchronous signal generator for calculating a pulse synchronous signal; a mains phase synchronous signal generator for calculating a mains phase synchronous signal synchronized with the mains phase; and a synchronous signal control unit for transmitting / receiving synchronous signals and locking the phase synchronous signal and the pulse synchronous signal.

[0092] When performing pulse synchronization operation: the pulse synchronous signal generator calculates and generates a pulse synchronous signal, and then the synchronous signal control unit performs pulse signal synchronization judgment; if before the pulse synchronous signal generator outputs the pulse synchronous signal, the pulse synchronous signal bus has received the pulse synchronous signal and locked the pulse synchronization, it is determined that the pulse is synchronized, and the pulse synchronization operation ends; if no other pulse synchronous signals are transmitted to the synchronous signal control unit through the pulse synchronous signal bus and locked before the pulse synchronous signal generator outputs the pulse synchronous signal, it is determined that the pulse is not synchronized. At this time, the synchronous signal control unit locks the pulse synchronous signal generated by itself as the reference for pulse synchronization, outputs the pulse synchronous signal generated by itself to the pulse synchronous signal bus, and then ends the pulse synchronization operation.

[0093] When performing phase synchronization operation: the phase synchronous signal generator calculates and generates a phase synchronous signal, and then the synchronous signal control unit performs phase signal synchronization judgment; if before the phase synchronous signal generator outputs the phase synchronous signal, the phase synchronous signal bus has received the phase synchronous signal and locked the phase synchronization, it is determined that the pulse phase is synchronized, and the phase synchronization operation ends; if no other phase synchronous signals are transmitted to the synchronous signal control unit through the phase synchronous signal bus and locked before the phase synchronous signal generator outputs the phase synchronous signal, it is determined that the phase is not synchronized. At this time, the synchronous signal control unit locks the phase synchronous signal generated by itself as the reference for phase synchronization, outputs the phase synchronous signal generated by itself to the phase synchronous signal bus, and then ends the phase synchronization operation.

[0094] When the synchronization signal control unit receives the pulse synchronization signal and / or phase synchronization signal from the pulse synchronization signal bus and / or phase synchronization signal bus, the judgment and locking process of the pulse and / or phase synchronization by the synchronization signal control unit is as follows: Receive the pulse synchronization signal and / or phase synchronization signal through the pulse synchronization signal bus and / or phase synchronization signal bus, and determine whether the received pulse synchronization signal and / or phase synchronization signal is the signal sent by its own synchronization signal control unit; if it is the pulse synchronization signal and / or phase synchronization signal sent by its own synchronization signal control unit, end the process; if it is not the pulse synchronization signal and / or phase synchronization signal sent by itself, lock the received pulse synchronization signal and / or phase synchronization signal as the reference signal for pulse synchronization and / or phase synchronization, and issue a pulse signal lock flag and / or phase signal lock flag.

[0095] In the single-line synchronization signal bus architecture, a multi-module synchronization control module implemented by a single-chip (MCU) software is used to generate, process, and analyze synchronization signals, so as to achieve the purpose of phase signal synchronization and pulse signal synchronization among multiple multi-module synchronization control modules.

[0096] In the single-line synchronization signal bus architecture, the synchronization signal bus is connected to all multi-module synchronization control modules to transmit and receive pulse synchronization signals and phase synchronization signals among these multi-module synchronization control modules.

[0097] In the single-line synchronization signal bus architecture, the multi-module synchronization control module includes: a pulse synchronization signal generator for calculating the pulse synchronization signal; a mains phase synchronization signal generator for calculating the mains phase synchronization signal; and a synchronization signal control and analysis unit for transmitting and receiving synchronization signals and analyzing the transmitted or received synchronization signals as phase synchronization signals or pulse synchronization signals, and then performing phase synchronization signal locking and pulse synchronization signal locking.

[0098] In the single-line synchronization signal bus architecture, the operation process of pulse synchronization and phase synchronization is as follows: The pulse synchronization signal generator and / or phase synchronization signal generator calculates and generates the pulse synchronization signal and / or phase synchronization signal, and then the synchronization signal control and analysis unit performs the judgment of pulse synchronization and / or phase synchronization.

[0099] In the single-line synchronization signal bus architecture, if before the pulse synchronization signal generator and / or phase synchronization signal generator outputs the pulse synchronization signal and / or phase synchronization signal, the synchronization signal bus has received the pulse synchronization signal and / or phase synchronization signal and has locked the pulse synchronization and / or phase synchronization, it is determined that the pulse and / or phase has been synchronized, and this action process is directly ended.

[0100] In a single - line synchronous signal bus architecture, if before the pulse synchronous signal generator and / or the phase synchronous signal generator outputs a pulse synchronous signal and / or a phase synchronous signal, there are no other pulse synchronous signals and / or phase synchronous signals transmitted to the synchronous signal control and analysis unit through the synchronous signal bus and locked, it is determined that the pulse and / or phase is not synchronized. At this time, the synchronous signal control and analysis unit will lock the pulse synchronous signal and / or phase synchronous signal generated by itself as the pulse synchronous reference and / or phase synchronous reference, and output the pulse synchronous signal and / or phase synchronous signal generated by itself to the synchronous signal bus, and then end the process.

[0101] In a single - line synchronous signal bus architecture, the synchronous signal control and analysis unit receives the synchronous signal, and then performs signal analysis to determine whether the received synchronous signal is a pulse synchronous signal or a phase synchronous signal. If the received synchronous signal is a pulse synchronous signal, it is determined whether the received synchronous signal is sent by itself. If it is sent by itself, the process ends; if it is not sent by itself, the received synchronous signal is locked as the pulse synchronous reference, and a pulse signal lock mark is sent.

[0102] In a single - line synchronous signal bus architecture, the synchronous signal control and analysis unit receives the synchronous signal, and then performs signal analysis to determine whether the received synchronous signal is a pulse synchronous signal or a phase synchronous signal. If the received synchronous signal is a phase synchronous signal, it is determined whether the received synchronous signal is sent by itself. If it is sent by itself, the process ends; if it is not sent by itself, the received synchronous signal is locked as the phase synchronous reference, and a phase signal lock mark is sent.

[0103] As can be seen from the above, in an embodiment of the present invention, the PCS (PCS controller) that sends the pulse synchronous signal or the phase synchronous signal on the synchronous signal bus (whether it is a single - line or double - line synchronous signal bus) fastest (earliest) obtains the master control right, and the synchronous signal sent by the PCS controller that obtains the master control right is used as the system synchronous signal. As for other PCS controllers that do not obtain the master control right, they refer to the system synchronous signal to synchronize with the system synchronous signal.

[0104] The present invention relates to a parallel architecture of a power conversion system (PCS). When multiple PCSs operate in parallel, a phase and pulse synchronous control method is proposed, which can make the pulse - width modulation (PWM) signals provided by multiple PCSs synchronize with the AC mains signal to ensure the synchronous operation of the outputs of each PCS. The present invention solves problems such as circulating current and interference that may occur in the system, and significantly improves the stability of the overall system.

[0105] Although the present invention may describe many specific details, these should not be construed as limitations on the scope of the claimed invention, but rather as descriptions of features of particular embodiments. In the description of the present invention, certain features described in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although a feature may initially be described as acting in certain combinations and may even initially be illustrated as such, in some cases, one or more features may be removed from that combination, and the illustrated combination may be directed to a sub-combination or variation of a sub-combination. Similarly, although operations are depicted in the drawings as occurring in a particular order, this should not be construed as requiring that the operations must occur in the particular order or sequence shown, or that all depicted operations must be performed to achieve the desired result.

[0106] Although only some examples and implementations of the above embodiments of the present invention are disclosed. Based on the disclosed content, changes, modifications, and enhancements can be made to the described examples and implementations as well as other implementations.

[0107] In summary, although the present invention has been disclosed above in embodiments, it is not intended to limit the present invention. Those of ordinary skill in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications should all fall within the scope of the present invention.

Claims

1. A power conversion system (PCS) parallel architecture, comprising: A plurality of PCSs, the PCSs are coupled to each other via a synchronization signal bus to achieve synchronization with each other, and the PCSs are also each coupled to an AC mains and a DC power source; Each of the PCSs includes a PCS controller. Among these PCS controllers, when a target PCS controller among these PCS controllers sends a synchronization signal on the synchronization signal bus the fastest to obtain a master right, the synchronization signal sent by the target PCS controller that obtains the master right is regarded as a system synchronization signal, and the other PCS controllers that have not obtained the master right refer to the system synchronization signal to synchronize with the system synchronization signal.

2. The power conversion system (PCS) parallel architecture according to claim 1, wherein: When the synchronization signal bus includes a pulse synchronization signal bus and a phase synchronization signal bus, each of the PCS controllers includes a multi-module synchronization control module, and the multi-module synchronization control module includes: A pulse synchronization signal generator, calculating and generating an own pulse synchronization signal; a phase synchronization signal generator, calculating and generating a phase synchronization signal of its own; and, A synchronization signal control unit is used to transmit / receive the synchronization signal and perform phase synchronization signal locking and pulse synchronization signal locking.

3. The power conversion system (PCS) parallel architecture according to claim 2, wherein: When locking the pulse synchronization signal: The pulse synchronization signal generator calculates and generates the own pulse synchronization signal; If the pulse synchronization signal bus has received a system pulse synchronization signal and has locked pulse synchronization before the pulse synchronization signal generator outputs its own pulse synchronization signal, it is determined that the pulse is synchronized; and If the system pulse synchronization signal is not transmitted to the synchronization signal control unit through the pulse synchronization signal bus and locked before the pulse synchronization signal generator outputs the own pulse synchronization signal, it is determined that the pulse is not synchronized, and the synchronization signal control unit locks the own pulse synchronization signal as a reference for pulse synchronization and outputs the own pulse synchronization signal to the pulse synchronization signal bus.

4. The power conversion system (PCS) parallel architecture according to claim 2, wherein: When locking the phase synchronization signal: The phase synchronization signal generator calculates and generates the own phase synchronization signal; If the phase synchronization signal bus has received a system phase synchronization signal and has locked the phase synchronization before the phase synchronization signal generator outputs the own phase synchronization signal, it is determined that the phase is synchronized; and If the system phase synchronization signal is not transmitted to the synchronization signal control unit through the phase synchronization signal bus and locked before the phase synchronization signal generator outputs its own phase synchronization signal, it is determined that the phase is not synchronized, and the synchronization signal control unit locks the own phase synchronization signal as a reference for phase synchronization and outputs the own phase synchronization signal to the phase synchronization signal bus.

5. The power conversion system (PCS) parallel architecture according to claim 2, wherein: The synchronization signal control unit also receives a first pulse synchronization signal and / or a first phase synchronization signal through the pulse synchronization signal bus and / or the phase synchronization signal bus, and determines whether the received first pulse synchronization signal and / or the first phase synchronization signal is sent by the synchronization signal control unit; If the received first pulse synchronization signal and / or the first phase synchronization signal is sent by the synchronization signal control unit, no action is performed; If the received first pulse synchronization signal and / or the first phase synchronization signal are not sent by the synchronization signal control unit, the received first pulse synchronization signal and / or the first phase synchronization signal are locked as a pulse synchronization reference signal and / or a phase synchronization reference signal, and a pulse signal locking mark and / or a phase signal locking mark are issued.

6. The power conversion system (PCS) parallel architecture according to claim 1, wherein: When the synchronization signal bus includes a single synchronization signal bus, each of the PCS controllers includes a multi-module synchronization control module, and the multi-module synchronization control module includes: A pulse synchronization signal generator, calculating and generating an own pulse synchronization signal; a phase synchronization signal generator, calculating and generating a phase synchronization signal of its own; and, A synchronization signal control and analysis unit is used to transmit and receive a synchronization signal and analyze the transmitted or received synchronization signal as a phase synchronization signal or a pulse synchronization signal, and then perform phase synchronization signal locking and pulse synchronization signal locking.

7. The power conversion system (PCS) parallel architecture according to claim 6, wherein: The pulse synchronization signal generator and / or the phase synchronization signal generator calculate and generate the own pulse synchronization signal and / or the own phase synchronization signal, and the synchronization signal control and analysis unit determines the pulse synchronization and / or phase synchronization.

8. The power conversion system (PCS) parallel architecture according to claim 6, wherein: If the synchronization signal bus has received a first pulse synchronization signal and / or a first phase synchronization signal and has locked the pulse synchronization and / or phase synchronization before the pulse synchronization signal generator and / or the phase synchronization signal generator outputs the own pulse synchronization signal and / or the own phase synchronization signal, then it is determined that the pulse and / or phase are synchronized; If the first pulse synchronization signal and / or the first phase synchronization signal has not been transmitted to the synchronization signal control and analysis unit through the synchronization signal bus and locked before the pulse synchronization signal generator and / or the phase synchronization signal generator outputs the own pulse synchronization signal and / or the own phase synchronization signal, it is determined that the pulse and / or the phase are not synchronized, and the synchronization signal control and analysis unit locks the own pulse synchronization signal and / or the own phase synchronization signal as the pulse synchronization reference and / or the phase synchronization reference, and outputs the own pulse synchronization signal and / or the own phase synchronization signal to the synchronization signal bus.

9. The power conversion system (PCS) parallel architecture according to claim 6, wherein if the synchronization signal received by the synchronization signal control and analysis unit is the pulse synchronization signal, it is determined whether the received synchronization signal is issued by itself, and if it is not issued by itself, the received synchronization signal is locked as a pulse synchronization reference and a pulse signal locking mark is issued; and If the received synchronization signal is the phase synchronization signal, it is determined whether the received synchronization signal is sent by itself. If it is not sent by itself, the received synchronization signal is locked as a phase synchronization reference and a phase signal locking mark is issued.

10. A synchronous control method of a power conversion system (PCS) parallel architecture, the power conversion system (PCS) parallel architecture comprising: A plurality of PCSs are coupled to each other via a synchronization signal bus to achieve synchronization with each other, and each of the PCSs includes a PCS controller to execute the synchronization control method: Among these PCS controllers, when a target PCS controller among these PCS controllers sends a synchronization signal on the synchronization signal bus the fastest to obtain a master right, the synchronization signal sent by the target PCS controller that obtains the master right is regarded as a system synchronization signal, and the other PCS controllers that have not obtained the master right refer to the system synchronization signal to synchronize with the system synchronization signal.

11. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 10, wherein: When the synchronization signal bus includes a pulse synchronization signal bus and a phase synchronization signal bus, each of the PCS controllers includes a multi-module synchronization control module, and the multi-module synchronization control module includes: A pulse synchronization signal generator, calculating and generating an own pulse synchronization signal; a phase synchronization signal generator, calculating and generating a phase synchronization signal of its own; and, A synchronization signal control unit is used to transmit / receive the synchronization signal and perform phase synchronization signal locking and pulse synchronization signal locking.

12. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 11, wherein: When locking the pulse synchronization signal: The pulse synchronization signal generator calculates and generates the own pulse synchronization signal; If the pulse synchronization signal bus has received a system pulse synchronization signal and has locked pulse synchronization before the pulse synchronization signal generator outputs its own pulse synchronization signal, it is determined that the pulse is synchronized; and If the system pulse synchronization signal is not transmitted to the synchronization signal control unit through the pulse synchronization signal bus and locked before the pulse synchronization signal generator outputs the own pulse synchronization signal, it is determined that the pulse is not synchronized, and the synchronization signal control unit locks the own pulse synchronization signal as a reference for pulse synchronization and outputs the own pulse synchronization signal to the pulse synchronization signal bus.

13. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 11, wherein: When locking the phase synchronization signal: The phase synchronization signal generator calculates and generates the own phase synchronization signal; If the phase synchronization signal bus has received a system phase synchronization signal and has locked the phase synchronization before the phase synchronization signal generator outputs the own phase synchronization signal, it is determined that the phase is synchronized; and If the system phase synchronization signal is not transmitted to the synchronization signal control unit through the phase synchronization signal bus and locked before the phase synchronization signal generator outputs its own phase synchronization signal, it is determined that the phase is not synchronized, and the synchronization signal control unit locks the own phase synchronization signal as a reference for phase synchronization and outputs the own phase synchronization signal to the phase synchronization signal bus.

14. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 11, wherein: The synchronization signal control unit also receives a first pulse synchronization signal and / or a first phase synchronization signal through the pulse synchronization signal bus and / or the phase synchronization signal bus, and determines whether the received first pulse synchronization signal and / or the first phase synchronization signal is sent by the synchronization signal control unit; If the received first pulse synchronization signal and / or the first phase synchronization signal is sent by the synchronization signal control unit, no action is performed; If the received first pulse synchronization signal and / or the first phase synchronization signal are not sent by the synchronization signal control unit, the received first pulse synchronization signal and / or the first phase synchronization signal are locked as a pulse synchronization reference signal and / or a phase synchronization reference signal, and a pulse signal locking mark and / or a phase signal locking mark are issued.

15. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 10, wherein: When the synchronization signal bus includes a single synchronization signal bus, each of the PCS controllers includes a multi-module synchronization control module, and the multi-module synchronization control module includes: A pulse synchronization signal generator, calculating and generating an own pulse synchronization signal; a phase synchronization signal generator, calculating and generating a phase synchronization signal of its own; and, A synchronization signal control and analysis unit is used to transmit and receive a synchronization signal and analyze the transmitted or received synchronization signal as a phase synchronization signal or a pulse synchronization signal, and then perform phase synchronization signal locking and pulse synchronization signal locking.

16. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 15, wherein: The pulse synchronization signal generator and / or the phase synchronization signal generator calculate and generate the own pulse synchronization signal and / or the own phase synchronization signal, and the synchronization signal control and analysis unit determines the pulse synchronization and / or phase synchronization.

17. The synchronous control method of the power conversion system (PCS) parallel architecture according to claim 15, wherein: If the synchronization signal bus has received a first pulse synchronization signal and / or a first phase synchronization signal and has locked the pulse synchronization and / or phase synchronization before the pulse synchronization signal generator and / or the phase synchronization signal generator outputs the own pulse synchronization signal and / or the own phase synchronization signal, then it is determined that the pulse and / or phase are synchronized; If the first pulse synchronization signal and / or the first phase synchronization signal has not been transmitted to the synchronization signal control and analysis unit through the synchronization signal bus and locked before the pulse synchronization signal generator and / or the phase synchronization signal generator outputs the own pulse synchronization signal and / or the own phase synchronization signal, it is determined that the pulse and / or the phase are not synchronized, and the synchronization signal control and analysis unit locks the own pulse synchronization signal and / or the own phase synchronization signal as the pulse synchronization reference and / or the phase synchronization reference, and outputs the own pulse synchronization signal and / or the own phase synchronization signal to the synchronization signal bus.

18. The synchronous control method of the parallel architecture of the power conversion system (PCS) according to claim 15, wherein if the synchronization signal received by the synchronization signal control and analysis unit is the pulse synchronization signal, it is determined whether the received synchronization signal is issued by itself, and if it is not issued by itself, the received synchronization signal is locked as a pulse synchronization reference, and a pulse signal locking mark is issued; and If the received synchronization signal is the phase synchronization signal, it is determined whether the received synchronization signal is sent by itself. If it is not sent by itself, the received synchronization signal is locked as a phase synchronization reference and a phase signal locking mark is issued.

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