Ultrahigh-voltage MOSFET terminal structure and preparation method thereof

Abstract

The invention provides an ultrahigh-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) terminal structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate; forming an oxide layer on the substrate; forming a main junction and a VLD junction in the substrate; depositing on the oxide layer to form a polycrystalline silicon field plate; depositing and forming a metal field plate on the polycrystalline silicon field plate; wherein the depth of the VLD junction is gradually reduced along the direction far away from the main junction. According to the embodiment of the invention, the VLD junction and the depth change of the VLD junction are arranged, and the polycrystalline silicon field plate and the metal field plate are matched, so that the terminal structure is shorter, the cost is lower and the reliability is higher while the high voltage resistance is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an ultra-high voltage MOSFET terminal structure and a preparation method thereof. Background Art

[0002] Ultra-high voltage MOSFETs (i.e., metal-oxide-semiconductor field-effect transistors) have the characteristics of small control power and fast switching speed, and are widely used in fields such as industrial power supplies, photovoltaic energy storage, instrumentation, medical aerospace, rail transit, and national grid power supplies. The technical difficulty lies in the design of the terminal structure. The main function of the terminal structure is to optimize the surface electric field distribution, prevent premature breakdown due to electric field concentration at the edge of the device, and thus increase the breakdown voltage. To meet the ultra-high voltage withstand requirements of the terminal, the design size of the terminal in the ultra-high voltage field is bound to be much larger than that in the medium-high voltage field, which results in an increase in the overall size of the chip. Therefore, how to obtain a terminal design with a shorter terminal length and higher reliability while ensuring the voltage withstand has become a key issue in device design. Summary of the Invention

[0003] In order to improve at least some of the disadvantages or deficiencies in the prior art, embodiments of the present invention provide an ultra-high voltage MOSFET terminal structure and a preparation method thereof, which make the terminal structure shorter, the cost less, and the reliability higher while ensuring high voltage withstand.

[0004] On the one hand, a preparation method of an ultra-high voltage MOSFET terminal structure provided by an embodiment of the present invention includes: providing a substrate; forming an oxide layer on the substrate; forming a main junction and a VLD junction in the substrate; depositing a polysilicon field plate on the oxide layer; depositing a metal field plate on the polysilicon field plate; wherein, the depth of the VLD junction gradually becomes smaller along the direction away from the main junction.

[0005] In some embodiments, the forming of the main junction and the VLD junction in the substrate specifically includes: horizontally opening a plurality of terminal injection windows on the oxide layer; injecting doping impurities into the substrate through the plurality of terminal injection windows; opening a main junction injection window on the oxide layer; injecting the doping impurities into the substrate through the main junction injection window; performing high-temperature push-junction to make the doping impurities injected through the terminal injection windows form the continuous VLD junction, and make the doping impurities injected through the main junction injection window form the main junction; wherein, the widths of the plurality of terminal injection windows gradually become smaller along the direction away from the main junction, and the distance between every two adjacent terminal injection windows gradually increases along the direction away from the main junction.

[0006] In some embodiments, the width difference between every two adjacent terminal injection windows is 0 μm - 0.2 μm.

[0007] In some embodiments, the width range of the terminal injection window is 1 μm - 7 μm.

[0008] In some embodiments, the distance range between every two adjacent terminal injection windows is 3 μm - 10.5 μm.

[0009] In some embodiments, the energy of the doped impurity injected by the terminal injection window is less than the energy of the doped impurity injected by the main junction injection window.

[0010] In some embodiments, the energy range of the doped impurity injected by the terminal injection window is 60 Kev - 100 Kev; the energy range of the doped impurity injected by the main junction injection window is 80 Kev - 120 Kev.

[0011] In some embodiments, depositing and forming a metal field plate on the polysilicon field plate includes forming a dielectric layer on the polysilicon field plate through photolithography and etching; performing hole photolithography and etching on the dielectric layer; and forming the metal field plate by metal precipitation on the dielectric layer.

[0012] Another embodiment of the present invention provides a super-high voltage MOSFET terminal structure, including: a substrate, in which a main junction and a VLD junction are arranged, and the depth of the VLD junction gradually becomes smaller along the direction away from the main junction; an oxide layer, located on the substrate; a polysilicon field plate, located on the oxide layer; a dielectric layer, located on the polysilicon field plate; and a metal field plate, located on the dielectric layer.

[0013] In some embodiments, the number of the polysilicon field plates is 19, the length of the polysilicon field plates is 20 μm, and the spacing between every two adjacent polysilicon field plates is 4 μm.

[0014] As can be seen from the above, the above technical features of the present invention can have one or more of the following beneficial effects: A super-high voltage MOSFET terminal structure and a preparation method thereof provided by an embodiment of the present invention, through a gradient VLD junction design, whose depth gradually decreases along the direction away from the main junction, optimize the electric field distribution, reduce the risk of electric field concentration, improve the breakdown voltage of the terminal structure, have a high breakdown voltage ability, and meet the super-high voltage application scenario; and the combination and application of the VLD junction with the polysilicon field plate and the metal field plate enable the terminal structure to achieve ultra-high breakdown voltage within a short length, effectively reducing the chip area and manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 It is a flowchart of a manufacturing method for a super-high voltage MOSFET terminal structure provided by an embodiment of the present invention.

[0017] Figure 2 It is a schematic structural diagram of a super-high voltage MOSFET terminal structure provided by an embodiment of the present invention.

[0018] Figure 3 It is a schematic structural diagram of lithography window opening in a super-high voltage MOSFET terminal structure provided by an embodiment of the present invention.

[0019] Figure 4 It is a schematic structural diagram of doping impurity implantation in a super-high voltage MOSFET terminal structure provided by an embodiment of the present invention.

[0020] Figure 5 It is a schematic structural diagram of forming a polysilicon field plate in a super-high voltage MOSFET terminal structure provided by an embodiment of the present invention.

[0021] Reference numerals: 10. Substrate; 20. Oxide layer; 210. Terminal injection window; 220. Main junction injection window; 30. Main junction; 40. VLD junction; 410. Field limiting ring; 50. Polysilicon field plate; 60. Metal field plate; 70. Cut-off field plate; 80. Cut-off ring. Detailed implementation manners

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0023] As Figure 1 shown, Figure 1 It is the process of a preparation method for a super-high voltage MOSFET terminal structure shown in an embodiment of the present invention. A preparation method for a super-high voltage MOSFET terminal structure according to an embodiment of the present invention includes: Step S10: Provide a substrate 10.

[0024] Step S20: Form an oxide layer 20 on the substrate 10.

[0025] Step S30: Form a main junction 30 and a VLD junction 40 in the substrate 10.

[0026] Step S40: Deposit and form a polysilicon field plate 50 on the oxide layer 20.

[0027] Step S50: Deposit and form a metal field plate 60 on the polysilicon field plate 50.

[0028] Among them, in step S10, the substrate 10 is a silicon substrate. Since the base material of the ultra-high voltage device needs to use a relatively thick low-doped layer, generally greater than 300 μm, and the silicon-based wafer cannot achieve such a thick epitaxial process, the base material is selected as a low-doped single crystal material. For example, the resistivity of the substrate 10 can be, for example, 150 - 170 Ω•cm, the thickness range of the thinned substrate 10 is 300 μm - 380 μm, and the length is 650 μm.

[0029] In step S20, the substrate 10 undergoes a first field oxidation to form an oxide layer 20 with a thickness of, for example, 4000 angstroms, and then undergoes a second oxidation to form an oxide layer 20 with a thickness of, for example, 20000 angstroms for subsequent precipitation of the polysilicon field plate 50. The thick oxide layer suppresses the surface electric field concentration through its high dielectric strength, especially the peak value of the lateral electric field in the terminal region. The oxide layer 20 serves as an insulating layer between the polysilicon field plate 50 and the underlying substrate 10, which can prevent the polysilicon field plate 50 from directly contacting the semiconductor surface, avoid the risk of leakage current or short circuit, provide a flat and stable surface for the deposition and etching of the polysilicon field plate 50, and ensure the precise formation of the field plate structure.

[0030] Referring to Figure 2 、 Figure 3 and Figure 4 , in step S30, the depth of the VLD junction 40 gradually decreases in the direction away from the main junction 30. The VLD junction 40 forms a laterally graded doping concentration distribution, which can effectively expand the depletion region and reduce the electric field peak value, thereby improving the breakdown voltage capability of the device. The VLD junction 40 includes a plurality of field limiting rings 410, and the PN junctions formed by each field limiting ring 410 are connected together, so that the VLD terminal junction can form a large continuous PN junction, and the junction depth gradually decreases in the direction away from the main junction 30.

[0031] In steps S40 and S50, the metal field plate 60 can be selected from copper, aluminum, and tungsten. In this embodiment, the metal field plate 60 is a metal aluminum field plate. The polysilicon field plate 50 and the metal field plate 60 are used to improve the electric field distribution of the semiconductor device. By changing the electric field distribution, the electric field concentration phenomenon is reduced, thereby improving the breakdown voltage capability and reliability of the device.

[0032] In this embodiment, a terminal PN junction is formed by adopting the lateral variable doping technique, and a terminal structure manufactured with a polysilicon field plate 50 and a metal field plate 60 is used. Its terminal breakdown voltage can reach more than 3100V. On the basis of ensuring the breakdown voltage, the length of the manufactured terminal structure is shorter and the size is smaller. Through the synergistic effect of the polysilicon field plate and the metal field plate, the electric field concentration phenomenon is reduced and the reliability is improved.

[0033] Specifically, referring to Figure 3 and Figure 4 , step S30 specifically includes: Step S31, a plurality of terminal injection windows 210 are laterally opened on the oxide layer 20.

[0034] Step S32, doping impurities are injected into the substrate 10 through the plurality of terminal injection windows 210.

[0035] Step S33, a main junction injection window 220 is opened on the oxide layer 20.

[0036] Step S34, doping impurities are injected into the substrate 10 through the main junction injection window 220.

[0037] Step S35, high-temperature junction pushing is performed to form a continuous VLD junction 40 with the doping impurities injected through the terminal injection windows 210, and to form a main junction with the doping impurities injected through the main junction injection window 220.

[0038] Among them, in step S31, the terminal injection windows 210 are lithographed through a photoresist, and the oxide layer 20 of the terminal injection windows 210 is etched away, and the photoresist is removed to expose the terminal injection windows 210. The width difference between every two adjacent terminal injection windows 210 can be, for example, 0μm - 0.2μm, the width range of the terminal injection windows 210 is, for example, 1μm - 7μm, and the distance range between every two adjacent terminal injection windows 210 is, for example, 3μm - 10.5μm; and the widths of the plurality of terminal injection windows 210 show a gradually decreasing trend, and the distance between every two adjacent terminal injection windows 210 shows a gradually increasing trend. Among them, the widths of the plurality of terminal injection windows 210 can be designed to gradually decrease along the direction away from the main junction 30. Specifically, the width difference between every two adjacent terminal injection windows 210 can be, for example, 0μm, 0.10μm, 0.15μm or 0.20μm.

[0039] In step S32, doping impurities are injected into the substrate 10 through the terminal injection windows 210. Among them, the substrate 10 is of the first conduction type, and the doping impurities are of the second conduction type. In this embodiment, the first conduction type is N-type and the second conduction type is P-type. Specifically, the doping impurities are boron ions.

[0040] In step S33, a main junction photolithography is performed on the oxide layer 20 to lithographically expose a main junction implantation window 220. The width dimension of the main junction implantation window 220 is, for example, greater than 35 μm.

[0041] In step S34, a doped impurity, i.e., boron ions, is implanted through the main junction implantation window 220, and the photoresist is removed after the main junction implantation is completed.

[0042] In step S35, for example, the device is pushed in an environment of 1150 °C for more than 300 minutes, so that the doped impurities implanted through the main junction implantation window 220 form a main junction 30; and the doped impurities implanted through the terminal implantation window 210 form a continuous VLD junction 40, that is, PN junctions (i.e., field limiting rings) are formed after the diffusion of the doped impurities in each terminal implantation window 210, and these field limiting rings 410 form a VLD junction 40 with a linearly varying implanted doped impurity concentration. Specifically, during the high-temperature process, the boron ion impurities in the terminal implantation window 210 undergo lateral and vertical diffusion. The lateral diffusion causes the PN junctions of each terminal implantation window 210 to be connected together to form a PN junction with a relatively long series connection (i.e., the VLD junction 40); the vertical diffusion causes the main junction 30 and the PN junction to reach a specified depth.

[0043] Among them, the widths of the multiple terminal implantation windows 210 gradually decrease in the direction away from the main junction 30, and the distances between every two adjacent terminal implantation windows 210 gradually increase in the direction away from the main junction 30. Since the widths of the terminal implantation windows 210 are different, the impurity concentrations in each terminal implantation window 210 after implanting boron ions will be different. The narrower the terminal implantation window 210, the lower the impurity concentration, and the shallower the junction depth of the PN junction (i.e., the field limiting ring) formed after pushing the junction. Therefore, the PN junction depth in the region close to the main junction 30 is deep, and the PN junction away from the main junction 30 is shallow, making the concentration of the implanted doped impurities vary linearly in the lateral direction, thereby eliminating the peak electric field, making the surface electric field uniform, and thus increasing the breakdown voltage.

[0044] In some embodiments, the energy of the doped impurities implanted through the terminal implantation window 210 is less than the energy of the doped impurities implanted through the main junction implantation window 220, ensuring that the PN junction concentration of the main junction 30 is higher and the PN junction depth is deeper, which is beneficial to the electric field optimization of the terminal structure.

[0045] Specifically, the energy range of the doped impurities injected by the terminal injection window 210 is 60 Kev - 100 Kev. The doped impurities in this terminal region have a relatively shallow penetration depth in the substrate 10, forming a shallow doping. Combined with the subsequent high-temperature junction pushing, the lateral diffusion of the doped impurities is significant, and multiple PN junctions are connected in series to form a gradient distribution, dispersing the surface electric field. The energy range of the doped impurities injected by the main junction injection window 220 is 80 Kev - 120 Kev, enabling the doped impurities to penetrate deeper. Combined with a high dose, a deep and high-concentration PN junction is formed. After high-temperature junction pushing, the junction depth in the main junction region is deeper than that in the terminal region. The high-concentration doping reduces the on-resistance of the main junction 30, improves the current-carrying capacity, and the deep-junction structure optimizes the longitudinal electric field distribution, preventing premature breakdown in the main junction region, which is beneficial to electric field optimization. Moreover, the dose of the doped impurities injected by the terminal injection window 210 is also less than that of the doped impurities injected by the main junction injection window 220.

[0046] See Figure 4 , in some embodiments, before depositing and forming the polysilicon field plate 50 on the oxide layer 20 in step S40, it further includes lithography in the active region, defining the boundary between the active region and the terminal region through a photoresist mask; selectively etching the oxide layer 20 (i.e., the secondary field oxide layer) on the surface of the active region to expose the substrate 10, providing a clean substrate 10 for subsequent processes such as gate oxidation, source injection, and metal contact, and being able to maintain the thick oxide layer in the terminal region to ensure that its breakdown voltage performance is not affected; removing the residual photoresist after lithography to ensure surface cleanliness and avoid impurities or defects introduced by photoresist residues from affecting the device reliability.

[0047] Furthermore, after step S40, it further includes: P-well injection; P+ lithography / injection / degluing; P-well junction pushing; N+ lithography / injection / degluing.

[0048] See Figure 5 , in some embodiments, step S50 of depositing and forming the metal field plate 60 on the polysilicon field plate 50 includes: forming a dielectric layer on the polysilicon field plate 50 through lithography and etching; Performing hole lithography and etching on the dielectric layer; Forming the metal field plate 60 by metal precipitation on the dielectric layer.

[0049] Among them, the material of the dielectric layer can be selected as phosphosilicate glass (PSG), undoped silicon glass (USG), borophosphosilicate glass (BPSG), etc., or a double-layer composite material of USG and PSG or BPSG.

[0050] After step S50, it further includes: depositing silicon dioxide and silicon oxide, depositing a passivation layer; performing back high-dose implantation on the substrate 10. The passivation layer isolates environmental moisture, ionic contaminants, and particles, preventing device failure due to corrosion or leakage. Through back high-dose implantation, a highly doped region is formed on the back of the substrate 10, forming a low-resistance contact, and enabling the depletion region to stop expanding at the substrate edge, avoiding edge breakdown and improving reliability.

[0051] See Figure 2 According to an embodiment of the present invention, a super-high voltage MOSFET terminal structure formed according to the above method is provided, including a substrate 10, an oxide layer 20, a polysilicon field plate 50, a dielectric layer, and a metal field plate 60. A main junction 30 and a VLD junction 40 are provided in the substrate 10. The depth of the VLD junction 40 gradually decreases in the direction away from the main junction 30. The gradually changing doping concentration distribution can effectively expand the depletion region and reduce the electric field peak value, thereby optimizing the electric field distribution at the device edge and avoiding local electric field concentration. The oxide layer 20 is located on the substrate 10, the polysilicon field plate 50 is located on the oxide layer 20, the dielectric layer is located on the polysilicon field plate 50, and the metal field plate 60 is located on the dielectric layer. The polysilicon field plate 50 and the metal field plate 60 act together to further improve the electric field distribution, reduce the electric field concentration phenomenon, and improve the breakdown voltage of the device. While ensuring the breakdown voltage, this terminal structure can reduce the size of the terminal structure, improve the chip integration, and reduce the manufacturing cost by optimizing the doping distribution and the electric field distribution.

[0052] Furthermore, a cutoff ring 80 is further included on the substrate 10. The cutoff ring 80 is located at the edge of the terminal structure. The VLD junction 40 is located between the cutoff ring 80 and the main junction 30. The depth of the VLD junction 40 gradually decreases from the main junction 30 to the cutoff ring 80, reducing the strong electric field concentration at the end of the terminal structure, enabling the PN junction depletion region to quickly cutoff after expanding to the cutoff ring 80, and reducing the possibility of leakage of the terminal structure.

[0053] See Figure 2 and Figure 5 In some embodiments, for example, the number of polysilicon field plates 50 is 19, the length of the polysilicon field plate 50 is 20 μm, and the spacing between every two adjacent polysilicon field plates 50 is 4 μm. Through the electric field superposition effect, the longitudinal electric field distribution is effectively smoothed.

[0054] Further, it further includes a cutoff field plate 70. One end of the cutoff field plate 70 is located on the oxide layer 20, and the other end is lapped on the cutoff ring 80. The cutoff field plate 70 can transfer a part of the internal electric field of the substrate 10 to the oxide layer 20, which can further reduce the leakage current of the device, improve the local field strength, reduce the concentration of the local field strength, and improve the breakdown voltage of the terminal structure. Among them, the length of the cutoff field plate 70 is, for example, 18.5 μm, which is slightly shorter than that of other polysilicon field plates 50, forming a progressive electric field attenuation at the end of the terminal to avoid premature breakdown caused by edge electric field concentration.

[0055] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0056] In addition, it can be understood that the foregoing embodiments are only exemplary descriptions of the present invention. On the premise that there is no conflict in technical features, no contradiction in structure, and no violation of the purpose of the present invention, the technical solutions of the various embodiments can be arbitrarily combined and used in combination.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing an ultra-high voltage MOSFET terminal structure, characterized in that: include: Providing a substrate (10); forming an oxide layer (20) on the substrate (10); forming a main junction (30) and a VLD junction (40) in the substrate (10); Depositing a polysilicon field plate (50) on the oxide layer (20); Depositing a metal field plate (60) on the polysilicon field plate (50); The depth of the VLD junction (40) gradually decreases in a direction away from the main junction (30).

2. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 1, characterized in that: The forming of the main junction (30) and the VLD junction (40) in the substrate (10) specifically comprises: A plurality of terminal injection windows (210) are laterally opened on the oxide layer (20); Injecting doping impurities into the substrate (10) through the plurality of terminal injection windows (210); Opening a main junction injection window (220) on the oxide layer (20); Injecting the doping impurities into the substrate (10) through the main junction injection window (220); Performing high temperature push-junction, so that the doping impurities injected through the terminal injection window (210) form the continuous VLD junction (40), and so that the doping impurities injected through the main junction injection window (220) form the main junction (30); The widths of the plurality of terminal injection windows (210) gradually decrease in a direction away from the main junction (30), and the distance between each two adjacent terminal injection windows (210) gradually increases in a direction away from the main junction (30).

3. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 2, characterized in that: The width difference between any two adjacent terminal injection windows (210) is 0 μm-0.2 μm.

4. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 3, characterized in that: The width of the terminal injection window (210) ranges from 1 μm to 7 μm.

5. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 2, characterized in that: The distance between each two adjacent terminal injection windows (210) ranges from 3 μm to 10.5 μm.

6. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 2, characterized in that: The energy of the doping impurities injected into the terminal injection window (210) is less than the energy of the doping impurities injected into the main junction injection window (220).

7. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 6, characterized in that: The energy range of the doping impurities injected into the terminal injection window (210) is 60 KeV-100 KeV; The energy range of the doping impurities injected into the main junction injection window (220) is 80 KeV-120 KeV.

8. The method for preparing the ultra-high voltage MOSFET terminal structure according to claim 1, characterized in that: The step of depositing a metal field plate (60) on the polysilicon field plate (50) comprises: Forming a dielectric layer on the polysilicon field plate (50) through photolithography and etching; Performing hole photolithography and etching on the dielectric layer; The metal field plate (60) is formed on the dielectric layer by metal deposition.

9. An ultra-high voltage MOSFET terminal structure, characterized in that: include: A substrate (10) having a main junction (30) and a VLD junction (40) disposed therein, wherein the depth of the VLD junction (40) gradually decreases in a direction away from the main junction (30); An oxide layer (20) located on the substrate (10); A polysilicon field plate (50) located on the oxide layer (20); a dielectric layer, located on the polysilicon field plate (50); and A metal field plate (60) is located on the dielectric layer.

10. The ultra-high voltage MOSFET terminal structure according to claim 9, characterized in that: The number of the polysilicon field plates (50) is 19, the length of the polysilicon field plates (50) is 20 μm, and the distance between any two adjacent polysilicon field plates (50) is 4 μm.

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