MMC (Modular Multilevel Converter) fault processing method and device based on sub-module, equipment and storage medium

Abstract

The invention discloses an MMC sub-module fault processing method, device and equipment and a storage medium, and the method comprises the steps: obtaining the capacitor voltage value of a sub-module of an MMC and the bridge arm current value of the sub-module, the MMC comprises six bridge arms of three phases, each bridge arm comprises a plurality of sub-modules, the capacitor of each sub-module is connected with an equivalent series resistor in series, and further, the equivalent series resistor is connected with the capacitor voltage value of the sub-module of the MMC; the resistance value of an equivalent series resistor in the sub-module is monitored through the capacitor voltage value and the bridge arm current value, if the resistance value of the equivalent series resistor is higher than a preset resistance value, it is determined that the capacitor of the sub-module fails, fault-tolerant control is carried out on the sub-module through a voltage-sharing and circulating current suppression algorithm, a three-phase switching signal is output, and the three-phase switching signal acts on the MMC. Therefore, the circulating current fundamental frequency component and the double frequency component caused by fault-tolerant control after the fault can be eliminated through the circulating current suppression strategy, the effect of circulating current suppression is achieved, and the stability of system fault operation is improved.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and more specifically, to a fault handling method, device, equipment and storage medium for a modular multilevel converter (MMC) based on sub-modules. Background Art

[0002] In the field of modern power electronics technology, the modular multilevel converter (MMC) is widely used in key fields such as high-voltage direct current transmission because of its low output voltage harmonics, small switching losses, and ability to achieve high-voltage and large-capacity power conversion. Its reliability problem has thus attracted much attention in the academic and industrial circles.

[0003] Electrolytic capacitors, with the advantages of large capacitance and high cost performance, undertake key tasks such as stabilizing the DC bus voltage in the MMC converter. However, it is the component with the shortest lifespan in the MMC converter. Affected by the working temperature, voltage stress, and ripple current, the internal electrolyte volatilizes, resulting in a decrease in capacitance value and an increase in equivalent series resistance (ESR). When the capacitance value is reduced to 80% of the initial value, or the ESR is increased to 2-3 times the initial value, the capacitor fails.

[0004] However, the number of capacitors in the MMC sub-module is huge, and its reliability problem is prominent. A large number of capacitor failures will reduce the system response speed and further threaten the stable operation of the system.

[0005] Therefore, how to enable the MMC to perform fault handling for sub-modules, timely identify and remove faults, so as to improve the stability of the system, is an issue that needs attention. Summary of the Invention

[0006] In view of the above problems, the present application provides a fault handling method, device, equipment and storage medium for an MMC based on sub-modules to improve the stability of the system.

[0007] To achieve the above object, the following specific solutions are proposed:

[0008] A fault handling method for an MMC based on sub-modules includes:

[0009] Obtain the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module, where the MMC includes six arms in three phases, each arm includes a number of sub-modules, and the capacitor of each sub-module is connected in series with an equivalent series resistance;

[0010] Monitor the resistance value of the equivalent series resistance in the sub-module through the capacitance voltage value and the arm current value;

[0011] If the resistance value of the equivalent series resistance is higher than a preset resistance value, determine that the capacitor of the sub-module fails;

[0012] Fault tolerance control is performed on the sub-module through the voltage equalization and circulating current suppression algorithms, three-phase switching signals are output, and the three-phase switching signals are applied to the MMC.

[0013] Optionally, obtaining the capacitor voltage value of the sub-module of the MMC and the arm current value of the sub-module includes:

[0014] Detecting a first capacitor voltage value at a previous sampling moment of the positive jump edge of the capacitor voltage of the sub-module of the MMC, a second capacitor voltage value and a first arm current value at a subsequent sampling moment of the positive jump edge;

[0015] Detecting a third capacitor voltage value at a previous sampling moment of the negative jump edge of the capacitor voltage of the sub-module, a fourth capacitor voltage value and a second arm current value at a subsequent sampling moment of the negative jump edge.

[0016] Optionally, monitoring the resistance value of the equivalent series resistance in the sub-module through the capacitor voltage value and the arm current value includes:

[0017] Using the following formula, calculating the resistance value of the equivalent series resistance in the sub-module according to the first capacitor voltage value, the second capacitor voltage value, the first arm current value, the third capacitor voltage value, the fourth capacitor voltage value and the second arm current value:

[0018]

[0019] Wherein, is the resistance value of the equivalent series resistance in the sub-module, is the first capacitor voltage value, is the second capacitor voltage value, is the first arm current value, is the third capacitor voltage value, is the fourth capacitor voltage value, is the second arm current value.

[0020] Optionally, the method further includes:

[0021] If there are sub-modules that fail in the arm on the target phase of the MMC, then determining that the peak value of the output voltage of the sub-module in the arm on the target phase is:

[0022]

[0023] Wherein, is the total number of sub-modules in the arm on the target phase, is the capacitor voltage value of the sub-module that does not fail in the arm on the target phase;

[0024] Determine that the output voltage peak value of the lower arm of the target phase is:

[0025] .

[0026] Optionally, the method further includes:

[0027] Lift the voltage of the sub-modules on the upper arm of the target phase that have not failed. After the failure of the sub-modules occurs, determine the capacitance voltage reference value of the sub-modules that have not failed as:

[0028]

[0029] where is the default reference value of the sub-module capacitance voltage;

[0030] After performing fault tolerance control on the sub-modules on the upper arm of the target phase, determine the upper limit value of the sub-modules allowed to fail on the upper arm of the target phase as:

[0031]

[0032] where is the maximum withstand voltage value of the sub-module capacitance voltage of the MMC.

[0033] Optionally, the fault tolerance control of the sub-modules by the voltage equalization and circulating current suppression algorithm and the output of three-phase switching signals include:

[0034] Calculate the circulating current reference value using the following formula:

[0035]

[0036] where is the proportional coefficient, is the integral coefficient, 1 / s is the integral link, is the average value of the capacitance voltages of all sub-modules in one phase of the MMC, is the capacitance voltage reference value of the sub-modules that have not failed in the one phase;

[0037] Input the circulating current reference value into a notch filter for processing and perform deadbeat current tracking to obtain the upper arm inductor voltage and the lower arm inductor voltage of the one phase. The upper arm inductor voltage is:

[0038]

[0039] where is the arm inductor, is the control cycle duration, is the reference value of the AC side current of the j-th phase of the MMC, is the current of the upper bridge arm of the j-th phase at the k-th control period;

[0040] The voltage of the lower bridge arm inductor is:

[0041]

[0042] where, is the current of the lower bridge arm of the j-th phase at the K-th control period;

[0043] Modulate the voltage of the upper bridge arm inductor to obtain the reference voltage of the upper bridge arm of the MMC as:

[0044]

[0045] where, is the DC bus voltage of the MMC, is the reference voltage of the bridge arm of the MMC under normal operating conditions;

[0046] Modulate the voltage of the lower bridge arm inductor to obtain the reference voltage of the lower bridge arm of the MMC as:

[0047]

[0048] Output three-phase switching signals according to the reference voltage of the upper bridge arm and the reference voltage of the lower bridge arm.

[0049] An MMC sub-module-based fault handling device, comprising:

[0050] A sub-module electrical value acquisition unit, configured to acquire the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module, where the MMC includes three phases and a total of six bridge arms, each bridge arm includes a plurality of sub-modules, and the capacitance of each sub-module is connected in series with an equivalent series resistance;

[0051] An equivalent series resistance monitoring unit, configured to monitor the resistance value of the equivalent series resistance in the sub-module through the capacitance voltage value and the arm current value;

[0052] A sub-module capacitance failure determination unit, configured to determine that the capacitance of the sub-module fails if the resistance value of the equivalent series resistance is higher than a preset resistance value;

[0053] A fault response unit, configured to perform fault tolerance control on the sub-module through an equalizing and circulating current suppression algorithm, output three-phase switching signals, and apply the three-phase switching signals to the MMC.

[0054] Optionally, the sub-module electrical value acquisition unit includes:

[0055] The first sub-module electrical value acquisition sub-unit is configured to detect a first capacitor voltage value at a previous sampling moment of the positive edge of the capacitor voltage of the sub-module of the MMC, and a second capacitor voltage value and a first arm current value at a subsequent sampling moment of the positive edge;

[0056] The second sub-module electrical value acquisition sub-unit is configured to detect a third capacitor voltage value at a previous sampling moment of the negative edge of the capacitor voltage of the sub-module, and a fourth capacitor voltage value and a second arm current value at a subsequent sampling moment of the negative edge.

[0057] Optionally, the equivalent series resistance monitoring unit includes:

[0058] The equivalent series resistance monitoring sub-unit is configured to calculate the resistance value of the equivalent series resistance in the sub-module by using the following formula according to the first capacitor voltage value, the second capacitor voltage value, the first arm current value, the third capacitor voltage value, the fourth capacitor voltage value, and the second arm current value:

[0059]

[0060] Wherein, is the resistance value of the equivalent series resistance in the sub-module, is the first capacitor voltage value, is the second capacitor voltage value, is the first arm current value, is the third capacitor voltage value, is the fourth capacitor voltage value, is the second arm current value.

[0061] Optionally, the device further includes:

[0062] The sub-module output voltage peak determination unit is configured to, if there are sub-modules that fail on the arm of the target phase of the MMC, determine the sub-module output voltage peak of the arm on the target phase as:

[0063]

[0064] Wherein, is the total number of sub-modules of the arm on the target phase, is the sub-module capacitor voltage value of the arm on the target phase that does not fail;

[0065] The lower arm output voltage peak determination unit is configured to determine the output voltage peak of the lower arm of the target phase as:

[0066] .

[0067] Optionally, the device further includes:

[0068] A capacitor voltage reference value determination unit, configured to boost the voltage of the sub-modules on the arm of the target phase where no fault occurs, and after the sub-module fault occurs, determine the capacitor voltage reference value of the non-faulty sub-module as:

[0069]

[0070] wherein, is the default reference value of the sub-module capacitor voltage;

[0071] A faulty sub-module upper limit value determination unit, configured to determine the upper limit value of the sub-modules allowed to have faults on the arm of the target phase as: after performing fault tolerance control on the sub-modules on the arm of the target phase

[0072]

[0073] wherein, is the maximum withstand voltage value of the sub-module capacitor voltage of the MMC.

[0074] Optionally, the fault response unit includes:

[0075] A circulating current reference value calculation unit, configured to calculate the circulating current reference value by using the following formula:

[0076]

[0077] wherein, is the proportionality coefficient, is the integral coefficient, 1 / s is the integral link, is the average value of the capacitor voltages of all sub-modules in one of the phases of the MMC, is the capacitor voltage reference value of the non-faulty sub-modules in the one phase;

[0078] An arm inductor voltage determination unit, configured to input the circulating current reference value to a notch filter for processing and perform deadbeat current tracking to obtain the upper arm inductor voltage and the lower arm inductor voltage of the one phase, and the upper arm inductor voltage is:

[0079]

[0080] wherein, is the arm inductor, is the control cycle duration, is the AC side current reference value of the j-th phase of the MMC, is the upper arm current of the j-th phase at the k-th control cycle;

[0081] The lower-arm inductor voltage is as follows:

[0082]

[0083] Wherein, is the lower-arm current of the j-th phase at the K-th control period;

[0084] The first modulation unit is used to modulate the upper-arm inductor voltage to obtain the upper-arm reference voltage of the MMC as:

[0085]

[0086] Wherein, is the DC bus voltage of the MMC, is the arm reference voltage of the MMC under normal operating conditions;

[0087] The second modulation unit is used to modulate the lower-arm inductor voltage to obtain the lower-arm reference voltage of the MMC as:

[0088]

[0089] The three-phase switch signal output unit is used to output three-phase switch signals according to the upper-arm reference voltage and the lower-arm reference voltage.

[0090] An MMC sub-module based fault handling device, comprising a memory and a processor;

[0091] The memory is used to store programs;

[0092] The processor is used to execute the program to implement each step of the MMC sub-module based fault handling method as described above.

[0093] A storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each step of the MMC sub-module based fault handling method as described above is implemented.

[0094] With the above technical solution, the present application obtains the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module. Among them, the MMC includes six arms in three phases, each arm includes a number of sub-modules, and the capacitors of each sub-module are connected in series with an equivalent series resistance. Further, by the capacitance voltage value and the arm current value, the resistance value of the equivalent series resistance in the sub-module is monitored. If the resistance value of the equivalent series resistance is higher than the preset resistance value, it is determined that the capacitor of the sub-module fails. Fault tolerance control is performed on the sub-module through the voltage equalization and circulating current suppression algorithms, three-phase switching signals are output, and the three-phase switching signals are applied to the MMC. Thus, it can be seen that through the circulating current suppression strategy, the fundamental frequency component and the second harmonic component of the circulating current caused by fault tolerance control after a fault can be eliminated, the effect of circulating current suppression can be achieved, and the stability of the system during fault operation can be improved.

[0095] Further, it is not necessary to add additional sensors to monitor the resistance value of the equivalent series resistance in real time, which is more efficient and convenient compared with the traditional method using additional sensors. Brief Description of the Drawings

[0096] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0097] Figure 1 It is a schematic flow chart for implementing fault handling of MMC based on sub-modules provided by an embodiment of the present application;

[0098] Figure 2 It is a topology diagram of an MMC provided by an embodiment of the present application;

[0099] Figure 3 It is a schematic diagram of an MMC sub-module provided by an embodiment of the present application;

[0100] Figure 4 It is a schematic diagram of the current and voltage waveforms of a sub-module provided by an embodiment of the present application;

[0101] Figure 5 It is a control block diagram of a deadbeat circulating current control strategy provided by an embodiment of the present application;

[0102] Figure 6 It is a schematic structural diagram of a device for implementing fault handling of MMC based on sub-modules provided by an embodiment of the present application;

[0103] Figure 7 It is a schematic structural diagram of a device for implementing fault handling of MMC based on sub-modules provided by an embodiment of the present application. Detailed Embodiments

[0104] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0105] The solution of the present application can be implemented based on a terminal with data processing capabilities, and the terminal can be a computer, the cloud, a server, etc.

[0106] Next, in combination with Figure 1 As described above, the fault handling method of the MMC of the present application based on sub-modules may include the following steps:

[0107] Step S110: Obtain the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module.

[0108] Among them, the MMC may include six arms in three phases. Each arm includes a number of sub-modules, and the capacitors of each sub-module are connected in series with equivalent series resistors.

[0109] The topology diagram of the MMC is as Figure 2 shown. The MMC includes three phases, each phase includes upper and lower arms, a total of six arms, and each arm has N half-bridge sub-modules. The schematic diagram of each sub-module is as Figure 3 shown. The sub-module can adopt a common half-bridge structure, including two IGBTs, T1 and T2. Among them, the sub-module capacitor can be equivalent to the series combination of an ideal capacitor and an ideal resistor. i C is the current flowing through the sub-module capacitor, i arm is the current flowing into the sub-module, which can be equivalent to the arm current of the MMC, u C0 and u esr are the voltages of the ideal capacitor and ESR equivalent to the sub-module capacitor, and u C is the voltage of the sub-module capacitor.

[0110] Specifically, the process of obtaining the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module may include:

[0111] S1101: Detect the first capacitance voltage value of the sub-module capacitor of the MMC at the previous sampling moment of the positive edge transition, the second capacitance voltage value at the subsequent sampling moment of the positive edge transition, and the first arm current value.

[0112] Specifically, the schematic diagram of the current-voltage waveform of the sub-module is as Figure 4As shown. Continuously detect the capacitor voltage and arm current of the sub-module, and monitor whether the voltage and current have positive or negative jumps. If a positive or negative jump occurs, record the time and the voltage and current at that time.

[0113] S1202. Detect the third capacitor voltage value at the sampling time before the negative jump edge of the capacitor voltage of the sub-module, and the fourth capacitor voltage value and the second arm current value at the sampling time after the negative jump edge.

[0114] Step S120. Monitor the resistance value of the equivalent series resistance in the sub-module through the capacitor voltage value and the arm current value.

[0115] Specifically, the resistance value of the equivalent series resistance in the sub-module can be calculated by using the first capacitor voltage value, the second capacitor voltage value, the first arm current value, the third capacitor voltage value, the fourth capacitor voltage value, and the second arm current value:

[0116]

[0117] Among them, is the resistance value of the equivalent series resistance in the sub-module, is the first capacitor voltage value, is the second capacitor voltage value, is the first arm current value, is the third capacitor voltage value, is the fourth capacitor voltage value, is the second arm current value.

[0118] Step S130. If the resistance value of the equivalent series resistance is higher than the preset resistance value, determine that the capacitor of the sub-module fails.

[0119] Specifically, the preset resistance value can be between 2 times and 3 times the initial resistance value of the equivalent series resistance. It can be understood that when the equivalent series resistance increases to 2 - 3 times its initial value, it can be considered that the capacitor has failed.

[0120] Step S140. Perform fault tolerance control on the sub-module through the voltage equalization and circulating current suppression algorithm, output three-phase switching signals, and apply the three-phase switching signals to the MMC.

[0121] The MMC fault handling method provided in this embodiment monitors the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module. Among them, the MMC includes six arms in three phases, each arm includes several sub-modules, and the capacitors of each sub-module are connected in series with equivalent series resistors. Further, by using the capacitance voltage value and the arm current value, the resistance value of the equivalent series resistor in the sub-module is monitored. If the resistance value of the equivalent series resistor is higher than the preset resistance value, it is determined that the capacitor of the sub-module fails. Fault tolerance control is performed on the sub-module through the voltage equalization and circulating current suppression algorithms, three-phase switching signals are output, and the three-phase switching signals are applied to the MMC. Thus, it can be seen that through the circulating current suppression strategy, the fundamental frequency component and the second harmonic component of the circulating current caused by fault tolerance control after a fault can be eliminated, the effect of circulating current suppression can be achieved, and the stability of the system during fault operation can be improved.

[0122] Further, it is not necessary to add additional sensors to monitor the resistance value of the equivalent series resistor in real time, which is more efficient and convenient compared with the traditional method using additional sensors.

[0123] In some embodiments of the present application, the voltage equalization and fault handling strategy of the MMC sub-module in the above embodiment are introduced. The implementation process of this strategy may include:

[0124] S1. If sub-modules on the arm of the target phase of the MMC fail, it is determined that the peak output voltage of the sub-modules on the arm of the target phase is:

[0125]

[0126] Among them, is the total number of sub-modules on the arm of the target phase, is the capacitance voltage value of the sub-modules on the arm of the target phase that do not fail.

[0127] S2. Determine that the peak output voltage of the lower arm of the target phase is:

[0128] .

[0129] S3. Lift the voltage of the sub-modules on the arm of the target phase that do not fail. After the sub-module failures occur, determine the capacitance voltage reference value of the sub-modules that do not fail as:

[0130]

[0131] Among them, is the default reference value of the sub-module capacitance voltage.

[0132] S4. After performing fault tolerance control on the sub-modules of the arm on the target phase, determine that the upper limit value of the sub-modules that allow faults on the arm on the target phase is:

[0133]

[0134] where is the maximum withstand voltage of the sub-module capacitor voltage of the MMC.

[0135] Furthermore, introduce the process of performing fault tolerance control on the sub-modules through the voltage equalization and circulating current suppression algorithms and outputting three-phase switching signals mentioned in the foregoing embodiments. Specifically, it may include:

[0136] S1401. Calculate the circulating current reference value using the following formula:

[0137]

[0138] where is the proportional coefficient, is the integral coefficient, 1 / s is the integral link, is the average value of the capacitor voltages of all sub-modules in one phase of the MMC, is the capacitor voltage reference value of the non-faulty sub-modules in the one phase.

[0139] S1402. Input the circulating current reference value into a notch filter for processing and perform deadbeat current tracking to obtain the inductor voltage of the upper arm and the inductor voltage of the lower arm of the one phase.

[0140] Specifically, the basic idea of the deadbeat control strategy is: According to the given system state equation, combined with the output feedback quantity of the system and the output reference value required for the next control period, the control quantity for the next control period can be calculated. When the deadbeat control strategy is applied to the MMC system, it can achieve the tracking of the actual arm current to the reference current, that is, i * (K)=i(K + 1). As Figure 5 shown, Figure 5 shows the specific control block diagram of the deadbeat circulating current control strategy.

[0141] where the inductor voltage of the upper arm is:

[0142]

[0143] where is the arm inductor, is the control period duration, is the AC side current reference value of the j-th phase of the MMC, is the current of the upper arm of the j-th phase at the k-th control period.

[0144] The lower-arm inductor voltage is as follows:

[0145]

[0146] Wherein, is the lower-arm current of the j-th phase at the K-th control period.

[0147] S1403. Modulate the upper-arm inductor voltage to obtain the upper-arm reference voltage of the MMC as follows:

[0148]

[0149] Wherein, is the DC bus voltage of the MMC, is the arm reference voltage of the MMC under normal operating conditions.

[0150] S1404. Modulate the lower-arm inductor voltage to obtain the lower-arm reference voltage of the MMC as follows:

[0151] .

[0152] S1405. Output three-phase switching signals according to the upper-arm reference voltage and the lower-arm reference voltage.

[0153] It can be understood that through the fault handling with a circulating current suppression link, the stability of the asymmetric operation of the MMC arm sub-modules is ensured, the fault tolerance of the system is improved, and the operation reliability is enhanced.

[0154] Next, the device for implementing the MMC sub-module-based fault handling provided in the embodiments of the present application will be described. The device for implementing the MMC sub-module-based fault handling described below can be correspondingly referred to the method for implementing the MMC sub-module-based fault handling described above.

[0155] Referring to Figure 6 , Figure 6 is a schematic structural diagram of a device for implementing the MMC sub-module-based fault handling disclosed in the embodiments of the present application.

[0156] As Figure 6 shown, the device may include:

[0157] A sub-module electrical value acquisition unit 11, configured to acquire the capacitor voltage value of the sub-module of the MMC and the arm current value of the sub-module. Wherein, the MMC includes three phases with a total of six arms, each arm includes a plurality of sub-modules, and the capacitor of each sub-module is connected in series with an equivalent series resistance;

[0158] The equivalent series resistance monitoring unit 12 is used to monitor the resistance value of the equivalent series resistance in the sub-module based on the capacitance voltage value and the arm current value.

[0159] The sub-module capacitance failure determination unit 13 is used to determine that the capacitance of the sub-module fails if the resistance value of the equivalent series resistance is higher than a preset resistance value.

[0160] The fault handling unit 14 is used to perform fault tolerance control on the sub-module through the voltage equalization and circulating current suppression algorithms, output three-phase switching signals, and apply the three-phase switching signals to the MMC.

[0161] Optionally, the sub-module electrical value acquisition unit includes:

[0162] The first sub-module electrical value acquisition sub-unit is used to detect the first capacitance voltage value at the previous sampling moment of the positive edge of the capacitance voltage of the sub-module of the MMC, as well as the second capacitance voltage value and the first arm current value at the next sampling moment of the positive edge.

[0163] The second sub-module electrical value acquisition sub-unit is used to detect the third capacitance voltage value at the previous sampling moment of the negative edge of the capacitance voltage of the sub-module, as well as the fourth capacitance voltage value and the second arm current value at the next sampling moment of the negative edge.

[0164] Optionally, the equivalent series resistance monitoring unit includes:

[0165] The equivalent series resistance monitoring sub-unit is used to calculate the resistance value of the equivalent series resistance in the sub-module according to the following formula based on the first capacitance voltage value, the second capacitance voltage value, the first arm current value, the third capacitance voltage value, the fourth capacitance voltage value, and the second arm current value:

[0166]

[0167] Wherein, is the resistance value of the equivalent series resistance in the sub-module, is the first capacitance voltage value, is the second capacitance voltage value, is the first arm current value, is the third capacitance voltage value, is the fourth capacitance voltage value, is the second arm current value.

[0168] Optionally, the device further includes:

[0169] The sub-module output voltage peak value determination unit is used to if there is an arm on the target phase of the MMC If a sub-module fails, the peak value of the output voltage of the sub-module of the arm on the target phase is determined as:

[0170]

[0171] Where is the total number of sub-modules of the arm on the target phase, is the capacitance voltage value of the sub-module that has not failed in the arm on the target phase;

[0172] The lower-arm output voltage peak determination unit is used to determine the peak value of the output voltage of the lower arm of the target phase as:

[0173] .

[0174] Optionally, the device further includes:

[0175] The capacitance voltage reference value determination unit is used to boost the voltage of the sub-module that has not failed in the arm on the target phase. After the failure of sub-modules occurs, the capacitance voltage reference value of the sub-module that has not failed is determined as:

[0176]

[0177] Where is the default reference value of the sub-module capacitance voltage;

[0178] The faulty sub-module upper limit value determination unit is used to determine the upper limit value of the faulty sub-module allowed in the arm on the target phase after performing fault tolerance control on the sub-module of the arm on the target phase as:

[0179]

[0180] Where is the maximum withstand voltage value of the sub-module capacitance voltage of the MMC.

[0181] Optionally, the fault response unit includes:

[0182] The circulating current reference value calculation unit is used to calculate the circulating current reference value by the following formula:

[0183]

[0184] Where is the proportionality coefficient, is the integral coefficient, 1 / s is the integral link, is the average value of the capacitance voltages of all sub-modules of one of the phases in the MMC, is the capacitance voltage reference value of the sub-module that has not failed in the one phase;

[0185] The arm inductance voltage determination unit is configured to input the circulating current reference value into a notch filter for processing and perform deadbeat current tracking to obtain the upper-arm inductance voltage and the lower-arm inductance voltage of one of the phases. The upper-arm inductance voltage is:

[0186]

[0187] Wherein, is the arm inductance, is the control cycle duration, is the AC-side current reference value of the j-th phase of the MMC, is the upper-arm current of the j-th phase at the k-th control cycle;

[0188] The lower-arm inductance voltage is:

[0189]

[0190] Wherein, is the lower-arm current of the j-th phase at the K-th control cycle;

[0191] The first modulation unit is configured to modulate the upper-arm inductance voltage to obtain the upper-arm reference voltage of the MMC as:

[0192]

[0193] Wherein, is the DC bus voltage of the MMC, is the arm reference voltage of the MMC under normal operating conditions;

[0194] The second modulation unit is configured to modulate the lower-arm inductance voltage to obtain the lower-arm reference voltage of the MMC as:

[0195]

[0196] The three-phase switch signal output unit is configured to output three-phase switch signals according to the upper-arm reference voltage and the lower-arm reference voltage.

[0197] The MMC sub-module-based fault handling device provided in the embodiments of the present application can be applied to MMC sub-module-based fault handling equipment, such as terminals: mobile phones, computers, etc. Optionally, Figure 7 shows the hardware structure block diagram of the MMC sub-module-based fault handling equipment. Referring to Figure 7 , the hardware structure of the MMC sub-module-based fault handling equipment may include: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4;

[0198] In the embodiments of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete the communication with each other through the communication bus 4;

[0199] The processor 1 may be a central processing unit (CPU), or a specific integrated circuit (ASIC) (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention, etc.;

[0200] The memory 3 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), etc., such as at least one disk memory;

[0201] Wherein, the memory stores a program, and the processor can call the program stored in the memory, and the program is used for:

[0202] Obtain the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module, wherein the MMC includes three phases with a total of six arms, each arm includes several sub-modules, and the capacitors of each sub-module are connected in series with an equivalent series resistance;

[0203] Monitor the resistance value of the equivalent series resistance in the sub-module through the capacitance voltage value and the arm current value;

[0204] If the resistance value of the equivalent series resistance is higher than a preset resistance value, it is determined that the capacitor of the sub-module fails;

[0205] Perform fault tolerance control on the sub-module through an equal voltage sharing and circulating current suppression algorithm, output three-phase switching signals, and apply the three-phase switching signals to the MMC.

[0206] Optionally, the refined functions and extended functions of the program can be referred to the above description.

[0207] The embodiments of the present application further provide a storage medium, which can store a program suitable for execution by a processor, and the program is used for:

[0208] Obtain the capacitance voltage value of the sub-module of the MMC and the arm current value of the sub-module, wherein the MMC includes three phases with a total of six arms, each arm includes several sub-modules, and the capacitors of each sub-module are connected in series with an equivalent series resistance;

[0209] Monitor the resistance value of the equivalent series resistance in the sub-module through the capacitance voltage value and the arm current value;

[0210] If the resistance value of the equivalent series resistance is higher than the preset resistance value, it is determined that the capacitor of the sub-module fails.

[0211] Perform fault tolerance control on the sub-module through the voltage equalization and circulating current suppression algorithm, output three-phase switching signals, and apply the three-phase switching signals to the MMC.

[0212] Optionally, the refinement function and expansion function of the program can be referred to the above description.

[0213] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0214] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0215] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MMC submodule-based fault handling method, characterized in that: include: Obtaining the capacitor voltage value of the submodule of the MMC and the bridge arm current value of the submodule, wherein the MMC comprises three phases and six bridge arms, each bridge arm comprises a number of submodules, and the capacitor of each submodule is connected in series with an equivalent series resistor; Monitoring the resistance value of the equivalent series resistance in the submodule through the capacitor voltage value and the bridge arm current value; If the resistance of the equivalent series resistance is higher than the preset resistance, it is determined that the capacitor of the submodule fails; The submodule is subjected to fault-tolerant control through voltage balancing and circulating current suppression algorithms, a three-phase switch signal is output, and the three-phase switch signal is applied to the MMC.

2. The method according to claim 1, characterized in that Obtaining the capacitor voltage value of the submodule of the MMC and the bridge arm current value of the submodule, including: Detecting a first capacitor voltage value of a capacitor voltage of a submodule of the MMC at a sampling time before a positive transition edge, and a second capacitor voltage value and a first bridge arm current value at a sampling time after the positive transition edge; The third capacitor voltage value of the capacitor voltage of the submodule at a sampling time before the negative transition edge, and the fourth capacitor voltage value and the second bridge arm current value at a sampling time after the negative transition edge are detected.

3. The method according to claim 2, characterized in that Monitoring the resistance value of the equivalent series resistance in the submodule by using the capacitor voltage value and the bridge arm current value includes: The resistance value of the equivalent series resistance in the submodule is calculated using the following formula according to the first capacitor voltage value, the second capacitor voltage value, the first bridge arm current value, the third capacitor voltage value, the fourth capacitor voltage value and the second bridge arm current value: in, is the resistance value of the equivalent series resistance in the submodule, is the first capacitor voltage value, is the second capacitor voltage value, is the first bridge arm current value, is the third capacitor voltage value, is the fourth capacitor voltage value, is the current value of the second bridge arm.

4. The method according to claim 1, characterized in that: Also includes: If the bridge arm on the target phase of the MMC has If a submodule fails, the submodule output voltage peak value of the bridge arm on the target phase is determined to be: in, is the total number of submodules of the bridge arm on the target phase, is the submodule capacitor voltage value of the bridge arm on the target phase where no fault occurs; The output voltage peak value of the lower bridge arm of the target phase is determined as: 。 5. The method according to claim 4, characterized in that Also includes: The voltage of the submodule of the bridge arm of the target phase that has not failed is raised. After a submodule failure occurs, the capacitor voltage reference value of the submodule that has not failed is determined as: in, It is the default reference value of the submodule capacitor voltage; After performing fault-tolerant control on the submodules of the bridge arm on the target phase, the upper limit value of the submodules of the bridge arm on the target phase that can be allowed to fail is determined as: in, is the maximum withstand voltage value of the submodule capacitor voltage of the MMC.

6. The method according to claim 1, characterized in that The method of performing fault-tolerant control on the submodules through voltage balancing and circulating current suppression algorithms and outputting three-phase switch signals includes: The circulating current reference value is calculated using the following formula: in, is the proportionality coefficient, is the integral coefficient, 1 / s is the integral link, is the average value of the capacitor voltages of all submodules of one phase in the MMC, is a capacitor voltage reference value of a submodule in one of the phases where no fault occurs; The circulating current reference value is input into the trap filter for processing and deadbeat current tracking is performed to obtain the upper bridge arm inductor voltage and the lower bridge arm inductor voltage of one of the phases, and the upper bridge arm inductor voltage is: in, is the bridge arm inductance, To control the cycle length, is the reference value of the j-phase AC side current of the MMC, is the upper arm current of the jth phase in the kth control cycle; The lower bridge arm inductor voltage is: in, is the lower bridge arm current of the jth phase in the Kth control cycle; The upper bridge arm inductor voltage is modulated to obtain the upper bridge arm reference voltage of the MMC: in, is the DC bus voltage of the MMC, is the bridge arm reference voltage of the MMC under normal working conditions; The lower bridge arm inductor voltage is modulated to obtain the lower bridge arm reference voltage of the MMC: A three-phase switching signal is output according to the upper bridge arm reference voltage and the lower bridge arm reference voltage.

7. A MMC submodule-based fault handling device, characterized in that: include: A submodule electrical value acquisition unit, used to acquire the capacitor voltage value of the submodule of the MMC and the bridge arm current value of the submodule, wherein the MMC comprises three phases and six bridge arms, each bridge arm comprises a number of submodules, and the capacitor of each submodule is connected in series with an equivalent series resistor; An equivalent series resistance monitoring unit, used to monitor the resistance value of the equivalent series resistance in the submodule through the capacitor voltage value and the bridge arm current value; A submodule capacitor failure determination unit, configured to determine that the capacitor of the submodule has failed if the resistance of the equivalent series resistor is higher than a preset resistance; The fault response unit is used to perform fault-tolerant control on the submodule through voltage balancing and circulating current suppression algorithms, output a three-phase switch signal, and apply the three-phase switch signal to the MMC.

8. The device according to claim 7, characterized in that The submodule electrical value acquisition unit includes: The first submodule electrical value acquisition subunit is used to detect a first capacitor voltage value of the capacitor voltage of the submodule of the MMC at a sampling time before the positive jump edge, and a second capacitor voltage value and a first bridge arm current value at a sampling time after the positive jump edge; The second submodule electrical value acquisition subunit is used to detect the third capacitor voltage value of the capacitor voltage of the submodule at a sampling moment before the negative jump edge, and the fourth capacitor voltage value and the second bridge arm current value at a sampling moment after the negative jump edge.

9. An MMC submodule-based fault handling device, characterized in that: including memory and processor; The memory is used to store programs; The processor is used to execute the program to implement each step of the MMC sub-module-based fault handling method as described in any one of claims 1 to 6.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the MMC sub-module-based fault handling method as claimed in any one of claims 1 to 6 is implemented.

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