Test system and method, electronic equipment, storage medium and product

Abstract

The invention discloses a testing system and method, electronic equipment, a storage medium and a product, and relates to the technical field of testing, and the testing system comprises a to-be-tested board, the electronic equipment and a conversion device; the to-be-tested board is in communication connection with the electronic equipment, and the to-be-tested board is provided with a memory disk slot; the electronic equipment is in communication connection with the conversion device and is used for sending a debugging instruction; the conversion device is connected with the to-be-tested board through the memory disk slot, the conversion device is used for converting the preset memory into a target memory disk according to the debugging instruction so as to test the to-be-tested board, and the target memory disk is a computing high-speed interconnection memory disk. The technical problem that the cost is high in the prior art is solved, the preset memory is converted into the computing high-speed interconnection memory, and the to-be-tested board is tested by using the target memory disk, so that the technical effect of reducing the production test cost during the production test is achieved.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and in particular, to a testing system, method, electronic device, storage medium, and product. Background Art

[0002] In related testing solutions, during the production testing of the backplane, a computing high-speed interconnect memory disk is required. However, the computing high-speed interconnect memory disk is expensive, and during the production testing process, the DUT (Device Under Test) board needs to be continuously replaced, and the memory disk needs to be continuously plugged and unplugged, resulting in high production testing costs. Summary of the Invention

[0003] This application provides a testing system, method, electronic device, storage medium, and product to at least solve the problem of high production testing costs caused by using a computing high-speed interconnect memory disk for production testing in related technologies.

[0004] This application provides a testing system, including a DUT board, an electronic device, and a conversion device; The DUT board is communicatively connected to the electronic device, and a memory disk slot is provided on the DUT board; The electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; The conversion device is connected to the DUT board through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instruction to test the DUT board, and the target memory disk is a computing high-speed interconnect memory disk.

[0005] This application provides a testing method, which is applied to the testing system and includes: In response to the testing system forming a loop, power on and test the target DUT board; In response to the completion of the test of the target DUT board, power off and shut down.

[0006] This application also provides a testing device, including: A testing unit, configured to power on and test the target DUT board in response to the testing system forming a loop; A power-off unit, configured to power off and shut down in response to the completion of the test of the target DUT board.

[0007] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above testing methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of any of the above testing methods.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above test methods when executed by a processor.

[0010] Through the present application, the test system includes a board under test, an electronic device, and a conversion device; the board under test is communicatively connected to the electronic device, and a memory disk slot is provided on the board under test; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; the conversion device is connected to the board under test through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instruction to test the board under test, and the target memory disk is a compute express link memory disk, which solves the technical problem of high cost in using a compute express link memory for testing during the production test process in the related solution. By converting the preset memory into a compute express link memory and using the target memory disk to test the board under test, the technical effect of reducing the production test cost during the production test is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts.

[0012] Figure 1 It is a schematic structural diagram of a test system provided by an embodiment of the present application; Figure 2 It is a schematic structural diagram of a test system provided by an embodiment of the present application; Figure 3 It is a schematic structural diagram of a test system provided by an embodiment of the present application; Figure 4 It is a schematic flowchart of a test method provided by an embodiment of the present application; Figure 5 It is a schematic flowchart of a test method provided by an embodiment of the present application; Figure 6 It is a schematic structural diagram of a test device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the protection scope of the present application.

[0014] It should be noted that in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] To facilitate a better understanding of the technical solutions described in the embodiments of the present disclosure by those skilled in the art, before introducing the embodiments of the present disclosure, the following explanations are made for the technical terms in the embodiments of the present disclosure.

[0016] Compute Express Link (CXL): It is an open industry standard for high-bandwidth and low-latency device interconnection, allowing fast and reliable data transmission between different components within a computer system, aiming to solve bottleneck problems in high-performance computing, including memory capacity, memory bandwidth, and input / output latency, etc. CXL can also achieve memory expansion and memory sharing, and can communicate with computing accelerators such as Graphics Processing Unit (GPU), Field-Programmable Gate Array (FPGA), etc., providing a faster and more flexible way of data exchange and processing.

[0017] Complex Programmable Logic Device (CPLD): CPLD allows the functions of digital circuits to be realized through software programming, has a high degree of integration and flexibility, and is suitable for application scenarios that require fast response times, such as signal processing, protocol conversion, etc.

[0018] E3.S interface: E3.S is a standard form factor interface designed specifically for data center and enterprise-level applications, and is part of the EDSFF (Enterprise&Data Center SSD Form Factor) standard. It is mainly used for servers and storage devices. The E3.S interface supports NVMe2.0 and PCIe5.0 technologies.

[0019] Peripheral Component Interconnect Express (PCIe): It is used to connect various external devices such as graphics cards, Solid State Drives (SSDs), network cards, etc.

[0020] Electrically Erasable Programmable Read-Only Memory (EEPROM): It is a non-volatile memory (Non-Volatile Memory, NVM), that is, the data will not be lost after power-off.

[0021] Dual In-line Memory Module (DIMM) interface is a standard physical interface for installing and connecting Dynamic Random Access Memory (DRAM) chips, which is widely used in computer systems such as desktops, laptops, and servers.

[0022] Multi-Channel I / O Cable (MCIO): It is a high-speed data transmission cable used in high-performance computing environments, supporting multi-channel parallel transmission and the latest PCIe standard. It plays an important role in modern data centers, servers, and storage systems, especially in application scenarios that require high bandwidth and low latency.

[0023] Serial Peripheral Interface (SPI): SPI is a high-speed synchronous serial communication interface standard, mainly used for short-distance inter-chip communication. It uses four lines and can connect one master device to multiple slave devices.

[0024] CXL is a dynamic multi-protocol technology designed to support accelerators and memory devices. CXL provides a rich set of protocols, including input / output semantics similar to PCIe (i.e., CXL.io), cache protocol semantics (i.e., CXL.cache), and memory access semantics on discrete or packet links (i.e., CXL.mem). CXL.io is required for discovery and enumeration, error reporting, point-to-point access to CXL memory, and host physical address lookup. The CXL.cache and CXL.mem protocols can be selectively implemented by specific accelerator or memory device usage models. CXL provides a low-latency, high-bandwidth path for accelerator access to the system and system access to memory connected to CXL devices.

[0025] CXL memory disk is a DRAM module based on the CXL interface, which can enable server systems to significantly expand their memory capacity and bandwidth.

[0026] CXL backplane, like a traditional hard disk backplane, is connected to the motherboard through MCIO cables, but instead of traditional hard disks, CXL memory disks are connected to it.

[0027] In recent years, the development of technologies such as artificial intelligence, machine learning, and cloud computing has given rise to a vast amount of data. With the rise of data-driven technologies, there has also been a corresponding demand for more powerful computer hardware architectures. To create powerful processors, more and more cores are integrated on a single processor chip to meet the processing and performance requirements of data-intensive applications. However, the memory bandwidth and capacity have not kept pace with the growth of the number of Central Processing Unit (CPU) cores, resulting in a gap between processor and memory performance.

[0028] The unmet demands for memory capacity and bandwidth are driving the breakthrough of existing memory technologies. Due to the limitations of existing conventional DRAM designs, it is difficult to expand memory capacity beyond a certain level, so new memory interface technologies are needed. In addition, the rise of artificial intelligence and big data has promoted the trend of heterogeneous computing, where multiple different types of processors can process large amounts of data in parallel.

[0029] In view of such trends, it is necessary to develop next-generation interconnect technologies for heterogeneous computing and composite infrastructures to achieve efficient resource utilization.

[0030] CXL is an open interconnect standard developed by the CXL™ Consortium, which is a high-speed, low-latency CPU-to-device interconnect technology based on the PCIe physical layer. CXL can provide an efficient connection between the host CPU and interconnected devices (such as accelerators and memory expansion devices). CXL memory disks and backplanes were born in this context. During the production testing process of CXL backplanes, CXL memory disks are required. However, CXL memory disks are expensive, and during the production testing process, the boards need to be continuously changed and the memory disks need to be continuously plugged and unplugged, making CXL memory disks a consumable for production testing, which results in high production testing costs. Therefore, we must have a device and method to reduce this production testing cost.

[0031] During the production testing process of devices based on the CXL architecture, the diagnostic testing of CXL backplanes is a key link. Due to the high bandwidth and low latency characteristics of CXL, its testing usually requires relying on high-performance CXL memory disks (such as CXL SSDs or CXL DRAM modules) to simulate real application scenarios and verify the signal integrity, protocol compatibility, and stability of the backplane.

[0032] In related test schemes, the production testing process faces the following challenges: First of all, CXL memory disks are expensive. As an emerging technology, its related hardware has not been widely popularized, resulting in a relatively high unit price of CXL memory disks, usually ranging from several thousand to tens of thousands of yuan.

[0033] Secondly, frequent plugging and unplugging leads to wear and tear. During production testing, each CXL backplane needs to be tested independently, and the CXL memory disk needs to be repeatedly plugged and unplugged to adapt to different test items or replace the board under test. Such mechanical operations are likely to cause physical wear of the CXL connectors (such as PCIe5.0 / 6.0 interfaces), and even damage the gold fingers or firmware of the memory disk, further shortening its service life.

[0034] Thirdly, the testing efficiency is low. The operation of manually replacing the memory disk is time-consuming and may introduce interference factors such as poor contact, affecting the consistency and reliability of the test.

[0035] These problems make the CXL memory disk a high-value consumable in production testing, significantly driving up the overall production cost. Taking a certain production line as an example, if 100 backplanes are tested every day, the loss cost of only the CXL memory disk may reach hundreds of thousands of yuan per year.

[0036] Through the present application, the test system includes a board under test, an electronic device, and a conversion device; the board under test is communicatively connected to the electronic device, and a memory disk slot is provided on the board under test; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board under test through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instructions to test the board under test, and the target memory disk is a Compute Express Link (CXL) memory disk, solving the technical problem of high cost in the related solutions when using CXL memory for testing during the production testing process. By converting the preset memory into CXL memory and using the target memory disk to test the board under test, the technical effect of reducing the production testing cost during production testing is achieved.

[0037] The present application can convert ordinary memory into a CXL interface so that it can be connected to a CXL backplane and can work normally like a CXL memory disk. Moreover, only the gold finger interface part of the CXL memory disk is worn during the production testing process, and the gold finger interface part is convenient to replace, greatly reducing the production testing cost.

[0038] A test system and method provided by an embodiment of the present disclosure can be applied to the production testing, debugging, and verification of any device and system using CXL memory disks.

[0039] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the following further describes the present application in detail with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1 It is a schematic structural diagram of a test system provided by an embodiment of the present disclosure.

[0041] As Figure 1 shown, the system includes a board under test, an electronic device, and a conversion device; The board under test is communicatively connected to an electronic device, and a memory disk slot is provided on the board under test; The electronic device is communicatively connected to a conversion device, and the electronic device is configured to send a debugging instruction; The conversion device is connected to the board under test through the memory disk slot, and the conversion device is configured to convert a preset memory into a target memory disk according to the debugging instruction to test the board under test, and the target memory disk is a Compute Express Link (CXL) memory disk.

[0042] In some embodiments, the board under test refers to a hardware device that needs to be functionally verified or performance tested, usually a motherboard or backplane including a memory expansion interface.

[0043] In some embodiments, the board under test and the electronic device are communicatively connected through an MCIO cable, supporting PCIe5.0 signal transmission.

[0044] In some embodiments, the number of memory disk slots can be one, two, or more, and the present application does not limit the number of memory disk slots provided on the board under test.

[0045] In some embodiments, the memory disk slot is an interface for inserting a storage module (such as an SSD, CXL memory disk), and common forms include the E3.S interface, U.2 interface, and M.2 interface. Among them, taking the memory disk slot as the E3.S as an example, the E3.S interface is connected to the board under test through a gold finger plug-in to transmit CXL protocol signals.

[0046] In some embodiments, the electronic device is a master device for controlling and monitoring the test process, and the electronic device is usually a server or a dedicated controller. In the present application, a server is taken as an example.

[0047] In some embodiments, the conversion device is a hardware device for simulating a specific protocol memory.

[0048] In some embodiments, the conversion device is compatible with the CXL protocol standard (such as CXL 2.0) and supports being recognized as a compliant CXL device in a server system.

[0049] In some embodiments, the preset memory refers to a data source memory pre-specified by the system, usually a standard Double Data Rate 5 (DDR5) memory module, that is, ordinary memory.

[0050] In some embodiments, the target memory disk refers to the target type to be finally simulated or replaced. In the present application, the target memory disk is a Compute Express Link (CXL) memory, that is, a CXL memory, which conforms to the CXL.mem protocol.

[0051] In some embodiments, power is taken from the 5V pin of the E3.S interface by default.

[0052] In some embodiments, 5V can be converted to voltages such as 3.3V or 1.8V through a direct current to direct current (DC-DC) module for use by the conversion device.

[0053] In some embodiments, by converting to voltages such as 3.3V or 1.8V through a DC-DC module, a variety of input voltage ranges are supported, and the power supply environment of different platforms can be adapted.

[0054] Through the present application, the test system includes a board under test, an electronic device, and a conversion device; the board under test is communicatively connected to the electronic device, and a memory disk slot is provided on the board under test; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; the conversion device is connected to the board under test through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instruction to test the board under test, and the target memory disk is a compute express link (CXL) memory disk, which solves the technical problem of high cost in using CXL memory for testing during the production test process in related solutions. By converting the preset memory into a CXL memory and using the target memory disk to test the board under test, the technical effect of reducing the production test cost during the production test is achieved.

[0055] In some embodiments, the conversion device includes a target chip, a control module, a memory module, and a debugging module; The target chip is communicatively connected to the board under test through a first preset interface; The control module is communicatively connected to the target chip, and the control module is used to monitor the state of the target chip, and the state of the target chip includes at least one of the temperature of the target chip and the link rate of the target chip; The memory module is communicatively connected to the target chip through a second preset interface, and the memory module is used to store data; The debugging module is communicatively connected to the control module, and the debugging module is communicatively connected to the electronic device through a third preset interface. The debugging module is used to convert the debugging instruction into a serial communication signal and transmit it to the control module.

[0056] In some embodiments, the conversion device converts a memory in one physical form or protocol (such as DDR5) into a memory device with another protocol standard, such as a CXL memory, for verifying the function and performance of the board under test without using a native CXL memory, so as to reduce the cost of production testing.

[0057] In some embodiments, the target chip implements PCIe-to-CXL protocol conversion, maps the PCIe signals of the DIMM memory to the CXL.mem protocol, and interacts with the server through the E3.S interface to control functions such as link training, data transmission, and cache coherence.

[0058] In some embodiments, the control module is typically composed of a microcontroller unit (MCU), FPGA, or CPLD, and is responsible for monitoring the status of the target chip, such as temperature, voltage, link rate, etc., processing instructions from the debugging module, and coordinating communication between modules. In addition, the control module also supports remote firmware upgrade through a Universal Serial Bus (USB) interface (without physical disassembly).

[0059] In some embodiments, the memory module is typically a standard DDR5 DIMM memory module, providing a data source that is converted into the target memory disk, supporting high-speed access, and adapting to the bandwidth requirements of the PCIe / CXL protocol.

[0060] In some embodiments, the debugging module typically uses a USB-UART bridge (such as FT232, CP210x) to receive debugging instructions sent by an electronic device (such as a server), convert the instructions into serial communication signals, such as Universal Asynchronous Receiver / Transmitter (UART), Inter-Integrated Circuit (I²C), SPI, and send them to the control module, which can be used for operations such as firmware update, log collection, status query, and real-time monitoring.

[0061] In some embodiments, the first preset interface is typically E3.S, U.2, PCIe x4 / x8, etc., which is used to achieve high-speed communication between the target chip and the board under test, support the PCIe / CXL protocol, ensure the stability of the data link, and is inserted into the memory disk slot of the board under test.

[0062] In some embodiments, the second preset interface is typically a DIMM interface, supporting standard DDR4 / DDR5 memory modules, Low Power Double Data Rate (LPDDR) interfaces, etc., which is used to connect the memory module to the target chip, read and write actual memory data, and the data is sent to the target chip through this interface for protocol conversion.

[0063] In some embodiments, the memory capacity and speed are dynamically adapted to the target chip, i.e., the CXL chip, with a maximum support of 128GB per single strip, indicating that the system supports a maximum single memory module capacity of 128GB in hardware design. This limitation mainly depends on the address bus width of the target chip, the memory controller capabilities of the conversion device, and whether the basic input / output system / firmware supports large-capacity memory mapping. Specifically, it can vary depending on the CXL protocol version. Specifically, the memory capacity can be 8GB, 16GB, 32GB, 64GB, 128GB, etc.; the memory speed, i.e., the data transfer speed of the memory, such as DDR5-4800, DDR5-5600, DDR5-6400, etc., indicates that the system can automatically identify and adjust the working parameters of the target chip according to the capacity and speed of the currently used memory module (such as DDR5), enabling it to be compatible with memory modules of different specifications.

[0064] In some embodiments, the third preset interface is usually a USB interface, UART interface, RS232 interface, JTAG interface, etc. The debugging module is connected to an electronic device, such as a server, through this interface, and is used to send debugging instructions and obtain status information, and is commonly used in automated test scenarios such as attention command (AT) debugging and Python script control.

[0065] In some embodiments, the conversion device further includes a power module; The power module is communicatively connected to a power adapter through a fourth preset interface, and the power adapter is used to supply power to the conversion device.

[0066] In some embodiments, an external 5V to 12V power adapter can be optionally connected to cope with high-power consumption scenarios, such as later expanding the load of multiple memory strips.

[0067] In some embodiments, the fourth preset interface refers to a reserved physical or logical interface for connecting the power module in the conversion device to the power adapter.

[0068] In some embodiments, the type of the fourth preset interface can be a USB Type-A / Type-C, a dedicated DC power interface, or a PCIe 12V power supply interface. Among them, the USB Type-A / Type-C is suitable for low-power consumption scenarios, and the PCIe 12V power supply interface is suitable for high-power CXL simulation.

[0069] In some embodiments, the power module refers to a circuit module responsible for providing stable voltage and current to the entire conversion device. This module may include a DC-DC converter, a voltage regulator circuit, a power management unit, and an input filter protection circuit. Among them, the DC-DC converter is used for buck / boost conversion to provide the required voltage for the conversion device.

[0070] In some embodiments, the power adapter is an external power supply device for converting mains power into a low-voltage DC power supply suitable for use by an electronic device, such as 12V, 5V, 3.3V, so as to provide a continuous and stable power supply for the conversion device.

[0071] In some embodiments, in order to avoid the E3.S / U.2 slot of the server or motherboard being unable to provide sufficient power to drive a high-performance target chip and a large-capacity memory module, and to ensure that the conversion device can obtain sufficient power support independently of the host device (such as a server), in this application, the power module in the conversion device is connected to an external power adapter through a specific interface to ensure the stability and compatibility of the system operation.

[0072] In some embodiments, the conversion device further includes a cache module; The cache module is communicatively connected to the target chip, and the cache module is used to store the firmware and configuration parameters of the conversion device, and the configuration parameters include at least one of a device identifier and a link training mode.

[0073] In some embodiments, the cache module stores the device firmware and configuration parameters, such as the device ID and the link training mode, for loading when the CXL chip is started.

[0074] In some embodiments, the cache module can be an EEPROM, a non-volatile memory, a ferroelectric memory, or a static random access memory with power-down protection.

[0075] In some embodiments, the firmware refers to the underlying program running on the target chip, which can include a protocol stack, such as the conversion logic of PCIe and CXL.mem, an initialization process, an error handling mechanism, and a driver interface, etc.

[0076] In some embodiments, the configuration parameters refer to a set of parameters for customizing the system. Among them, the device identifier is used to identify the identity information of the conversion device, and the link training mode defines the training strategy used when the link is established, such as Gen3, Gen4, Gen5 rate matching, default voltage / frequency setting, and user-defined flag bits, etc.

[0077] In some embodiments, the number of conversion devices is determined by the number of memory disk slots on the board under test.

[0078] In some embodiments, as Figure 2 shown, Figure 2 is a schematic structural diagram of a test system provided by an embodiment of this application. Figure 2 In it, the conversion device is installed on the E3.S interface of the board under test. The number of conversion devices is strongly related to the design of the board under test. For example, if the board under test supports 4 CXL memory disk slots, then 4 conversion devices need to be inserted to ensure full-channel coverage.

[0079] In some embodiments, the DUT board is connected to the server motherboard using an MCIO high-speed cable, which supports a single-channel rate of 32GT / s and above. Among them, the MCIO high-speed cable complies with the Gen-Z or PCIe 5.0 standard.

[0080] In some embodiments, the test system further includes a universal serial bus hub, which is used to expand the number of third preset interfaces of the electronic device so as to connect multiple conversion devices simultaneously.

[0081] In some embodiments, the serial bus hub, namely the USB hub (HUB), is connected between the server and the conversion device, expanding one USB interface into multiple interfaces, enabling the host to connect multiple USB devices simultaneously. The serial bus hub can be active (with power management) or passive (only signal expansion).

[0082] In some embodiments, by introducing a universal serial bus hub to expand the number of USB interfaces on the electronic device, parallel debugging and control of multiple conversion devices can be supported. In this way, an electronic device that originally had only one USB interface can connect multiple conversion devices simultaneously, thereby achieving concurrent testing of multiple devices.

[0083] In some embodiments, based on the present application, a buffer interface or an automatic switching device can also be adopted to avoid frequent plugging and unplugging operations, extend the lifespan of the CXL memory disk, and protect hardware resources.

[0084] In some embodiments, as Figure 3 shown, Figure 3 is a schematic structural diagram of a test system provided by an embodiment of the present application, including the aforementioned DUT board, electronic device, and conversion device. The conversion device includes a CXL chip (target memory disk), CPLD, DIMM interface, memory module including a registered dual inline memory module (RDIMM) / unbuffered dual inline memory module (UDIMM) (preset memory), UART module, power module, E3.S interface, USB interface, power supply interface, EEPROM. The DUT board includes an E3.S interface, and the electronic device includes a USB interface.

[0085] In some embodiments, through protocol conversion technology, ordinary DDR5 memory modules are simulated as storage devices compliant with the CXL standard. A high-performance CXL protocol conversion chip is used to convert the PCIe signal of the memory into the CXL.mem protocol in real time, enabling the system to recognize it as a native CXL memory disk.

[0086] In some embodiments, each module in the conversion device of the present application adopts a split architecture design, and the memory module and the conversion device can be independently replaced. When long-term testing causes the conversion device (including CXL chips, power modules, etc.) to age, only the device body needs to be replaced, while the memory module can still be used continuously, significantly reducing the maintenance cost and avoiding the waste problem of the entire scrapping of the CXL memory disk in the traditional solution. Under the harsh condition of plugging and unplugging 50 times a day, the device life can reach more than 2 years, and the memory module can be reused for more than 5 years.

[0087] In some embodiments, by integrating a USB-UART bridge chip, the test system supports directly sending debug instructions at the operating system layer. Specifically, the following methods can be used to achieve automated testing: command-line tools can be used to call the AT instruction set to query the device status (such as using AT+CXL_VER to obtain the firmware version); script control can also be utilized, for example, Python scripts can batch execute link training, bit error rate testing, etc. through the PyUSB library. Real-time monitoring can also be performed to continuously collect parameters such as temperature and voltage and record them in the database, and an alarm is automatically triggered when an anomaly occurs.

[0088] In some embodiments, the test method is applied to the aforementioned test system, such as Figure 4 shown Figure 4 is a schematic flowchart of a test method provided by an embodiment of the present application. The test method includes: Step 401, in response to the test system forming a loop, power on and test the target board to be tested; Step 402, in response to the end of the test of the target board to be tested, power off and shut down.

[0089] In some embodiments, the board to be tested is installed on the server, and its power supply and signal lines are ensured to be correctly connected. The conversion device is inserted into the memory disk slot (such as E3.S) on the board to be tested, and an MCIO high-speed cable is used to connect the server (electronic device) and the board to be tested; a USB is used to connect the server and the conversion device.

[0090] In some embodiments, powering on refers to supplying power to the server, the board to be tested, and the conversion device.

[0091] In some embodiments, by responding to the test system forming a loop, powering on and testing the target board to be tested, the server detects whether the conversion device is recognized as the target memory disk device.

[0092] In some embodiments, after the test of the board to be tested is completed, the server saves the test results and powers off. Here, shutting down refers to turning off the electronic device, that is, the server in the present application.

[0093] In some embodiments, before powering on and testing the target board under test in response to the test system forming a loop, the test method further includes: Obtain a set of boards under test, where the set of boards under test includes multiple boards under test; Based on the set of boards under test, determine the target board under test, where the target board under test is one of the boards in the set of boards under test.

[0094] In some embodiments, the set of boards under test refers to a set composed of multiple hardware devices that need to perform function verification or performance testing. Among them, each device is called a board under test, which may include different models of CXL backplanes, PCIe expansion cards, and server motherboards. In this application, the set of boards under test mainly focuses on CXL backplanes.

[0095] In some embodiments, the target board under test is a specific individual in the set of boards under test, indicating the board under test that is currently to be tested.

[0096] In some embodiments, as Figure 5 shown, Figure 5 is a schematic flowchart of a test method provided by an embodiment of the present application. Specifically, the test method includes: installing the board under test on the corresponding server; inserting a conversion device into each memory disk connector on the backplane; powering on and booting; executing a test program to test the board under test; after the test is completed, powering off and shutting down; if there are still boards under test, then replace and continue the test; if there are no boards under test, then this batch of tests ends.

[0097] Through the present application, the test method is applied to a test system, and the test system includes a board under test, an electronic device, and a conversion device; the board under test is communicatively connected to the electronic device, and a memory disk slot is provided on the board under test; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; the conversion device is connected to the board under test through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instruction to test the board under test. The target memory disk is a compute express link memory disk, which solves the technical problem of high cost in the related solution when using the compute express link memory for testing during the production test process. By converting the preset memory into the compute express link memory and using the target memory disk to test the board under test, the technical effect of reducing the production test cost during the production test is achieved.

[0098] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0099] An embodiment of the present application further provides a test device 600, Figure 6A schematic structural diagram of a test device provided by an embodiment of the present disclosure is as follows Figure 6 shown, including: A test unit 601, configured to power on and test a target board to be tested in response to forming a loop by a test system; A power-off unit 602, configured to power off and shut down in response to the end of the test of the target board to be tested.

[0100] Further, in a possible implementation manner of an embodiment of the present disclosure, the test device 500 further includes a determination unit, and the determination unit is configured to: Obtain a set of boards to be tested, where the set of boards to be tested includes multiple boards to be tested; Based on the set of boards to be tested, determine a target board to be tested, where the target board to be tested is one of the boards in the set of boards to be tested.

[0101] Through the present application, the test system includes a board to be tested, an electronic device, and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is configured to send a debugging instruction; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is configured to convert a preset memory into a target memory disk according to the debugging instruction to test the board to be tested, and the target memory disk is a computing high-speed interconnect memory disk, which solves the technical problem of high cost in using the computing high-speed interconnect memory for testing in the production test process in the related solution. By converting the preset memory into the computing high-speed interconnect memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production test cost during the production test is achieved.

[0102] For the description of the features in the embodiment corresponding to the test device, reference may be made to the relevant description of the embodiment corresponding to the test method, which will not be elaborated here one by one.

[0103] An embodiment of the present application further provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above test method embodiments.

[0104] An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program is configured to execute the steps in any one of the above test method embodiments when running.

[0105] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0106] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-described test method embodiments are implemented.

[0107] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-described test method embodiments are implemented.

[0108] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0109] The above has introduced in detail a test system, method, electronic device, storage medium, and product provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A test system, characterized in that, It includes a board under test, an electronic device, and a conversion device; The board under test is communicatively connected to the electronic device, and a memory disk slot is provided on the board under test; The electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; The conversion device is connected to the board under test through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instruction to test the board under test, and the target memory disk is a compute express link memory disk.

2. The test system according to claim 1, characterized in that The conversion device includes a target chip, a control module, a memory module, and a debugging module; The target chip is communicatively connected to the board under test through a first preset interface; The control module is communicatively connected to the target chip, and the control module is used to monitor the state of the target chip, and the state of the target chip includes at least one of the temperature of the target chip and the link rate of the target chip; The memory module is communicatively connected to the target chip through a second preset interface, and the memory module is used to store data; The debugging module is communicatively connected to the control module, and the debugging module is communicatively connected to the electronic device through a third preset interface, and the debugging module is used to convert the debugging instruction into a serial communication signal and transmit it to the control module.

3. The test system according to claim 2, wherein The conversion device further includes a power module; The power module is communicatively connected to a power adapter through a fourth preset interface, and the power adapter is used to supply power to the conversion device.

4. The test system according to claim 2, wherein The conversion device further includes a cache module; The cache module is communicatively connected to the target chip, and the cache module is used to store the firmware and configuration parameters of the conversion device, and the configuration parameters include at least one of a device identifier and a link training mode.

5. The test system according to claim 1, characterized in that, The number of the conversion devices is determined by the number of memory disk slots on the board under test.

6. The test system according to claim 2, characterized in that, The system further includes a universal serial bus hub, and the universal serial bus hub is used to expand the number of third preset interfaces of the electronic device so as to connect multiple conversion devices simultaneously.

7. A testing method, characterized in that, The method is applied to the test system according to any one of claims 1-6, and the method includes: In response to the test system forming a loop, power on and test a target board under test; In response to the test of the target board under test being completed, power off and shut down.

8. The test method according to claim 7, characterized in that, Before the step of in response to the test system forming a loop, power on and test a target board under test, the method further includes: Obtain a set of boards under test, and the set of boards under test includes multiple boards under test; Based on the set of boards under test, determine the target board under test, and the target board under test is one of the boards under test in the set of boards under test.

9. An electronic device, characterized in that, It includes: A memory for storing a computer program; A processor for implementing the steps of the test method according to any one of claims 7 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the test method according to any one of claims 7 to 8 when executed by a processor.

11. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the test method according to any one of claims 7 to 8 when executed by a processor.

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