Method for writing test parameters into single-board memory
By establishing a channel pin and code comparison table, the test parameters are written directly into the single board memory, which solves the time-consuming and cost-effective problem in the existing technology, and realizes efficient writing of test parameters, reducing costs and improving testing efficiency.
Patent Information
- Application Number
- CN202311830572.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-01
AI Technical Summary
When writing test parameters into single-board memory, the existing technology requires repeated combination of the entity address and test parameters of single-board memory multiple times, resulting in a long time and high cost.
By establishing a channel pin comparison table and a channel code comparison table, the test parameters are directly written to the single-board memory to reduce the number of buffers. Only one test buffer can be used to complete the parameter writing.
It greatly reduces the time to combine single-board memory entity addresses and test parameters, reduces hardware costs, and improves the testing efficiency of the test machine.
Smart Images
Figure CN120234202A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a method for writing test parameters into the memory of a single board, and in particular to a method that can improve the efficiency of writing test parameters. Background Art
[0002] To improve the test efficiency, a general test machine needs to detect many chips under test simultaneously. The test machine is provided with many test single boards, and many test positions (sites) can be defined on each test single board. The chips under test are placed in these test positions for testing. In practice, a test position may correspond to many pins of the test single board, and each corresponding pin is electrically connected to a corresponding pad of the chip under test. The test single board can read or write data to the chips under test in the test positions. However, when the test machine writes test parameters into the memory of these test single boards, it often takes a considerable amount of time.
[0003] Please refer to Figure 1 , Figure 1 which is a flowchart of the steps of the traditional method for writing test parameters into the memory of a single board. As Figure 1 shown, in step S90, the traditional test machine first searches for the physical address of the memory of the single board. Here, it is assumed that the test machine finds that the first channel corresponds to the 63rd pin of the test single board numbered 3 and the 0th pin of the test single board numbered 0, the second channel corresponds to the 62nd pin of the test single board numbered 3 and the 1st pin of the test single board numbered 0, and the third channel corresponds to the 61st pin of the test single board numbered 3 and the 2nd pin of the test single board numbered 0.
[0004] Next, in step S92, the traditional test machine converts the test code of each channel into a corresponding set of test parameters. For example, the channel may transmit test codes such as 0, 1, 2, etc., and the test codes 0, 1, 2 each represent a specific test pattern. Then, in step S94, the traditional test machine combines the physical address of the memory of the single board and the corresponding test parameters in multiple buffers respectively. Here, the traditional test machine needs to configure a buffer for each test single board, and let the buffer first combine the corresponding physical address of the memory of the single board and the test parameters. For example, the address 0 of the buffer of the test single board numbered 0 needs to store "the test parameters corresponding to the physical address 0 of the memory of the single board", the address 1 needs to store "the test parameters corresponding to the physical address 1 of the memory of the single board", and so on.
[0005] Finally, in step S96, a traditional testing machine writes the data in the buffer of each tested single board into the corresponding single-board memory. For example, the traditional testing machine writes the data in the buffer of the 0th tested single board into the first row of the single-board memory of the 0th tested single board, representing the test tasks to be executed by the 0th tested single board in the first time (interval). That is to say, the test parameters stored at address 0 of the buffer are written into the physical address 0 of the single-board memory, and the test parameters stored at address 1 of the buffer are written into the physical address 1 of the single-board memory. Those of ordinary skill in the art can understand that the testing machine needs to continuously execute many test tasks on the chip under test. That is to say, the traditional testing machine often has to repeat steps S92 to S96 several times to finish writing a series of test tasks. In particular, repeatedly combining the physical address of the single-board memory and the corresponding test parameters in multiple buffers (S94) is quite time-consuming, and it also requires more cost to configure a buffer for each tested single board. Accordingly, the industry needs a new method for writing test parameters into the single-board memory to reduce the hardware cost and improve the testing efficiency of the testing machine. Summary of the Invention
[0006] The technical problem to be solved by this application is to provide a method for writing test parameters into the single-board memory, which does not need to combine the physical address of the single-board memory and the corresponding test parameters in the buffer, thereby reducing the number of buffers and improving the testing efficiency of the testing machine.
[0007] This application proposes a method for writing test parameters into the single-board memory, which is used for a testing machine with multiple tested single boards, and each tested single board has N pins. The method includes: establishing a channel-pin correspondence table associated with each tested single board, where the channel-pin correspondence table indicates that the i-th channel in M channels corresponds to the j-th pin among the N pins of the tested single board where it is located; converting each test code transmitted by the M channels at the first time into a corresponding set of test parameters; maintaining a channel code correspondence table in the test buffer, where the channel code correspondence table stores the test parameters corresponding to the i-th channel in M channels at the first time; and writing the test parameters corresponding to the i-th channel at the first time into the physical address of the corresponding single-board memory of each tested single board according to the channel-pin correspondence table and the channel code correspondence table. Where the physical address of the single-board memory is associated with the j-th pin among the N pins, M and N are positive integers, i is a positive integer not greater than M, and j is a positive integer not greater than N.
[0008] In some embodiments, the method of writing test parameters into the single-board memory further includes: converting each test code transmitted by M channels at a second time into a corresponding another set of test parameters to update the channel code look-up table maintained in the test buffer, where the channel code look-up table indicates the test parameters corresponding to the i-th channel among the M channels at the second time; according to the channel pin look-up table and the updated channel code look-up table, writing the set of test parameters corresponding to the i-th channel at the second time into the single-board memory of each corresponding test board. Here, the test parameters corresponding to the first time stored in the single-board memory of each test board are the first test task, and the test parameters corresponding to the second time stored are the second test task that follows the first test task. In addition, each of the test boards is provided with at least one test position for setting a chip under test, and the test position is defined with a plurality of connection pads, and each of the connection pads corresponds to one of the N pins respectively.
[0009] In summary, the method of writing test parameters into the single-board memory provided by the present application uses the establishment of the channel pin look-up table and the channel code look-up table to greatly reduce the time for combining the physical addresses of the single-board memory and the corresponding test parameters. Moreover, the present application only requires one test buffer, instead of requiring a corresponding buffer to be configured for each test board as in the traditional case, which not only reduces costs but also improves the test efficiency of the test machine.
[0010] The other effects and detailed content of the embodiments of the present application are described below in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0012] Figure 1 is a flowchart of the steps of the traditional method of writing test parameters into the single-board memory;
[0013] Figure 2 is a flowchart of the steps of the method of writing test parameters into the single-board memory according to an embodiment of the present application;
[0014] Figure 3 is a schematic diagram of the channel pin look-up table according to an embodiment of the present application;
[0015] Figure 4 is a schematic diagram of the channel code look-up table according to an embodiment of the present application;
[0016] Figure 5 It is a schematic diagram of writing to the single-board memory according to an embodiment of the present application.
[0017] Symbol Explanation
[0018] S10~S16: Step flow
[0019] S90~S96: Step flow Detailed Implementation Manner
[0020] In the following implementation manners, the positional relationships described include: up, down, left, and right. Unless otherwise specified, they are all based on the directions in which the components are shown in the drawings.
[0021] Please refer to Figure 2 and Figure 3 , Figure 2 It is a step flowchart of a method for writing test parameters to the single-board memory according to an embodiment of the present application. Figure 3 It is a schematic diagram of a channel pin position comparison table and a channel code comparison table according to an embodiment of the present application. As shown in the figure, the present application is applied to a test machine. The test machine may have multiple test single boards, and each test single board has multiple pins (N pins). In practice, each test single board provides at least one test position, and the test position can be used to set the chip under test, and the test position is defined with multiple connection pads for electrically connecting the chip under test. Each connection pad can respectively correspond to one of the pins. That is to say, the test machine can transmit signals to the chip under test or extract signals from the chip under test via the pins of the test single board. Here, this embodiment describes that when the test machine is to transmit test signals to the chip under test, it often needs to first write the relevant signals into the single-board memory of the corresponding test single board.
[0022] Different from the traditional method of writing test parameters to the single-board memory, this embodiment does not require repeatedly combining the physical address of the single-board memory and the corresponding test parameters in the buffer. Taking an actual example, it is also assumed that the test machine finds that the first channel corresponds to the 63rd pin of the test single board numbered 3 and the 0th pin of the test single board numbered 0, the second channel corresponds to the 62nd pin of the test single board numbered 3 and the 1st pin of the test single board numbered 0, and the third channel corresponds to the 61st pin of the test single board numbered 3 and the 2nd pin of the test single board numbered 0.
[0023] In step S10, the test machine of this embodiment can pre-establish a channel pin position comparison table associated with each test single board. For example Figure 3 as shown in , this embodiment can establish a channel pin position comparison table for the test single board numbered 0. This channel pin position comparison table indicates the channel name corresponding to each pin in the test single board numbered 0. Here,Figure 3 It is shown that the test machine provides 3 channels (M channels). The pin numbered 0 corresponds to the channel named 1, the pin numbered 1 corresponds to the channel named 2, and the pin numbered 2 corresponds to the channel named 3. Also, for the test single board numbered 3, a channel pin correspondence table will be established. This channel pin correspondence table indicates that the pin numbered 63 corresponds to the channel named 1, the pin numbered 62 corresponds to the channel named 2, and the pin numbered 61 corresponds to the channel named 3. Those with ordinary knowledge in the technical field can understand that the channel name can be defined by oneself, and this embodiment does not limit it here. In addition, from the above, it can be seen that one channel (such as channel 1) can correspond to different test positions on different test single boards, that is, different pins. This embodiment does not limit the number of test positions or pins that a channel can correspond to. It is worth mentioning that the test single board does not necessarily use all the pins. If some pins of the test single board do not correspond to a channel, the numbers of those pins will not be filled with the corresponding channel name.
[0024] Next, in step S12, the test machine of this embodiment can convert each test code transmitted by all channels at the first time into a corresponding set of test parameters. For example, at the first time, each channel may transmit its own test code respectively. The test code can be 0, 1, 2, L, H, X, Z, V, etc., and each represents a specific test pattern. In an example, the test code 0 may correspond to the command signals of parameter TP, parameter IO, and parameter CARE. Thus, the test machine can combine the command signals of parameter TP, parameter IO, and parameter CARE to form the test pattern indicated by the channel. Those with ordinary knowledge in the technical field should be able to understand the meanings represented by parameter TP, parameter IO, and parameter CARE respectively, and this embodiment will not elaborate here.
[0025] Next, in step S14, the test machine of this embodiment can provide a test buffer, and the test buffer can maintain a channel code correspondence table. Here, the channel code correspondence table can store the set of test parameters corresponding to the i-th channel among the M channels at the first time. Please refer to Figure 4 , Figure 4 which is a schematic diagram of the channel code correspondence table according to an embodiment of the present application. As Figure 4 shown, the channel code correspondence table will mark all the channel names, and each channel name will correspond to a set of test parameters. In practice, the first time refers to the duration of the test parameters (or the corresponding test patterns) provided by the M channels. Assuming a given first time (duration) a code TM0, then Figure 4 all the test parameters listed in the channel code correspondence table are corresponding to the first time (code TM0).
[0026] Next, in step S16, the test machine of this embodiment writes the set of test parameters stored in the test buffer (the test parameters corresponding to the first time) to the physical address of the board memory of the corresponding test board according to the channel pin correspondence table and the channel code correspondence table stored in the test buffer. Taking the above example, please also refer to Figures 3 to 5 , Figure 5 FIG. is a schematic diagram of writing to the board memory according to an embodiment of the present application. As shown in the figure, the test machine of this embodiment can know, according to the channel pin correspondence table of the test board numbered 0, that the pin numbered 0 corresponds to the channel with the channel name 1, so that the test machine can read the test parameters of the corresponding channel with the channel name 1 and write them to the physical address numbered 0 of the board memory of the test board numbered 0. Those of ordinary skill in the art can understand that the test parameters in the physical address numbered 0 of the board memory are the test behaviors of the pin numbered 0.
[0027] The test machine of this embodiment can then know, according to the channel pin correspondence table of the test board numbered 0, that the pins numbered 1, 2,... correspond to the channels with the channel names 2, 3,... so that the test machine can read the test parameters of the corresponding channels with the channel names 2, 3,... and write them to the physical addresses numbered 1, 2,... of the board memory of the test board numbered 0. Similarly, the test machine of this embodiment can again know, according to the channel pin correspondence table of the test board numbered 3, that the pins numbered 63, 62, 61,... correspond to the channels with the channel names 1, 2, 3,... so that the test machine can read the test parameters of the corresponding channels with the channel names 1, 2, 3,... and write them to the physical addresses numbered 63, 62, 61,... of the board memory of the test board numbered 3.
[0028] After the test machine of this embodiment writes the test parameters of all channels corresponding to the first time to the board memory of the test board, it can then process the test tasks associated with the second time. In practice, since the channel pin correspondence table associated with each test board indicates the hardware connection relationship, the hardware connection relationship should not change between consecutive test tasks. Therefore, the test machine of this embodiment can use the established channel pin correspondence table associated with each test board without establishing the channel pin correspondence table again.
[0029] Assuming the test tasks at the second time and the test tasks at the first time, then the test machine of this embodiment will return to Figure 2In step S12, similar to the previous time, each test code transmitted by all channels at the second time is converted into a corresponding another set of test parameters. Then, in the next step, the test buffer can be updated to store the set of test parameters corresponding to the i-th channel among the M channels at the second time. Since the test buffer has been updated with the new test parameters, in the next step, the test machine of this embodiment writes the set of test parameters (the test parameters corresponding to the second time) stored in the test buffer to the physical address of the board memory of the corresponding test board according to the channel pin correspondence table and the updated channel code correspondence table stored in the test buffer. By analogy, the board memory of each test board can be updated with all the test parameters required for each test task of all pins.
[0030] In summary, the method for writing test parameters to the board memory provided by this application uses the establishment of the channel pin correspondence table and the channel code correspondence table, which greatly reduces the time for combining the physical address of the board memory and the corresponding test parameters. Moreover, this application only requires one test buffer, instead of configuring a corresponding buffer for each test board as in the traditional method, which not only reduces costs but also improves the test efficiency of the test machine.
[0031] The above-described embodiments and / or implementation manners are only used to illustrate the preferred embodiments and / or implementation manners for implementing the technology of this application, and do not impose any formal restrictions on the implementation manners of the technology of this application. Any person skilled in the art, without departing from the scope of the technical means disclosed in the content of this application, may make some changes or modifications to other equivalent embodiments, but should still be regarded as the same technology or embodiment as this application in essence.
Claims
1. A method for writing test parameters into the memory of a single board, which is used for a test machine with multiple test single boards, and each of the test single boards has N pins, characterized in that, The method includes: Establishing a channel pin correspondence table associated with each of the test single boards, the channel pin correspondence table indicating that a first i-th channel among the M channels corresponds to a first j-th pin among the N pins of the test single board where it is located; Converting each of the test codes transmitted by the M channels at a first time into a corresponding set of test parameters; Maintaining a channel code correspondence table in a test buffer, the channel code correspondence table storing the set of test parameters corresponding to the i-th channel among the M channels at the first time; and According to the channel pin correspondence table and the channel code correspondence table, writing the set of test parameters corresponding to the i-th channel at the first time into a physical address of a single board memory of each corresponding test single board; Wherein the physical address of the single board memory is associated with the j-th pin among the N pins; Where M and N are positive integers, i is a positive integer not greater than M, and j is a positive integer not greater than N.
2. The method for writing test parameters into the memory of a single board according to claim 1, characterized in that The method further includes: Converting each of the test codes transmitted by the M channels at a second time into a corresponding another set of test parameters; Updating the channel code correspondence table maintained in the test buffer, the channel code correspondence table indicating the set of test parameters corresponding to the i-th channel among the M channels at the second time; and According to the channel pin correspondence table and the updated channel code correspondence table, writing the set of test parameters corresponding to the i-th channel at the second time into the single board memory of each corresponding test single board.
3. The method for writing test parameters into the memory of a single board according to claim 2, wherein, The set of test parameters corresponding to the first time stored in the single board memory of each test single board is a first test task, and the set of test parameters corresponding to the second time stored is a second test task that continues the first test task.
4. The method for writing test parameters into the memory of a single board according to claim 1, characterized in that, Each test single board is provided with at least one test position for setting a chip under test, and the test position is defined with a plurality of connection pads, each of the connection pads corresponding to one of the N pins respectively.