Circuit analysis method and device, electronic equipment and computer program product

Abstract

The embodiment of the invention is suitable for the technical field of digital circuits, and provides a circuit analysis method and device, electronic equipment and a computer program product, and the method comprises the steps: obtaining description information of a to-be-analyzed circuit in different description modes; the description information in different description modes at least comprises a function abstract corresponding to a text description mode, a circuit diagram corresponding to a graphic description mode and a hardware description language corresponding to a programming language description mode; performing feature fusion on the single-mode features obtained based on the description information to generate fusion features of the circuit to be analyzed; inputting the fusion features into an analysis model, and generating an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit comprises a correlation circuit corresponding to the to-be-analyzed circuit and / or a prediction index corresponding to the to-be-analyzed circuit. According to the method provided by the embodiment of the invention, the circuit to be analyzed can be analyzed according to the characteristics under various description information, so that the analysis accuracy of the circuit is improved.

Description

Technical Field

[0001] The embodiments of the present application belong to the technical field of digital circuits, and particularly relate to a circuit analysis method, device, electronic device, and computer program product. Background Art

[0002] The rapid development of artificial intelligence depends on the support of digital integrated circuits (ICs). However, with the increasing demand for hardware computing power, the structure of digital integrated circuits has become increasingly complex, so the design cost of digital integrated circuits has also risen sharply. To reduce the design cost of digital integrated circuits, more and more researchers have started to use neural network models to assist in the analysis of the designed digital integrated circuits to reduce the design cost of digital integrated circuits. For example, other digital integrated circuits with similar structures are retrieved through a retrieval model; the indicators of the currently designed digital integrated circuit are predicted through a prediction model, etc.

[0003] In the prior art, when researchers use neural network models to assist in the analysis of digital integrated circuits, they usually extract the image features corresponding to the circuit diagrams of digital integrated circuits and input the image features into the analysis model to generate the analysis results corresponding to the digital integrated circuits. However, the circuit diagram is only one of the many manifestations of digital integrated circuits. Digital integrated circuits can have multiple different manifestations, and the focuses of different manifestations are different. For example, the focus of the circuit diagram is to visually present the connection relationships between various physical components (such as resistors, capacitors, transistors, etc.) in the circuit in a graphical manner. Therefore, the analysis accuracy of the existing method for analyzing digital integrated circuits only based on the image features of circuit diagrams is relatively low. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a circuit analysis method, device, electronic device, and computer program product to improve the analysis accuracy of circuit analysis for digital integrated circuits.

[0005] The first aspect of the embodiments of the present application provides a circuit analysis method, including:

[0006] Obtain the description information of the circuit to be analyzed under different description methods; the description information under different description methods at least includes the function summary corresponding to the text description method, the circuit diagram corresponding to the graphical description method, and the hardware description language corresponding to the programming language description method;

[0007] Perform feature fusion on the unimodal features obtained based on the description information to generate the fusion features of the circuit to be analyzed;

[0008] Input the fused feature into an analysis model to generate an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes an associated circuit corresponding to the circuit to be analyzed and / or a prediction index corresponding to the circuit to be analyzed.

[0009] In a possible implementation manner of the first aspect, the obtaining of the description information of the circuit to be analyzed in different description manners includes:

[0010] Split the circuit to be analyzed into multiple sub - circuits;

[0011] Obtain the description information of each sub - circuit in different description manners.

[0012] In a possible implementation manner of the first aspect, the feature fusion of the single - modality features obtained based on the description information to generate the fused feature of the circuit to be analyzed includes:

[0013] Extract features from the description information in different description manners through different feature extraction networks to determine the single - modality features of the sub - circuits; the different feature extraction networks respectively correspond to the different description manners;

[0014] Fuse the multiple single - modality features of the sub - circuits through a feature fusion network to determine the sub - fused features of the sub - circuits;

[0015] Perform feature splicing on the sub - fused features of the multiple sub - circuits to determine the fused feature corresponding to the circuit to be analyzed.

[0016] In a possible implementation manner of the first aspect, the extracting of features from the description information in different description manners through different feature extraction networks to determine the single - modality features of the sub - circuits includes at least one of the following:

[0017] Input the function summary into the feature extraction network corresponding to the text description manner to determine the first single - modality feature of the sub - circuit;

[0018] Input the circuit diagram into the feature extraction network corresponding to the graphical description manner to determine the second single - modality feature of the sub - circuit;

[0019] Input the hardware description language into the feature extraction network corresponding to the programming language description manner to determine the third single - modality feature of the sub - circuit.

[0020] In a possible implementation manner of the first aspect, the splitting of the circuit to be analyzed into multiple sub - circuits includes:

[0021] The circuit to be analyzed is split based on the registers in the circuit to be analyzed, and the sub - circuits are obtained; each sub - circuit includes one of the registers; the registers included in different sub - circuits are different.

[0022] In a possible implementation manner of the first aspect, the step of inputting the fusion feature into an analysis model to generate an analysis result corresponding to the circuit to be analyzed includes:

[0023] Input the fusion feature into the analysis model, and calculate the similarity between the fusion feature and the candidate features of the candidate circuits;

[0024] Use the candidate circuits with the similarity greater than the similarity threshold as the associated circuits of the circuit to be analyzed;

[0025] Calculate the predicted metrics of the circuit to be analyzed according to the circuit metrics of the associated circuits and the weight coefficients corresponding to the similarities;

[0026] Generate an analysis result corresponding to the circuit to be analyzed according to the associated circuits and the predicted metrics.

[0027] In a possible implementation manner of the first aspect, the predicted metrics include at least one of the predicted area of the circuit to be analyzed, the predicted power consumption of the circuit to be analyzed, the single timing margin of each register, the worst negative timing margin of the circuit to be analyzed, and the total negative margin of the circuit to be analyzed.

[0028] A second aspect of the embodiments of the present application provides a circuit analysis device, including:

[0029] An information acquisition module, configured to acquire description information of the circuit to be analyzed in different description manners; the description information in different description manners includes at least a function summary corresponding to the text description manner, a circuit diagram corresponding to the graphical description manner, and a hardware description language corresponding to the programming language description manner;

[0030] A feature acquisition module, configured to perform feature fusion on the single - modal features obtained based on the description information to generate a fusion feature of the circuit to be analyzed;

[0031] An analysis module, configured to input the fusion feature into an analysis model to generate an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes the associated circuit corresponding to the circuit to be analyzed and / or the predicted metrics corresponding to the circuit to be analyzed.

[0032] A third aspect of the embodiments of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where when the processor executes the computer program, the circuit analysis method as described in the first aspect above is implemented.

[0033] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the circuit analysis method described in the first aspect above is implemented.

[0034] A fifth aspect of the embodiments of the present application provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the circuit analysis method described in the first aspect.

[0035] Compared with the prior art, the embodiments of the present application have the following advantages:

[0036] In an embodiment of the present application, the electronic device can determine the fusion features of the circuit to be analyzed based on the unimodal features of a variety of different descriptive information. Since the description information of different description methods has different focuses, the method improved in the embodiment of the present application can effectively avoid the one-sidedness caused by a single description method, so that the generated fusion features can more accurately reflect the overall picture of the circuit to be analyzed, and improve the comprehensiveness and accuracy of the fusion features. Furthermore, since the accuracy of the fusion features is an important factor affecting the accuracy of the analysis results, the accuracy of the analysis results can be further improved by the method provided in the embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic diagram of a circuit analysis method provided in an embodiment of the present application;

[0039] Figure 2 This is a schematic diagram of a process for obtaining description information provided in an embodiment of the present application;

[0040] Figure 3 This is a schematic diagram of a fusion feature acquisition process provided in an embodiment of the present application;

[0041] Figure 4 is a schematic diagram of another circuit analysis method provided in an embodiment of the present application;

[0042] Figure 5 It is a schematic diagram of a sub-circuit acquisition process provided in an embodiment of the present application;

[0043] Figure 6It is a schematic diagram of another circuit analysis method provided by an embodiment of the present application;

[0044] Figure 7 It is a schematic diagram of a model training process provided by an embodiment of the present application;

[0045] Figure 8 It is a schematic diagram of a circuit analysis device provided by an embodiment of the present application;

[0046] Figure 9 It is a schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0047] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0048] To better understand the audio processing method provided by the present application, the following introduces the specific implementation process and algorithm from the implementation level.

[0049] The rapid development of artificial intelligence technology requires digital integrated circuits as hardware support, such as Graphics Processing Unit (GPU), Tensor Processing Unit (TPU), and Neural Network Processing Unit (NPU). Therefore, with the increasing demand for computing power in artificial intelligence technology, the circuit structure of digital integrated circuits has become increasingly complex. The increasingly complex circuit structure has also led to a sharp rise in the design cost of digital integrated circuits, posing challenges to traditional digital integrated circuit design methods. In recent years, in order to reduce the design difficulty and design cost of digital integrated circuits, more and more researchers have begun to explore methods of using artificial intelligence technology for assisted design.

[0050] Due to the powerful learning ability, efficient optimization algorithm, and fast processing ability for complex structures of artificial intelligence technology, by applying neural network models, the design process of digital integrated circuits can be accelerated, especially in key aspects such as automatic placement and routing. For example, in the early stage of digital integrated circuit design, researchers can identify potential problems caused by the current structure through prediction models, thus avoiding costly modifications in the later stage. In the existing technology, artificial intelligence technology is mainly applied in aspects such as automated chip design planning, early chip quality assessment, and automated chip design assistance. In the existing application solutions, researchers mostly obtain the image features of the circuit diagram corresponding to the circuit to be analyzed through supervised learning or self-supervised contrast learning methods, and perform assisted design based on the image features of the circuit diagram. It can be seen that most of the existing application solutions are set according to specific tasks and are generated by the method of supervising and training the neural network model through the image features corresponding to the circuit diagram of the digital integrated circuit.

[0051] However, the circuit diagram is only one of the many description methods of digital integrated circuits. Digital integrated circuits can have multiple different description methods, and the focuses of different description methods are different. Therefore, digital integrated circuits inherently have multi-modal characteristics. Digital integrated circuits can be described not only by circuit diagrams, but also by Hardware Description Language (HDL), operator graphs, netlists, or function summaries, etc. Generally speaking, the focuses of different description methods are different. The focus of the circuit diagram is to visually present the connection relationships between various physical components (such as resistors, capacitors, transistors, etc.) in the circuit in a graphical way; the focus of the hardware description language is to abstractly describe the behavior and function of the circuit. It can define the output response of the circuit under different input conditions in a way similar to software programming without the need to consider in detail the specific hardware implementation details; the netlist mainly focuses on accurately describing the connection relationships between various components (such as logic gates, flip-flops, etc.) in the circuit; the function summary mainly focuses on describing the main functions and application scenarios implemented by the circuit; the operator graph mainly focuses on presenting the execution order and mutual relationships of various logical operations and arithmetic operations in the circuit.

[0052] In view of this, an embodiment of the present application provides a method for generating a fusion feature corresponding to a circuit to be analyzed according to the description information of the circuit to be analyzed in different description methods. After the R & D personnel obtain the fusion feature corresponding to the circuit to be analyzed, they can perform analysis operations such as retrieval, index prediction, and quality assessment on the circuit to be analyzed according to the fusion feature. Since digital integrated circuits have different focuses in different description methods, in the embodiment of the present application, the electronic device determines the fusion feature based on the description information in the comprehensive description method, which can comprehensively describe the characteristics of the circuit from multiple dimensions, avoiding one-sided understanding that may be caused by relying only on a single information source, thereby making the analysis of the circuit by the electronic device more accurate and in-depth, and improving the accuracy of the circuit analysis of the electronic device.

[0053] The present application provides a management method for a circuit feature extraction model. The circuit feature extraction model can be a model used to obtain the fusion feature of the circuit to be analyzed. Specifically, the circuit feature extraction model can include multiple feature extraction networks and a feature fusion network. Among them, the feature extraction network can be used to extract the single-modal features of the circuit to be analyzed from the description information, and the feature fusion network can be used to perform feature fusion on multiple single-modal features to generate the fusion feature corresponding to the circuit to be analyzed.

[0054] Among them, the management method of the embodiment of the present application includes two stages, namely: a model training stage for generating an applicable circuit feature extraction model, and a model usage stage for applying the circuit feature extraction model.

[0055] Model usage stage

[0056] Refer to Figure 1 , which shows a schematic diagram of a circuit analysis method provided by an embodiment of the present application, and specifically may include the following steps:

[0057] S101. Obtain the description information of the circuit to be analyzed in different description methods.

[0058] In this embodiment, the circuit to be analyzed can be a digital integrated circuit in the design stage that the R & D personnel need to perform circuit analysis on. The description method of the circuit to be analyzed is a form that can express and present relevant information such as the structure, composition, and characteristics of the circuit. Among them, the description methods of the circuit to be analyzed can include text description methods, graphic description methods, programming language description methods, operator description methods, and netlist description methods, etc. The description information of the circuit to be analyzed in a certain description method refers to the information generated according to this description method that can be used to represent the specific content and details of the digital integrated circuit. Among them, the description information of the circuit to be analyzed can include a function summary in the text description method, a circuit diagram in the graphic description method, a hardware description language in the programming language description method, a circuit netlist in the netlist description method, etc.

[0059] When a user needs to perform circuit analysis on a circuit to be analyzed or needs to perform auxiliary design on the circuit to be analyzed through a neural network model, the user can send an analysis instruction to the electronic device. Among them, the analysis instruction can at least include the hardware description language of the circuit to be analyzed. That is, there are at least the following four cases for the analysis instruction. Case 1: The analysis instruction contains the hardware description language corresponding to the circuit to be analyzed; Case 2: The analysis instruction contains the hardware description language and circuit diagram corresponding to the circuit to be analyzed; Case 3: The analysis instruction contains the hardware description language and function summary corresponding to the circuit to be analyzed; Case 4: The analysis instruction contains the hardware description language, circuit diagram and function summary corresponding to the circuit to be analyzed.

[0060] See Figure 2 , which is a schematic diagram of the acquisition process of a kind of description information provided by an embodiment of the present application. As Figure 2 shown, after receiving the analysis instruction, the electronic device can obtain the description information of the circuit to be analyzed in different description methods, so as to extract the features of the circuit to be analyzed according to all the description information of the circuit to be analyzed. Among them, the description information obtained by the electronic device can at least include the function summary, circuit diagram and hardware description language of the circuit to be analyzed. Further, the description information obtained by the electronic device can also include the circuit netlist of the circuit to be analyzed.

[0061] In a possible implementation manner, after receiving the analysis instruction, the electronic device can determine whether the analysis instruction contains the circuit diagram corresponding to the circuit to be analyzed. As Figure 2 shown, if the electronic device determines that the analysis instruction does not contain a circuit diagram, the electronic device can call a preset circuit diagram generation program or the call interface of the circuit diagram generation program, and input the received hardware description language into the circuit diagram generation program to obtain the circuit diagram of the circuit to be analyzed in the graphical description method. If the electronic device determines that the analysis instruction contains a circuit diagram, the electronic device can not call the circuit diagram generation program and the call interface of the circuit diagram generation program. It should be noted that the circuit diagram generation program used by the electronic device can be any application program well known to those skilled in the art, such as an Electronic Design Automation Tool (EDA), which can automatically generate a circuit diagram. The embodiment of the present application is not used to specifically limit the circuit diagram generation program.

[0062] In a possible implementation manner, after receiving the analysis instruction, the electronic device can determine whether the analysis instruction contains the function summary corresponding to the circuit to be analyzed. As Figure 2As shown, if the analysis instruction of the electronic device does not include a function summary, the electronic device can call a preset language model and input the obtained description information into the language model to generate a function summary corresponding to the circuit to be analyzed through the language model. If the analysis instruction of the electronic device includes a function summary, the electronic device may not call the language model. It should be noted that the language model used to generate the function summary in the embodiments of the present application can be any model known to those skilled in the art that can be used to generate summaries, such as a Transformer-based language model, a large language model (LLM), etc. The embodiments of the present application do not specifically limit the language model.

[0063] S102. Perform feature fusion on the unimodal features obtained based on the description information to generate a fusion feature of the circuit to be analyzed.

[0064] In this embodiment, after the electronic device obtains the description information, it can perform feature extraction on the description information to obtain the unimodal features included in the description information. Specifically, the electronic device can input the description information in a certain description method into the feature extraction network corresponding to this description method, so as to perform feature extraction on the description information through the feature extraction network corresponding to this description method and obtain the unimodal features corresponding to the circuit to be analyzed. After the electronic device obtains the unimodal features respectively included in each description information, it can input all the obtained unimodal features into the feature fusion network to perform feature fusion on all the unimodal features through the feature fusion network and generate a fusion feature.

[0065] In a possible implementation manner, since the description information obtained by the electronic device at least includes a hardware description language, a circuit diagram, and a function summary, the electronic device can at least include a feature extraction network corresponding to the text description method, a feature extraction network corresponding to the graphical description method, and a feature extraction network corresponding to the programming language description method. Refer to Figure 3 , which shows a schematic diagram of the acquisition process of a fusion feature provided by an embodiment of the present application. As Figure 3 shown, after the electronic device obtains the description information, it can perform feature extraction on the function summary through the feature extraction network corresponding to the text description method to determine the first unimodal feature of the circuit to be analyzed, perform feature extraction on the circuit diagram through the feature extraction network corresponding to the graphical description method to determine the second unimodal feature of the circuit to be analyzed, and can also perform feature extraction on the hardware description language through the feature extraction network corresponding to the programming language description method to determine the third unimodal feature of the circuit to be analyzed. Then, the electronic device can input the first unimodal feature, the second unimodal feature, and the third unimodal feature into the feature fusion network to perform feature fusion on all the unimodal features through the feature fusion network and generate a fusion feature.

[0066] Furthermore, the electronic device may further include a feature extraction network corresponding to the netlist description method. If the description information obtained by the electronic device further includes a circuit netlist corresponding to the netlist description method, the electronic device may further input the circuit netlist into the feature extraction network corresponding to the netlist description method to obtain the fourth single-modal feature corresponding to the circuit to be analyzed, and input the first single-modal feature, the second single-modal feature, the third single-modal feature, and the fourth single-modal feature into the feature fusion network, so as to perform feature fusion on all single-modal features through the feature fusion network to generate a fusion feature. If the description information obtained by the electronic device does not include a circuit netlist corresponding to the netlist description method, the electronic device may not obtain the fourth single-modal feature.

[0067] Specifically, the feature extraction network corresponding to the text description method may be composed of a language model (Bidirectional Encoder Representations From Transformers, BERT) and six different levels of transformers connected. Specifically, in the feature extraction network corresponding to the text description method, the electronic device may first input the function summary into the language model to perform word segmentation processing on the function summary through the language model, split the function summary into multiple tokens, and then the electronic device may input all the split tokens into each level of the transformer in sequence to generate the first single-modal feature included in the function summary. The feature extraction network corresponding to the graphical description method may be composed of seven different levels of graph transformers and a graph positional encoding connected. By performing feature extraction and encoding on the circuit diagram through the feature extraction network corresponding to the graphical description method, the electronic device may obtain the second single-modal feature {G1, G2,..., G n}, where n may be the number of nodes in the circuit diagram. The feature extraction network corresponding to the programming language description method may be a text encoder based on a large language model.

[0068] In a possible implementation, the feature fusion network can be formed by connecting 6 initialized multi-modal encoders and cross-attention networks at different levels. Since the first single-modal feature corresponding to the functional summary can provide richer semantic information, and the third single-modal feature corresponding to the programming language description and the second single-modal feature corresponding to the graphical description contain rich circuit details, the feature fusion network can perform feature fusion centered around the first single-modal feature corresponding to the functional summary. Specifically, the feature fusion network can first pad the third single-modal feature and the second single-modal feature to the same feature dimension, and then the feature fusion network can perform a feature mixing operation on the third single-modal feature and the second single-modal feature according to a preset interpolation coefficient to obtain a mixed feature. The mixed feature can be specifically expressed as: A{G1, G2,..., G n}+(1 - λ){C1, C2,..., Cg}. Where {G1, G2,..., G n} can represent the second single-modal feature, n can represent the feature dimension of the second single-modal feature; λ can be the first interpolation coefficient; A can be the second interpolation coefficient; {C1, C2,..., Cg} can represent the third single-modal feature, and g can represent the feature dimension of the third single-modal feature. Then, the feature fusion network can directly use the first single-modal feature as a query, use the mixed feature as keys and values, and input them into the cross-attention network to perform feature encoding through the cross-attention network and generate fused features {R1, R2,..., R m}. Where m can represent the feature dimension of the fused features.

[0069] S103. Input the fused features into the analysis model to generate an analysis result corresponding to the circuit to be analyzed.

[0070] In this embodiment, after obtaining the fused features, the electronic device can input the fused features into the analysis model to perform circuit analysis on the circuit to be analyzed through the analysis model and generate an analysis result corresponding to the circuit to be analyzed. Specifically, the analysis model in the electronic device can include a retrieval model and / or a prediction model. The analysis result corresponding to the analysis of the circuit includes at least one associated circuit corresponding to the circuit to be analyzed and / or a prediction index corresponding to the circuit to be analyzed. Among them, the prediction index can include at least one of a predicted area, a predicted power consumption, a predicted value of a single timing margin, a predicted value of the worst negative timing margin (WNS), and a predicted value of the total negative slack (TNS).

[0071] Among them, the predicted area can represent the total silicon area that may be required when implementing the circuit to be analyzed, and can be used to determine the physical feasibility and cost of the circuit to be analyzed. The predicted power consumption can represent the total power consumption that may be required when implementing the circuit to be analyzed, and can be used to evaluate the energy efficiency of the circuit to be analyzed. The single timing margin can be used to represent the margin of a certain register in the circuit to be analyzed, that is, the margin by which the register meets or does not meet the timing constraints during actual operation, which can help R & D personnel identify the registers that may cause timing violations in the circuit to be analyzed. The worst negative timing margin can be used to represent the negative timing margin of the circuit to be analyzed in the worst case, that is, the smallest negative timing margin value among the timing margins of all signal transmission paths in the circuit to be analyzed, and can be used to represent whether the circuit to be analyzed meets the timing requirements. The total negative margin is the sum of the negative margin values of all paths with negative timing margins in the circuit to be analyzed, and is used to represent the severity of the timing violation of the circuit to be analyzed, which helps R & D personnel with timing optimization work.

[0072] Through the method provided in this embodiment, the electronic device can determine the fusion features corresponding to the circuit to be analyzed according to the description information of the circuit to be analyzed in multiple description methods, and different description methods (such as schematic diagrams, circuit diagrams, logical expressions, state equations, etc.) focus on different aspects. Feature extraction will be performed according to multiple description information, and the characteristics of the circuit to be analyzed can be obtained from multiple angles, avoiding information loss caused by relying only on a single description method. Therefore, the fusion features generated by the method provided in the embodiments of this application are more comprehensive and accurate. Further, since the accuracy of the analysis model for circuit analysis of the circuit to be analyzed mainly depends on the accuracy of the fusion features, the method provided in this embodiment can also improve the accuracy of the analysis results of the circuit to be analyzed.

[0073] In a possible implementation manner, after obtaining the fusion features, the electronic device can directly input the fusion features into the prediction model to directly generate the prediction indicators corresponding to the circuit to be analyzed through the prediction model. Among them, the prediction model can be any model known to those skilled in the art that can perform prediction operations, such as a probability model, a clustering model, a deep learning model, etc. The embodiments of this application do not specifically limit the prediction model.

[0074] In a possible implementation manner, after obtaining the fusion features, the electronic device can directly input the fusion features into the retrieval model to directly generate the associated circuit corresponding to the circuit to be analyzed through the retrieval model. Among them, the retrieval model can be any model known to those skilled in the art that can perform retrieval operations, such as a Boolean model, a spatial vector model, a deep learning model, etc. The embodiments of this application do not specifically limit the retrieval model.

[0075] Figure 4The specific implementation flowchart of a circuit analysis method S102 and S103 provided in the second embodiment of the present application is shown. Refer to Figure 4 Compared with Figure 1 In the circuit analysis method provided in this embodiment, S102 includes: S401 to S402, and S103 includes: S403 to S405. The details are as follows:

[0076] S401. Split the circuit to be analyzed into multiple sub - circuits.

[0077] In the embodiment of the present application, refer to Figure 5 The schematic diagram of the acquisition process of a sub - circuit provided in the embodiment of the present application is shown. As Figure 5 shown, after the electronic device obtains the hardware description language of the circuit to be analyzed, it can split the circuit to be analyzed into M sub - circuits according to the hardware description language of the circuit to be analyzed. Among them, M can be a positive integer greater than or equal to 1.

[0078] In a possible implementation manner, the electronic device can determine multiple functional modules in the circuit to be analyzed according to the hardware description language of the circuit to be analyzed, and split the circuit to be analyzed into multiple sub - circuits according to the functional modules. Among them, each sub - circuit obtained by splitting according to the functional modules can be used to implement a function, and the functions implemented by different sub - circuits are different. Specifically, the hardware description language of the circuit to be analyzed may include multiple module definition statements. Among them, the module definition statement can be a statement in the hardware description language that defines the basic structure and function of the hardware module. The electronic device can determine at least one functional module corresponding to the circuit to be analyzed according to the module definition statements in the hardware description language, and split the circuit to be analyzed into sub - circuits corresponding to each functional module. For example, when a circuit to be analyzed includes an adder module, a multiplier module, and a filter module, the electronic device can split the circuit to be analyzed into sub - circuit A for implementing the adder function, sub - circuit B for implementing the multiplication function, and sub - circuit C for implementing the filter function.

[0079] In a possible implementation, the electronic device can determine multiple registers in the circuit to be analyzed according to the hardware description language of the circuit to be analyzed, and split the circuit to be analyzed into multiple sub-circuits according to the registers. Each sub-circuit obtained by splitting according to the registers can include one register, and the registers included in different sub-circuits are different. Specifically, after obtaining the hardware description language corresponding to a certain circuit to be analyzed, the electronic device can input the hardware description language into a parsing tool to parse the hardware description language through the parsing tool, and identify the registers, combinational logic and connection relationships in the circuit to be analyzed. It should be noted that the connection relationship can be at least one of the connection relationships between registers, the connection relationships between registers and combinational logic, and the connection relationships between combinational logic and combinational logic.

[0080] Then, the electronic device can use the registers and combinational logic as nodes and the connection relationships as edges to construct a graph model corresponding to the hardware description language. The electronic device can input the constructed graph model into a search algorithm preset by the R & D personnel. The search algorithm can traverse starting from each register node in each graph model. For a certain register node in the graph model, the electronic device can find all the nodes related to the register node, and construct a sub-graph corresponding to the register node according to all the found nodes and the connection relationships between the nodes. One sub-graph constructed by the electronic device can correspond to one sub-circuit. It should be noted that the search algorithm in the embodiments of the present application can be any search algorithm well known to those skilled in the art, such as the Breadth-First-Search (BFS) algorithm. The embodiments of the present application do not specifically limit the search algorithm.

[0081] S402. Obtain the description information of each sub-circuit in different description methods.

[0082] In this embodiment, after determining multiple sub-circuits corresponding to the circuit to be analyzed, the electronic device can respectively obtain the description information of each sub-circuit in different description methods. For any sub-circuit, the specific method for the electronic device to obtain the description information is the same as the specific method for the electronic device to obtain the description information of the circuit to be analyzed in the first embodiment of the present application. Please refer to the content in S101 of the first embodiment of the present application, and replace "the circuit to be analyzed" with "a certain sub-circuit" to understand the specific method for the electronic device to obtain the description information of the sub-circuit in different description methods in this embodiment.

[0083] S403. Extract features from the description information in different description methods through different feature extraction networks to determine the single-modal features of the sub-circuit.

[0084] In this embodiment, after the electronic device obtains the description information of each sub-circuit, it can separately extract multiple single-modal features corresponding to each sub-circuit. Among them, the specific method for the electronic device to obtain the single-modal features of any sub-circuit is the same as the method for the electronic device to obtain the single-modal features of the circuit to be analyzed in the first embodiment of this application. Readers can refer to the content in S102 of the first embodiment of this application, and replace the "circuit to be analyzed" in S102 with "sub-circuit" to understand the specific method for the electronic device to obtain the single-modal features of the sub-circuit.

[0085] S404. Feature-fuse the multiple single-modal features of the sub-circuit through a feature fusion network to determine the sub-fusion feature of the sub-circuit.

[0086] In this embodiment, the specific method for the electronic device to perform feature fusion on the multiple single-modal features of any sub-circuit is the same as the method for the electronic device to perform feature fusion on the multiple single-modal features of the circuit to be analyzed in the first embodiment of this application. Readers can refer to the content in S102 of the first embodiment of this application, replace the "circuit to be analyzed" in S102 with "sub-circuit", and replace the "fusion feature" with "sub-fusion feature" to understand the specific method for the electronic device to obtain the single-modal features of the sub-circuit.

[0087] S405. Perform feature stitching on the sub-fusion features of multiple sub-circuits to determine the fusion feature corresponding to the circuit to be analyzed.

[0088] In this embodiment, after the electronic device obtains the sub-fusion features of all sub-circuits corresponding to the circuit to be analyzed, it can perform feature stitching on the sub-fusion features of all sub-circuits to obtain the fusion feature corresponding to the circuit to be analyzed. It should be noted that the electronic device can perform feature stitching through any method well-known to those skilled in the art, such as a vector-based stitching method, a matrix-based stitching method, a neural network-based stitching method, etc. The embodiments of this application do not specifically limit the feature stitching method.

[0089] In the embodiments of this application, the electronic device can split the circuit to be analyzed into multiple sub-circuits and perform feature extraction according to the sub-circuits. Among them, compared with the complete circuit to be analyzed, the consistency between the hardware description language and the circuit netlist of the sub-circuit is higher. Therefore, splitting the circuit to be analyzed into multiple sub-circuits for circuit analysis can better assist the R & D personnel in circuit design work, thereby improving the circuit design efficiency of the R & D personnel and reducing the circuit design cost. In addition, since the sub-circuit is at an intermediate granularity level between the complete circuit to be analyzed and the components, performing feature extraction according to the sub-circuit can bridge the gap between the detailed components and the overall circuit, thereby helping the circuit feature extraction model better understand the circuit and further improving the accuracy of the features extracted by the circuit feature extraction model.

[0090] Among them, for the sub-circuits split according to the registers, since each sub-circuit can include the complete state transition of the registers within a single clock cycle, including all the timing paths and logical calculations of the registers. Therefore, splitting the sub-circuits according to the registers can help the circuit feature extraction model better learn the combinational behavior and sequential behavior of the circuit to be analyzed, thereby improving the accuracy of the fusion features generated by the circuit feature extraction model.

[0091] Figure 6 Fig. 5 shows a specific implementation flowchart of a circuit analysis method S103 provided in the third embodiment of the present application. Refer to Figure 6 , compared with Figure 1 the embodiments described above, S103 in a circuit analysis method provided in this embodiment includes: S601 to S604, which are specifically described in detail as follows:

[0092] S601. Calculate the similarity between the fusion feature and the candidate feature of the candidate circuit.

[0093] In the embodiments of the present application, after the electronic device obtains the fusion feature of the circuit to be analyzed, it can obtain the candidate circuit and the candidate feature corresponding to the candidate circuit from the preset database. Among them, the candidate circuit can be an implemented digital integrated circuit. Specifically, the candidate feature corresponding to the candidate circuit can also be generated by the electronic device through the methods of S101 to S102 in the first embodiment of the present application. When the electronic device refers to the content of S101 to S102 in the first embodiment of the present application for understanding, it can replace the "circuit to be analyzed" with the "candidate circuit" and replace the "fusion feature" with the "candidate feature" to understand the specific generation method of the candidate feature. The electronic device can input the fusion feature of the circuit to be analyzed and the candidate feature of the candidate circuit into a preset similarity function to calculate the similarity. Among them, the similarity function can be any function known to those skilled in the art, such as the cosine similarity function, the Manhattan distance function, the Pearson correlation coefficient function, etc., that can calculate the similarity.

[0094] S602. Use the candidate circuit with a similarity greater than the similarity threshold as the associated circuit of the circuit to be analyzed.

[0095] In the embodiments of the present application, for any candidate circuit, the electronic device can determine whether the similarity corresponding to the candidate circuit is greater than the similarity threshold. If the similarity corresponding to a certain candidate circuit is greater than the similarity threshold, the electronic device can identify the candidate circuit as the associated circuit of the circuit to be analyzed. If the similarity corresponding to a certain candidate circuit is less than or equal to the similarity threshold, the electronic device may not identify the candidate circuit as the associated circuit of the circuit to be analyzed.

[0096] S603. Calculate the predicted metrics of the circuit to be analyzed based on the circuit metrics of the associated circuits and the weight coefficients corresponding to the similarity.

[0097] In this embodiment, the preset database may also store the circuit metrics corresponding to each candidate circuit. Among them, the circuit metrics of a certain candidate circuit can be obtained by a researcher conducting a circuit test experiment on the candidate circuit. The circuit metrics of a certain candidate circuit may include at least one of circuit area, circuit power consumption, measured value of a single timing margin, measured value of the worst negative timing margin, and measured value of the total negative margin. After the electronic device determines the associated circuits corresponding to the circuit to be analyzed, it can calculate the weight coefficients of the associated circuits according to the similarity corresponding to each associated circuit. The electronic device can also obtain the circuit metrics corresponding to each associated circuit from the preset database. Then, the electronic device can perform weighted summation on the circuit metrics of all associated circuits according to the weight coefficients of each associated circuit to determine the predicted metrics of the circuit to be analyzed. Exemplarily, the electronic device can perform weighted summation on the circuit areas of all associated circuits according to the weight coefficients of each associated circuit to determine the predicted area of the circuit to be analyzed.

[0098] S604. Generate an analysis result corresponding to the circuit to be analyzed based on the associated circuits and the predicted metrics.

[0099] In this embodiment, after the electronic device determines the associated circuits and the predicted metrics of the circuit to be analyzed, it can generate an analysis result corresponding to the circuit to be analyzed based on the associated circuits and the predicted metrics, and display the generated analysis result through a preset display device.

[0100] Model training stage

[0101] In a possible implementation, refer to Figure 7 , which shows a schematic diagram of a model training process provided by an embodiment of the present application. As Figure 7As shown, before the electronic device generates the fused features through the feature extraction network and the feature fusion network, it can first obtain the first training network and the second training network corresponding to each description method, and perform model training on the first training network and the second training network to obtain the feature extraction network and the feature fusion network. Among them, the first training network can be a neural network capable of performing feature extraction operations on the description information. The second training network can be a neural network capable of performing feature fusion operations on multiple unimodal features. It should be noted that the training circuit in each of the following training tasks can be a circuit that includes a complete circuit structure like the circuit to be analyzed, or a circuit that only includes a partial circuit structure like a sub-circuit. The R & D personnel can select the corresponding training circuit according to the analysis requirements. For example, when the R & D personnel need to perform circuit analysis on a sub-circuit split according to a register, the training circuit can also be a circuit split from the complete circuit structure according to the register.

[0102] After the electronic device obtains the first training network and the second training network, it can train the first training network and / or the second training network through four training tasks in sequence to obtain the feature extraction network and the feature fusion network. Specifically, as Figure 7 shown, the electronic device can first perform intra-modal contrast learning on each first training network through Training Task 1. After completing Training Task 1, the electronic device can perform cross-modal contrast learning on all the first training networks through Training Task 2. After completing Training Task 2, the electronic device can perform multi-modal fusion contrast learning on the second network through Training Task 3. After completing Training Task 3, the electronic device can train all the first training networks and the second training network simultaneously through Training Task 4.

[0103] Each training method can be specifically as follows:

[0104] Training Task 1: Perform intra-modal contrast learning on each first training network respectively. Specifically, for the first training network corresponding to a certain description method, the electronic device can process the training information corresponding to the description method of the first training network through the first training network to generate the first initial feature. Then, the electronic device can calculate the first error value of the first training network according to the first initial feature and the expected feature corresponding to the training information, and update the parameters in the first training network according to the first error value. The electronic device can repeatedly execute the above operations of generating the first error value corresponding to the first initial feature and updating according to the first error value for any first training network until the first error value is less than or equal to the first error threshold, and the electronic device can determine that the first training network has completed Training Task 1. When all the first training networks have completed Training Task 1, the electronic device can stop executing Training Task 1 and start executing Training Task 2.

[0105] In a possible implementation, when the training information in the training dataset is masked information, the electronic device can perform Training Task 1 by using the training dataset containing the masked information. Specifically, the training dataset may include masked information corresponding to different description methods and expected features respectively corresponding to each masked information. The masked information may be information generated by randomly selecting content in the description information corresponding to the circuit to be trained and then replacing the selected content with a mask. Specifically, when the description method is a graphical description method, the first masked information may be information generated by randomly selecting circuit operators in the circuit diagram corresponding to the circuit to be trained and then replacing the selected circuit operators with a mask; when the description method is a text description method, the second masked information may be information generated by randomly selecting words in the function summary corresponding to the circuit to be trained and then replacing the selected words with a mask; when the description method is a programming language description method, the third masked information may be information generated by randomly selecting words in the hardware description language corresponding to the circuit to be trained and then replacing the selected words with a mask.

[0106] Specifically, when training based on the masked information, the specific calculation formula for the first error value can be as follows:

[0107]

[0108] where MSE can represent the first error value of the network to be trained corresponding to a certain description method; N1 can be the total number of masked information corresponding to this description method in the training dataset; y i can represent the first initial feature generated by the network to be trained corresponding to this description method based on the i-th masked information corresponding to this description method; can represent the expected feature of the i-th masked information corresponding to this description method.

[0109] In a possible implementation, when the training information in the training dataset is positive sample information and negative sample information, the electronic device can perform Training Task 1 through the training dataset containing the positive sample information and the negative sample information. Among them, the positive sample information can be the description information corresponding to the circuit after the equivalent transformation of the training circuit, and the negative sample information can be the description information corresponding to the circuit that has the same function as the training circuit but has a completely different structure. The expected feature can include the expected feature corresponding to the training circuit. The electronic device can process the positive sample information and the negative sample information respectively through the first training network to obtain the first initial feature corresponding to the positive sample information and the second initial feature corresponding to the negative sample information. Then, the electronic device calculates the first similarity between the first initial feature and the expected feature, and the second similarity between the second initial feature and the expected feature, and determines the first error value according to the first similarity and the second similarity.

[0110] In this case, when training according to the positive sample information and the negative sample information, the function for calculating the first error value can be specifically as follows:

[0111]

[0112] Among them, CL can represent the first error value of the network to be trained corresponding to a certain description method; N2 can represent the number of training circuits in the training dataset; can represent the first initial feature generated by the network to be trained corresponding to this description method based on the i-th positive sample information corresponding to this description method; y i can represent the expected feature corresponding to the training circuit; can represent the second initial feature generated by the network to be trained corresponding to this description method based on the i-th negative sample information corresponding to this description method; τ can represent a preset hyperparameter; K can represent the number of negative sample information corresponding to a certain training circuit in this description method; sim(,) can be a function for calculating the similarity between two feature matrices.

[0113] Training Task 2: Conduct cross-modal contrastive learning on different first training networks. Specifically, for the first training network corresponding to a certain description method, the electronic device can process the training information corresponding to the description method of the first training network through the first training network to generate first initial features. Then, the electronic device can determine and calculate the second error value between each of the to-be-trained networks based on the first initial features of all the to-be-trained networks, and update the parameters in the first training network according to the second error value. The electronic device can repeatedly execute the operation of generating the second error value corresponding to the first initial features and updating according to the second error value until the second error value is less than or equal to the second error threshold, at which point the electronic device can determine that Training Task 2 has been completed. When all the first training networks have completed Training Task 2, the electronic device can stop executing Training Task 2 and start executing Training Task 3.

[0114] Among them, the function for calculating the second error value can be specifically as follows:

[0115]

[0116] Among them, L loss can represent the second error value; N3 can represent the number of training information; CL i,S can represent the i-th first error value obtained by training the positive and negative sample information of the to-be-trained network corresponding to the text description method; CL i,G can represent the i-th first error value obtained by training the positive and negative sample information of the to-be-trained network corresponding to the graphical description method; CL i,C can represent the i-th first error value obtained by training the positive and negative sample information of the to-be-trained network corresponding to the programming language description method. Among them, the specific calculation method of each first error value can be the same as the calculation method when training based on positive and negative sample information in Training Task 1. Please refer to the content in Training Task 1 and will not be elaborated here.

[0117] Training Task 3: Conduct fusion training on the second training network.

[0118] In a possible implementation, the training information in the training dataset can be a feature composed of the second mask information in the form of text description, the circuit diagram in the form of graphic description, and the hardware description language in the form of programming language description by a certain training circuit. After the second training network processes the training information, it can generate the predicted value corresponding to each mask in the second mask information. Then, the electronic device can calculate the third loss value corresponding to the second training network according to the true value and the predicted value corresponding to each mask in the second mask information, and update the second training network according to the third loss value. When the third loss value is less than or equal to the third threshold, the electronic device can determine that training task three has been completed. The electronic device can stop executing training task three and start executing training task four.

[0119] Specifically, the specific calculation formula of the third loss value in the above method can be as follows:

[0120]

[0121] Among them, CE can represent the third loss value; V can represent the number of masks in the second mask information; y mask,i can represent the true value corresponding to the i-th mask; p mask,i can represent the predicted value corresponding to the i-th mask.

[0122] Training task four: Train all the first training networks and the second training network simultaneously. Specifically, the electronic device can first process the training information corresponding to the description method of each first training network through each first training network to generate the first initial features. Then, the electronic device can input all the first initial features into the second training network to generate the second initial features. The electronic device can calculate the fourth loss value between the second initial features and the expected features corresponding to the training information, and update all the first training networks and the second training network according to the fourth loss value. The electronic device can repeatedly execute the operation of generating the fourth loss value corresponding to the second initial features and updating according to the fourth loss value until the fourth loss value is less than or equal to the fourth error threshold. The electronic device can determine that training task four has been completed. When training task four is completed, the electronic device can stop executing the model training operation, and determine the current first training network as the feature extraction network and the current second training network as the feature fusion network.

[0123] Through the training method provided by the embodiments of the present application, since the electronic device can separately train and jointly train the first training network and the second training network through a variety of different training tasks. Among them, separate training enables each training network to focus on specific tasks for learning, facilitating developers to adjust network parameters targeted, while joint training can improve the generalization ability of training and reduce the overfitting phenomenon. Thus, it can be seen that the method provided by the embodiments of the present application can improve the accuracy of the trained feature extraction network and feature fusion network.

[0124] In the solution, in order to prove the effectiveness of the solution, the developers conducted a verification experiment on the circuit analysis method provided by the embodiments of the present application. The specific content of the verification experiment is as follows:

[0125] 1. Construct a dataset

[0126] To verify the method provided by the embodiments of the present application, the developers constructed an original dataset containing 41 original circuits, and these original circuits can come from various representative open-source benchmarks. Further, the original dataset can also include sub-circuits corresponding to each original circuit. Specifically, the original dataset can contain 7166 pairs of aligned register transfer level sub-circuits and netlist sub-circuits, and each sub-circuit of the register transfer level circuit can be described in three ways: text description, graphical description, and programming language description. To achieve contrastive learning, the developers used open-source tools (such as Yosys) to enhance the digital integrated circuits in the original dataset, and generated multiple positive samples by using the method of functional equivalent transformation, so that the number of sub-circuits in the original dataset finally reached 57328. The developers divided the original dataset into a training dataset and a test dataset according to the ratio of 80 / 20. Among them, the original circuit consists of tens of thousands of graph nodes and millions of code tokens, which makes it extremely challenging for existing graph and text models to process. In contrast, the number of nodes and code tokens of the sub-circuit is about 1000 times smaller, thus making scalable and fine-grained representation learning possible. Therefore, the effectiveness of the original dataset has been proven in the experiment.

[0127] 2. Select the existing technology as a control

[0128] When conducting experimental verification, the R & D personnel used three existing technologies, namely, hardware task-specific solutions, general text encoders, and software code encoders, as controls. Among them, the hardware solutions can include task-specific supervision methods RTL-Timer and MasterRTL, and the self-supervised pre-trained circuit encoder sNs v2. The software solutions can include various existing software code encoders such as Codesage, the encoder of CodeT5+, and UnixCoder. Among them, the input limit of the existing software code encoders is 1024 tokens. Therefore, before conducting the experiment, the R & D personnel can trim the hardware description language to adapt to the input limit of the software code encoders. As for the general text encoder, the R & D personnel used NV-Embed-V1 as a control, whose input limit is 23,000 tokens and is one of the best-performing text encoders in the existing technologies.

[0129] 3. Determine the evaluation metrics

[0130] To verify the effectiveness of this solution, the R & D personnel can verify the accuracy of the prediction metrics obtained in the embodiments of this application through the method of regression metric evaluation. The specific evaluation metrics can include the correlation coefficient between the label and the prediction metric and the Mean Absolute Percentage Error (MAPE).

[0131] 4. Verification results

[0132] To verify the effectiveness of this solution, the R & D personnel can verify the accuracy of the prediction metrics obtained in the embodiments of this application through the method of regression metric evaluation. The experiment found that the prediction metrics obtained by the method provided in the embodiments of this application are always better than all existing technologies. Its high correlation and low mean absolute percentage error prove the effectiveness and reliability of the method provided in the embodiments of this application. Compared with the existing technologies, the average absolute percentage error of the single timing margin, the worst negative timing margin, and the predicted area predicted by the method provided in the embodiments of this application is reduced by 5% compared with the single timing margin, the worst negative timing margin, and the predicted area predicted by the existing technologies. Compared with the existing technologies, the average absolute percentage error of the total negative margin predicted by the method provided in the embodiments of this application is reduced by 10%. Compared with the existing technologies, the average absolute percentage error of the predicted power consumption obtained by the method provided in the embodiments of this application is decreased by 13%.

[0133] Different from hardware solutions that usually require a large number of task-specific modifications, the circuit feature extraction model provided by the embodiments of the present application serves as a flexible basis for multiple tasks, allowing for fine-tuning without significant adjustments, thereby enhancing its versatility. In addition, the significant performance gap between the circuit feature extraction model provided by the embodiments of the present application and text / software-based models highlights the importance of constructing a hardware-specific model like the circuit feature extraction model provided by the embodiments of the present application in tasks in the field of hardware design.

[0134] To verify the effectiveness of the associated circuits retrieved by the embodiments of the present application, the R & D personnel conducted a detailed evaluation of the associated circuits obtained by the embodiments of the present application and compared them with the associated circuits retrieved based on the prior art. Through experiments, it is proved that the method provided by the present embodiment for generating the associated circuits corresponding to the circuits to be analyzed always performs best in the first retrieval of all tasks, achieving the lowest mean absolute percentage error. Specifically, during the experiment, the R & D personnel can set the number of associated circuits to 1 to minimize errors.

[0135] 5. Adjustment direction

[0136] The researchers further studied how it changes with the increase in the model size and the training sample size. The results show that increasing the parameters of the model and the sample size of the training samples can further improve the analysis accuracy, demonstrating the scalability of the method provided by the embodiments of the present application. This indicates that the R & D personnel can select a larger network to be trained and more training samples with a larger number of samples for training, which can further increase the accuracy of the trained feature extraction network and / or feature fusion network.

[0137] Specifically, when the number of parameters in the network to be trained increases from 270 million to 500 million, the error rate of the analysis results obtained by the method provided by the embodiments of the present application can be reduced from 19% to 12%. This trend indicates that a network to be trained with a larger number of parameters can capture more complex structural and semantic details in the circuit to be analyzed, thereby improving the analysis accuracy. Similarly, increasing the sample size of the training samples can also significantly reduce the error rate of the analysis results. Specifically, when the sample size of the training samples is quadrupled, the error rate of the analysis results obtained by the method provided by the embodiments of the present application is reduced from 24% to 12%. Therefore, it is necessary to use training samples with a larger sample size for training.

[0138] It should be noted that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0139] Refer to Figure 8, showing a schematic diagram of a circuit analysis device provided by an embodiment of the present application, which may specifically include an information acquisition module 801, a feature acquisition module 802, and an analysis module 803, where:

[0140] The information acquisition module 801 is configured to acquire description information of the circuit to be analyzed under different description methods; the description information under different description methods at least includes a function summary corresponding to the text description method, a circuit diagram corresponding to the graphic description method, and a hardware description language corresponding to the programming language description method.

[0141] The feature acquisition module 802 is configured to perform feature fusion on the single-modal features obtained based on the description information to generate the fusion features of the circuit to be analyzed.

[0142] The analysis module 803 is configured to input the fusion features into an analysis model to generate an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes an associated circuit corresponding to the circuit to be analyzed and / or a prediction index corresponding to the circuit to be analyzed.

[0143] The information acquisition module may also be configured to split the circuit to be analyzed into multiple sub-circuits; and acquire the description information of each sub-circuit under different description methods.

[0144] The feature acquisition module may also be configured to perform feature extraction on the description information under different description methods through different feature extraction networks to determine the single-modal features of the sub-circuits; the different feature extraction networks respectively correspond to the different description methods; perform feature fusion on the multiple single-modal features of the sub-circuits through a feature fusion network to determine the sub-fusion features of the sub-circuits; and perform feature splicing on the sub-fusion features of the multiple sub-circuits to determine the fusion features corresponding to the circuit to be analyzed.

[0145] The feature acquisition module may also be configured to input the function summary into the feature extraction network corresponding to the text description method to determine the first single-modal feature of the sub-circuit; input the circuit diagram into the feature extraction network corresponding to the graphic description method to determine the second single-modal feature of the sub-circuit; and input the hardware description language into the feature extraction network corresponding to the programming language description method to determine the third single-modal feature of the sub-circuit.

[0146] The feature acquisition module may also be configured to split the circuit to be analyzed based on the registers in the circuit to be analyzed to obtain the sub-circuits; each sub-circuit includes one of the registers; the registers included in different sub-circuits are different.

[0147] The analysis module can also be used to input the fusion feature into an analysis model, calculate the similarity between the fusion feature and the candidate feature of a candidate circuit; use the candidate circuit with a similarity greater than the similarity threshold as the associated circuit of the circuit to be analyzed; calculate the predicted index of the circuit to be analyzed according to the circuit index of the associated circuit and the weight coefficient corresponding to the similarity; and generate an analysis result corresponding to the circuit to be analyzed according to the associated circuit and the predicted index.

[0148] The predicted indexes in the analysis module include at least one of the predicted area of the circuit to be analyzed, the predicted power consumption of the circuit to be analyzed, the individual timing margin of each register, the worst negative timing margin of the circuit to be analyzed, and the total negative margin of the circuit to be analyzed.

[0149] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the description in the method embodiment section.

[0150] Referring to Figure 9 , a schematic diagram of an electronic device provided by an embodiment of the present application is shown. As Figure 9 shown, the electronic device 900 in the embodiment of the present application includes: a processor 910, a memory 920, and a computer program 921 stored in the memory 920 and executable on the processor 910. When the processor 910 executes the computer program 921, the steps in each embodiment of the above circuit analysis method are implemented, such as Figure 1 the steps S101 to S103 shown. Alternatively, when the processor 910 executes the computer program 921, the functions of each module / unit in each apparatus embodiment above are implemented, such as Figure 8 the functions of the modules 801 to 803 shown.

[0151] Exemplarily, the computer program 921 can be divided into one or more modules / units. The one or more modules / units are stored in the memory 920 and executed by the processor 910 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and these instruction segments can be used to describe the execution process of the computer program 921 in the electronic device 900. For example, the computer program 921 can be divided into an information acquisition module, a feature acquisition module, and an analysis module. The specific functions of each module are as follows:

[0152] The information acquisition module is used to acquire the description information of the circuit to be analyzed in different description methods; the description information in different description methods at least includes the function summary corresponding to the text description method, the circuit diagram corresponding to the graphic description method, and the hardware description language corresponding to the programming language description method.

[0153] A feature acquisition module, configured to perform feature fusion on unimodal features obtained based on the description information to generate fusion features of the circuit to be analyzed;

[0154] An analysis module, configured to input the fusion features into an analysis model to generate an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes an associated circuit corresponding to the circuit to be analyzed and / or a prediction index corresponding to the circuit to be analyzed.

[0155] The electronic device 900 may be a computing device such as a desktop computer or a cloud server. The electronic device 900 may include, but is not limited to, a processor 910 and a memory 920. Those skilled in the art can understand that Figure 9 This is merely an example of the electronic device 900 and does not constitute a limitation on the electronic device 900. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the electronic device 900 may further include input / output devices, network access devices, a bus, etc.

[0156] The processor 910 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0157] The memory 920 may be an internal storage unit of the electronic device 900, such as a hard disk or memory of the electronic device 900. The memory 920 may also be an external storage device of the electronic device 900, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 900. Further, the memory 920 may also include both the internal storage unit and the external storage device of the electronic device 900. The memory 920 is used to store the computer program 921 and other programs and data required by the electronic device 900. The memory 920 may also be used to temporarily store data that has been output or is to be output.

[0158] An embodiment of the present application also discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the circuit analysis method described in each of the foregoing embodiments is implemented.

[0159] An embodiment of the present application also discloses a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the circuit analysis method described in each of the foregoing embodiments is implemented.

[0160] An embodiment of the present application also discloses a computer program product. When the computer program product runs on a computer, the computer is caused to execute the circuit analysis method described in each of the foregoing embodiments.

[0161] The foregoing embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in each of the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present application, and should all be included in the protection scope of the present application.

Claims

1. A circuit analysis method, characterized in that: include: Obtaining description information of the circuit to be analyzed in different description modes; the description information in different description modes at least includes a function summary corresponding to the text description mode, a circuit diagram corresponding to the graphic description mode, and a hardware description language corresponding to the programming language description mode; Performing feature fusion on the single-modal features obtained based on the description information to generate fused features of the circuit to be analyzed; The fusion feature is input into the analysis model to generate an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes an associated circuit corresponding to the circuit to be analyzed and / or a prediction index corresponding to the circuit to be analyzed.

2. The method according to claim 1, characterized in that The obtaining description information of the circuit to be analyzed in different description modes includes: Splitting the circuit to be analyzed into multiple sub-circuits; The description information of each of the sub-circuits in different description modes is obtained.

3. The method according to claim 2, characterized in that The step of fusing the single-mode features obtained based on the description information to generate fused features of the circuit to be analyzed includes: Extracting features from the description information in the different description modes through different feature extraction networks to determine the single-mode features of the sub-circuit; the different feature extraction networks correspond to the different description modes respectively; Performing feature fusion on the multiple single-modal features of the sub-circuit through a feature fusion network to determine a sub-fusion feature of the sub-circuit; The sub-fusion features of the plurality of sub-circuits are concatenated to determine the fusion feature corresponding to the circuit to be analyzed.

4. The method according to claim 3, characterized in that The extracting features of the description information in the different description modes by using different feature extraction networks to determine the single-mode features of the sub-circuit includes at least one of the following: Inputting the function summary into a feature extraction network corresponding to the text description mode to determine a first single-mode feature of the subcircuit; Inputting the circuit diagram into a feature extraction network corresponding to the graphical description method to determine a second single-mode feature of the sub-circuit; The hardware description language is input into a feature extraction network corresponding to the programming language description mode to determine a third single-mode feature of the sub-circuit.

5. The method according to any one of claims 2 to 4, characterized in that: The step of dividing the circuit to be analyzed into a plurality of sub-circuits comprises: The circuit to be analyzed is split based on registers in the circuit to be analyzed to obtain the sub-circuits; each of the sub-circuits includes one register; and different sub-circuits include different registers.

6. The method according to any one of claims 1 to 4, characterized in that: The step of inputting the fusion feature into an analysis model to generate an analysis result corresponding to the circuit to be analyzed includes: Inputting the fused features into an analysis model, and calculating the similarity between the fused features and the candidate features of the candidate circuits; Taking the candidate circuits whose similarity is greater than a similarity threshold as associated circuits of the circuit to be analyzed; Calculating a prediction index of the circuit to be analyzed according to the circuit index of the associated circuit and a weight coefficient corresponding to the similarity; An analysis result corresponding to the circuit to be analyzed is generated according to the associated circuit and the prediction index.

7. The method according to any one of claims 1 to 4, characterized in that: The prediction index includes at least one of the predicted area of ​​the circuit to be analyzed, the predicted power consumption of the circuit to be analyzed, the single timing margin of each register, the worst negative timing margin of the circuit to be analyzed, and the total negative margin of the circuit to be analyzed.

8. A circuit analysis device, characterized in that: include: An information acquisition module, used to acquire description information of the circuit to be analyzed in different description modes; the description information in different description modes at least includes a function summary corresponding to a text description mode, a circuit diagram corresponding to a graphic description mode, and a hardware description language corresponding to a programming language description mode; A feature acquisition module, used for performing feature fusion on the single-mode features obtained based on the description information to generate fusion features of the circuit to be analyzed; The analysis module is used to input the fusion feature into the analysis model to generate the analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit includes the associated circuit corresponding to the circuit to be analyzed and / or the prediction index corresponding to the circuit to be analyzed.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the electronic device implements the circuit analysis method according to any one of claims 1 to 8.

10. A computer program product, characterized in that The invention comprises a computer program, which enables the circuit analysis method according to any one of claims 1 to 8 to be executed when the computer program is executed.

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