Wide-area power waveform synchronous monitoring system and synchronous monitoring method

Abstract

The invention provides a wide-area power waveform synchronous monitoring system and a synchronous monitoring method, in the synchronous monitoring system, firstly, a terminal layer node adopts a multi-channel synchronous sampling technology in combination with cross calibration, phase error detection and correction filtering, so that data of different signal sources can be ensured to be collected at the same time; and delay caused by hardware difference and different transmission paths is eliminated, so that the synchronization precision and accuracy of data uploaded to the edge layer node are relatively high, then the edge layer node can maintain the time synchronization precision at a relatively high level by executing a cross-hierarchy clock synchronization mechanism, and finally, synchronous analysis is performed through the master station layer node, so that the synchronization precision of the data uploaded to the edge layer node is improved. And the reliability of a monitoring result is ensured. According to the invention, the terminal layer node, the edge layer node and the master station layer node execute corresponding synchronous monitoring tasks at different levels, the synchronization precision can be improved, and the synchronization error can be reduced, so that the strict requirement of high-precision time synchronization is met, and the reliability of a synchronous monitoring result is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of smart grid monitoring, and particularly relates to a wide-area power waveform synchronous monitoring system and a synchronous monitoring method. Background Art

[0002] Wide-area power waveform synchronous monitoring mainly uses time synchronization technology to monitor and analyze waveforms of various electrical quantities such as voltage and current in the power grid. In this way, the operating state of the power grid can be grasped in real time, potential problems can be discovered in time, and the safe and stable operation of the power system can be ensured.

[0003] In traditional time synchronization technology, GPS (Global Positioning System) satellite timing, NTP (Network Time Protocol), and Precision Time Protocol constitute the main solution system.

[0004] In the GPS satellite timing solution, μs (microsecond)-level synchronization is mainly achieved through satellite signals. However, satellite signals are vulnerable to environmental influences such as building blockage and electromagnetic interference, resulting in synchronization errors often exceeding 1 μs in indoor or complex terrain scenarios. NTP mainly performs time calibration based on the network of the software protocol stack. Although this solution is simple to deploy, it is limited by the operating system scheduling and network jitter, and the synchronization accuracy can only be maintained at the millisecond level. The Precision Time Protocol includes IEEE 1588v2 / PTP (Precision Time Synchronization Protocol), which is mainly based on hardware timestamps. Although sub-microsecond-level accuracy can be achieved in a local area network environment, when deployed in a complex network topology with multi-hop switching, routing asymmetry, or burst traffic, the uncertainty of path delay and the non-linear response of the clock servo system will cause a significant increase in cumulative clock drift. Especially in the cross-heterogeneous network domain synchronization scenario, the frequency offset compensation error between the master and slave clocks increases exponentially, ultimately resulting in the degradation of synchronization accuracy to the order of dozens of microseconds.

[0005] In summary, the traditional time synchronization technology has too large synchronization errors and insufficient synchronization accuracy, and it is difficult to meet the stringent requirements of emerging fields such as power distribution and utilization system operation regulation and massive source-load control for high-precision time synchronization at the nanosecond level. Summary of the Invention

[0006] In order to overcome the defects of the above-mentioned traditional time synchronization technology with too large synchronization errors and insufficient synchronization accuracy, the present invention provides a wide-area power waveform synchronous monitoring system, including: a master station layer node, an edge layer node, and multiple terminal layer nodes that are communicatively connected to each other; Each of the terminal layer nodes is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node; The edge layer node is used to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform and upload it to the master station layer node; The master station layer node is used to perform synchronous analysis on the synchronized power waveform based on the reference clock according to a set time synchronization accuracy to obtain a synchronous monitoring result of the power waveform.

[0007] Optionally, the terminal layer node is specifically used to obtain a reference clock provided by a GPS / PTP clock source, lock the local clock with the reference clock by using a DPLL digital phase-locked loop to obtain a clock signal; adjust the clock signal by using a calibrated clock distributor to obtain a unified time reference; perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0008] Optionally, the terminal layer node is specifically used to calculate the correlation between the multiple sampling results by using a cross-correlator; analyze the phase deviation between different channels by using a phase error detection unit based on the correlation between the multiple sampling results to obtain multiple error feedback sampling results.

[0009] Optionally, the terminal layer node is specifically used to read filter coefficients corresponding to the multiple error feedback sampling results from a coefficient memory; use a shift register chain to transfer the multiple error feedback sampling results to a MAC operation unit array in a set order; perform filtering based on the filter coefficients by using the MAC operation unit array to obtain a corrected filtering result; perform delay compensation on the corrected filtering result to obtain an initial power waveform.

[0010] Optionally, the terminal layer node is specifically used to perform error calculation based on the multiple sampling results to obtain an error calculation result; if the error calculation result is greater than a preset error threshold, adjust a delay line to perform delay compensation on the corrected filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and use the corrected filtering result after delay compensation at this time as the initial power waveform.

[0011] Optionally, the terminal layer node is specifically used to adjust the delay amount of an initial delay value based on a proportional-integral algorithm to generate a new delay value, and update the new delay value to a delay register to achieve dynamic calibration of the delay line.

[0012] Optionally, the edge layer nodes are configured in a substation and interconnected with the master station layer nodes through a 5G network. The terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; and / or The edge layer nodes are configured in a distribution substation area and interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution substation area are interconnected with the edge layer nodes through power line carrier PLC and optical fibers.

[0013] Optionally, the initial power waveform is fused with energy flow and information flow.

[0014] On the other hand, the present invention also provides a wide-area power waveform synchronous monitoring method, including: Performing multi-channel synchronous sampling based on a reference clock to obtain a plurality of sampling results; Performing cross-calibration and phase error detection on the plurality of sampling results to obtain a plurality of error feedback sampling results; Performing correction filtering and delay compensation on the plurality of error feedback sampling results to obtain an initial power waveform and uploading it to the edge layer nodes, so that the edge layer nodes perform cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master station layer nodes perform synchronous analysis on the synchronized power waveform according to a set time synchronization accuracy based on the reference clock to obtain a synchronous monitoring result of the power waveform.

[0015] Optionally, the performing multi-channel synchronous sampling based on a reference clock to obtain a plurality of sampling results includes: Obtaining a reference clock provided by a GPS / PTP clock source, and locking the local clock with the reference clock by using a DPLL digital phase-locked loop to obtain a clock signal; Adjusting the clock signal by using a calibrated clock distributor to obtain a unified time reference; Performing multi-channel synchronous sampling under the unified time reference to obtain a plurality of sampling results.

[0016] Optionally, the performing cross-calibration and phase error detection on the plurality of sampling results to obtain a plurality of error feedback sampling results includes: Calculating the correlation between the plurality of sampling results by using a cross-correlator; Based on the correlation between the plurality of sampling results, using a phase error detection unit to analyze the phase deviation between different channels to obtain a plurality of error feedback sampling results.

[0017] Optionally, the performing correction filtering and delay compensation on the plurality of error feedback sampling results to obtain an initial power waveform includes: Reading the filter coefficients corresponding to the plurality of error feedback sampling results in a coefficient memory; Using a shift register chain, the multiple error feedback sampling results are transmitted to the MAC operation unit array in a set order; Based on the filter coefficients, filtering is performed using the MAC operation unit array to obtain a corrected filtering result; delay compensation is performed on the corrected filtering result to obtain an initial power waveform.

[0018] Optionally, the delay compensation is performed on the corrected filtering result to obtain an initial power waveform, including: Error calculation is performed based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, the delay line is adjusted to perform delay compensation on the corrected filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and the corrected filtering result after delay compensation at this time is used as the initial power waveform.

[0019] Optionally, the adjustment of the delay line includes: Based on the proportional-integral algorithm, the delay amount of the initial delay value is adjusted to generate a new delay value, and the new delay value is updated to the delay register to achieve dynamic calibration of the delay line.

[0020] Optionally, the edge layer nodes are configured in a substation and are interconnected with the master station layer nodes through a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; and / or The edge layer nodes are configured in a distribution area and are interconnected with the master station layer nodes through optical fibers, and the terminal layer nodes in the distribution area are interconnected with the edge layer nodes through power line carrier PLC and optical fibers.

[0021] Optionally, the initial power waveform is fused with an energy flow and an information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow reflecting the system operation state.

[0022] On the other hand, the present invention further provides a wide-area power waveform synchronous monitoring system, including: A multi-channel synchronous sampling module, configured to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; An error feedback module, configured to perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; A power waveform generation module, which is used to perform calibration filtering and delay compensation on the multiple error feedback sampling results, obtain an initial power waveform, and upload it to the edge layer node. The edge layer node is used to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform. And the master station layer node is used to perform synchronous analysis on the synchronized power waveform based on the reference clock according to the set time synchronization accuracy to obtain a synchronous monitoring result of the power waveform.

[0023] Optionally, the multi-channel synchronous sampling module includes: A clock locking unit, which is used to obtain a reference clock provided by a GPS / PTP clock source, and lock the local clock with the reference clock by using a DPLL digital phase-locked loop to obtain a clock signal; A clock synchronization unit, which is used to adjust the clock signal by using a calibrated clock distributor to obtain a unified time reference; A multi-channel sampling unit, which is used to perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0024] Optionally, the error feedback module includes: A cross-correlation calculation unit, which is used to calculate the correlation between the multiple sampling results by using a cross-correlator; An error feedback unit, which is used to analyze the phase deviation between different channels based on the correlation between the multiple sampling results by using a phase error detection unit to obtain multiple error feedback sampling results.

[0025] Optionally, the power waveform generation module includes: A coefficient reading unit, which is used to read the filter coefficients corresponding to the multiple error feedback sampling results in a coefficient memory; An error transfer unit, which is used to transfer the multiple error feedback sampling results to a MAC operation unit array in a set order by using a shift register chain; A filtering and compensation unit, which is used to perform filtering based on the filter coefficients by using the MAC operation unit array to obtain a calibrated filtering result; perform delay compensation on the calibrated filtering result to obtain an initial power waveform.

[0026] Optionally, the filtering and compensation unit is specifically used for: Perform error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, adjust the delay line to perform delay compensation on the calibrated filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and use the calibrated filtering result after delay compensation at this time as the initial power waveform.

[0027] Optionally, the filtering compensation unit is specifically configured to: Based on the proportional-integral algorithm, adjust the delay amount of the initial delay value to generate a new delay value, and update the new delay value to the delay register to achieve dynamic calibration of the delay line.

[0028] Optionally, the edge layer nodes are configured in a substation and interconnected with the master station layer nodes through a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; and / or The edge layer nodes are configured in a distribution transformer area and interconnected with the master station layer nodes through optical fibers, and the terminal layer nodes in the distribution transformer area are interconnected with the edge layer nodes through power line carrier PLC and optical fibers.

[0029] Optionally, the initial power waveform is fused with an energy flow and an information flow, and the information flow is a multi-dimensional time-frequency domain feature quantity of the energy flow reflecting the system operation state.

[0030] On the other hand, the present invention further provides an electronic device, including: at least one processor and a memory; the memory and the processor are connected through a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the above-mentioned wide-area power waveform synchronous monitoring method is implemented.

[0031] On the other hand, the present invention further provides a readable storage medium, on which an execution program is stored, and when the execution program is executed, the above-mentioned wide-area power waveform synchronous monitoring method is implemented.

[0032] Compared with the prior art, the beneficial effects of the present invention are: The present invention provides a wide-area power waveform synchronous monitoring system and a synchronous monitoring method. In this synchronous monitoring system, each terminal layer node is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; perform calibration filtering and delay compensation on the multiple error feedback sampling results to obtain the initial power waveform and upload it to the edge layer node; the edge layer node is used to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain the synchronous power waveform and upload it to the master station layer node; the master station layer node is used to perform synchronous analysis on the synchronous power waveform based on the reference clock according to the set time synchronization accuracy to obtain the synchronous monitoring result of the power waveform. First, the terminal layer node adopts multi-channel synchronous sampling technology combined with cross-calibration, phase error detection, and calibration filtering, which can ensure that data from different signal sources can be collected simultaneously, and eliminate delays caused by hardware differences and different transmission paths, making the data synchronization accuracy and accuracy uploaded to the edge layer node relatively high. Then, the edge layer node can maintain the time synchronization accuracy at a relatively high level by executing the cross-layer clock synchronization mechanism. Finally, through synchronous analysis by the master station layer node, the reliability of the monitoring result is ensured. It can be seen that in the present invention, the terminal layer node, the edge layer node, and the master station layer node perform corresponding synchronous monitoring tasks at different levels, which can improve the synchronization accuracy and reduce the synchronization error, thereby meeting the stringent requirements for nanosecond-level high-precision time synchronization in emerging fields such as power distribution and utilization system operation regulation and massive source-load control, and improving the reliability of the wide-area power waveform synchronous monitoring result. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the architecture of the wide-area power waveform synchronous monitoring system of the present invention; Figure 2 is a schematic diagram of the architecture of the wide-area power waveform synchronous monitoring system of the present invention; Figure 3 is a schematic diagram of the structure of the clock module of the present invention; Figure 4 is a schematic diagram of the structure of the ADC calibration module of the present invention; Figure 5 is a schematic diagram of the structure of the calibration filter of the present invention; Figure 6 is a schematic diagram of the structure of the delay compensation module of the present invention; Figure 7 is a schematic diagram of the synchronous sampling process of the present invention; Figure 8 is a schematic diagram of the process of the wide-area power disturbance and fluctuation synchronous monitoring method of the present invention; Figure 9 is a schematic diagram of the structure of the wide-area power disturbance and fluctuation synchronous monitoring system of the present invention; Figure 10 It is a schematic structural diagram of the electronic device of the present invention. Detailed implementation manners

[0034] The following further elaborates on the detailed implementation manners of the present invention in conjunction with the accompanying drawings.

[0035] Embodiment 1: The present invention provides a wide-area power waveform synchronization monitoring system. As Figure 1 shown, the synchronization monitoring system includes a master station layer node, an edge layer node, and multiple terminal layer nodes that are communicatively connected to each other.

[0036] The embodiment of the present invention provides a hierarchical system architecture, including a master station layer, an edge layer, and a terminal layer. The master station layer is configured with master station layer nodes, and may also integrate one or more control platforms such as a dispatching automation system, a distribution automation system, or a power quality monitoring system. The master station layer nodes can be deployed in the form of a master station server. The master station layer can rely on a dispatching automation system, a distribution automation system, or a power quality monitoring system. The edge layer is configured with edge layer nodes, and the terminal layer is configured with terminal layer nodes. The edge layer can be configured in a substation and / or a distribution transformer area, responsible for coordinating nodes in the jurisdiction and analyzing data characteristics. The edge layer nodes can include an edge computing gateway and / or an intelligent fusion terminal. The terminal layer is configured in a substation bus / user outgoing line, a distribution transformer area. The terminal layer nodes can include a bus monitoring terminal, a feeder monitoring terminal, a user outgoing line terminal, a distributed power source terminal, etc.

[0037] In a possible scenario, when the edge layer and the terminal layer are configured in a substation, the edge layer nodes are interconnected with the master station layer nodes through a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; when the edge layer and the terminal layer are configured in a distribution transformer area, the edge layer nodes are interconnected with the master station layer nodes through optical fibers, and the terminal layer nodes in the distribution transformer area are interconnected with the edge layer nodes through PLC (Power Line Carrier) / HPLC (High-speed Power Line Carrier), optical fibers. Through the hierarchical system architecture provided by the embodiment of the present invention, the terminal layer nodes can include multiple types of terminals and adopt multiple communication methods to realize the clock synchronization technology of monitoring nodes in multiple scenarios.

[0038] A specific system architecture is as Figure 2As shown in the figure, in the master station layer, the master station server is interconnected with the dispatching automation system through the IEC (International Electro Technical Commission) 61970 protocol, with the distribution automation system through IEC 61850, and with the power quality monitoring platform through PQDIF (Power Quality Data Interchange Format). The master station server is interconnected with the edge computing gateway deployed in the substation through a dedicated optical fiber network. The edge computing gateway is interconnected with the bus monitoring terminal through an optical fiber and connected to the feeder monitoring terminal through a network cable. The master station server is interconnected with the intelligent fusion node deployed in the distribution substation through 5G SA. The intelligent fusion node is interconnected with the user outgoing line terminal through PLC / HPLC and with the distributed power source terminal through an optical fiber. The intelligent fusion node is also interconnected with the edge computing gateway through IEEE 1588v2. In this system architecture, the substation and the distribution substation adopt a heterogeneous networking method combining optical fiber / 5G, and provide a cross-layer clock synchronization path between edge devices (see the dashed line in Figure 2 ).

[0039] In the embodiment of the present invention, each terminal layer node is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node; The edge layer node is used to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform and upload it to the master station layer node; The master station layer node is used to perform synchronous analysis on the synchronized power waveform according to the set time synchronization accuracy based on the reference clock to obtain a synchronous monitoring result of the power waveform.

[0040] In the embodiments of the present invention, first, the terminal layer nodes adopt multi-channel synchronous sampling technology combined with cross-calibration, phase error detection, and correction filtering, which can ensure that data from different signal sources can be collected simultaneously, and eliminate the delays caused by hardware differences and different transmission paths, so that the data synchronization accuracy and accuracy uploaded to the edge layer nodes are relatively high. Then, the edge layer nodes can maintain the time synchronization accuracy at a relatively high level by executing the cross-layer clock synchronization mechanism. Finally, through the synchronization analysis of the master station layer nodes, the reliability of the monitoring results is ensured. It can be seen that in the present invention, the terminal layer nodes, edge layer nodes, and master station layer nodes perform different synchronous monitoring tasks at different levels, which can improve the synchronization accuracy and reduce the synchronization error, thereby meeting the stringent requirements of emerging fields such as power distribution and utilization system operation regulation and massive source-load control for nanosecond-level high-precision time synchronization, and improving the reliability of wide-area power waveform synchronous monitoring results.

[0041] A clock synchronization module is deployed in the terminal layer nodes, such as Figure 3 shown. The clock synchronization module integrates a GPS / PTP clock source, a DPLL (Digital Phase-Locked Loop), and a calibration clock distributor. When the terminal layer nodes perform multi-channel synchronous sampling based on the reference clock and obtain multiple sampling results, they can obtain the reference clock provided by the GPS / PTP clock source, use the DPLL digital phase-locked loop to lock the local clock with the reference clock to obtain a clock signal, use the calibration clock distributor to adjust the clock signal to obtain a unified time reference, and perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0042] The GPS / PTP clock source provides a high-precision time reference. For example, the reference clock provided by the GPS / PTP clock source can be timed by the master station layer nodes. The DPLL digital phase-locked loop ensures the stability and accuracy of the local clock by locking the local clock of the terminal layer nodes with the reference clock provided by the GPS / PTP clock source. The calibration clock distributor can be responsible for adjusting and synchronizing the precise clock signal after the DPLL adjustment to ensure that the terminal layer nodes sample multiple data channels simultaneously under the unified time reference to obtain multiple sampling results.

[0043] An ADC (analog to digital converter) calibration module is also deployed in the terminal layer nodes, such as Figure 4As shown, the ADC calibration module integrates a cross-correlator and a phase error detection unit. When the terminal layer node performs cross-calibration and phase error detection on multiple sampling results to obtain multiple error feedback sampling results, it can use the cross-correlator to calculate the correlation between multiple sampling results; based on the correlation between multiple sampling results, the phase error detection unit is used to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

[0044] In a possible implementation, also Figure 4 taking [example] as an example, the terminal layer node samples and performs analog-to-digital conversion on the voltage signal through the voltage channel ADC, and samples and performs analog-to-digital conversion on the current signal through the current channel ADC to obtain the original data input to the cross-correlator, that is, multiple sampling results. Since the sampling is carried out under the precise time reference provided by the clock synchronization module, the synchronization of multi-channel sampling is ensured. The cross-correlator is used to process the two sets of original data to calculate the correlation in time between the two sets of original data, and possible phase differences or other errors can be identified. Then, the phase error detection unit can further analyze and quantify the phase error between the voltage signal and the current signal, and can accurately determine the phase deviation between the data of different channels. Based on the phase deviation, the error feedback sampling results are determined, ensuring the accuracy and reliability of the voltage and current waveforms based on the error feedback.

[0045] A calibration filter and a clock delay compensation module are also deployed in the terminal layer node. The error feedback result is used as an error input to the calibration filter and the clock delay compensation module for processing, which can effectively eliminate various errors introduced in the sampling process and ensure the high quality and reliability of the power waveform. As Figure 5 shown, the calibration filter integrates a coefficient memory, a shift register chain, and an array of MAC (Multiply-Accumulate) arithmetic units. When the terminal layer node performs calibration filtering and delay compensation on multiple error feedback sampling results to obtain the initial power waveform and upload it to the edge layer node, it can read the filter coefficients corresponding to multiple error feedback sampling results from the coefficient memory; use the shift register chain to transfer multiple error feedback sampling results to the MAC arithmetic unit array in a set order; based on the filter coefficients, use the MAC arithmetic unit array to perform filtering to obtain the calibration filtering result; perform delay compensation on the calibration filtering result to obtain the initial power waveform.

[0046] The calibration filter can be an FIR (Finite Impulse Response) calibration filter with a symmetric FIR structure. For example, it can be a 17th-order linear-phase FIR filter. The coefficient memory stores the filter coefficients used for calibration filtering. These coefficients are pre-calculated and stored according to a specific filtering algorithm, which determines the characteristics of the filter, such as frequency response, phase response, etc. For example, the filter coefficients can be dynamically updated through the LSM (Log-Structured Merge) algorithm. When the calibration filter receives an error input, it reads the corresponding filter coefficients from the coefficient memory to prepare for subsequent filtering operations. The shift register chain, as a digital circuit structure, is used for temporary storage and transmission of data, and is responsible for transmitting the error input data to the MAC operation unit array in a certain order. The functions of the shift register chain also include implementing data delay, enabling the timing control of the filter, and ensuring that data is processed at the correct time. Each MAC unit in the MAC operation unit array is responsible for performing one multiplication and addition operation, that is, multiplying an error input data by a filter coefficient and adding the calculated product to the previous calculation result. Through this series of operations, the error input data can be calibrated and filtered to eliminate or reduce the noise and interference components therein, and ensure that the finally output power waveform is accurate in both time and phase.

[0047] A possible implementation is as Figure 6 shown. When the terminal layer node performs delay compensation on the calibration filtering result to obtain the initial power waveform, it can calculate the error based on multiple sampling results to obtain the error calculation result. If the error calculation result is greater than the preset error threshold, it adjusts the delay line to perform delay compensation on the calibration filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and takes the calibration filtering result after delay compensation at this time as the initial power waveform.

[0048] When the error calculation result is not greater than the preset error threshold, the delay value of the current delay line can be saved as the current parameter.

[0049] To eliminate the time deviation between multiple channels and suppress high-frequency phase noise, when the terminal layer node adjusts the delay line, it can adjust the delay amount of the initial delay value based on the proportional-integral algorithm to generate a new delay value, and update this new delay value to the delay register to achieve dynamic calibration of the delay line. The terminal layer node performs sub-nanosecond fine-tuning on the sampling clock phase through a programmable delay line to eliminate the timing deviation caused by the difference in the transmission path between channels. In implementation, the terminal layer node can configure a programmable delay line structure inside the FPGA (Field Programmable Gate Array) to support a minimum step of 10 ps for clock phase adjustment. By adjusting the delay line, the terminal layer node can solve the problem of asynchronous sampling moments caused by differences in data transmission paths after voltage and current absorption, thereby eliminating the time deviation between channels. Moreover, by compensating for the jitter of the ADC clock tree, it can improve the harmonic measurement accuracy, suppress high-frequency phase noise, and adapt to dynamic environmental changes by automatically correcting delay fluctuations caused by temperature drift, device aging, etc.

[0050] Figure 7 A principle block diagram of a high-precision synchronous sampling process for multi-channel voltage and current based on sampling error feedback is proposed. The terminal layer node uses a GPS / PTP clock source to provide a reference clock. The DPLL digital phase-locked loop locks the local clock with the reference clock. The calibrated clock distributor synchronizes the clock signal adjusted by the DPLL. Then, the ADC driver clock generator drives the voltage channel ADC and the current channel ADC to collect voltage signals and current signals. The collected voltage signals and current signals are output synchronously. And by calculating the correlation of the two groups of signals in time through a cross-correlator, and then using a phase error detection unit to identify the phase deviation between the data of different channels, the error feedback sampling result is obtained. Then, the error feedback sampling result is corrected and filtered by a FIR correction filter, and delay compensation is performed by a clock delay compensation module to obtain the initial power waveform. During the real-time sampling process, based on the initial power waveform, feedback control can also be performed, and the ADC driver clock generator continues to perform synchronous sampling.

[0051] In one implementation, the initial power waveform output by the terminal layer node integrates the energy flow and the information flow, and the information flow is the multi-dimensional time-frequency domain characteristic quantity of the energy flow reflecting the system operation state. In some implementations, the "energy-information" dual-stream coupling can be realized through multi-dimensional waveform feature extraction and information fusion technology. Multi-dimensional waveform feature extraction can capture the detailed features of the waveform, establish a mapping relationship with the system operation state, and through analysis after the coupling of the energy flow and the information flow, it can reflect the overall performance of the system.

[0052] Combined with the above Figure 2, in a specific embodiment, when the master station layer node is deployed as a server, the hardware configuration can be a dual-active server, and the time synchronization accuracy is ≤ ±100 ns. When the edge layer is deployed in a substation, the edge layer node can be an edge computing gateway, whose core functions include transient event detection, and the communication interfaces include 4 optical fiber ports. When the edge layer is deployed in a distribution transformer area, the edge layer node can be an IFU (Intelligent Fusion Unit), whose core functions include harmonic responsibility division, and the communication interfaces include an HPLC + 5G module. When the terminal layer is deployed in a substation, the terminal layer node is the substation terminal, including a bus monitoring terminal and a feeder monitoring terminal, the sampling rate can be 256 kS / s, and the synchronization method can be IRIG-B code + optical fiber B code. When the terminal layer is deployed in a distribution transformer area, the terminal layer node is the distribution transformer area terminal, including a user outgoing line terminal and a distributed power source terminal, the sampling rate can be 64 kS / s, and the carrier communication can follow the Q / GDW11627-2016 standard.

[0053] The time monitoring system proposed in the embodiment of this application is multi-level, two-way feedback, and has fault tolerance capabilities, realizing high-precision and high-reliability time alignment from the master station to the terminal.

[0054] First, cross-layer synchronization logic can be realized: 1. Top-down calibration: Master station layer -> Edge layer: The master station layer node provides a ns-level reference clock through GNSS + atomic clock, and the edge node receives and synchronizes to this reference.

[0055] Edge layer -> Terminal layer: The edge node further distributes the time signal to the terminal device to achieve μs-level alignment, and the terminal layer hardware self-holds.

[0056] 2. Bottom-up feedback: Terminal layer feedback: Each terminal reports the health status of its local clock (such as crystal oscillator drift, error statistics, etc.).

[0057] Edge layer response: Dynamically adjust the time synchronization window and calibration strategy according to the terminal feedback.

[0058] Master station layer optimization: The master station layer comprehensively considers the feedback information of the whole network, optimizes the timing strategy, and improves the overall synchronization performance.

[0059] Secondly, a fault degradation mode can be provided: 1. Master station failure: When the master station timing source fails, the edge node automatically switches to a local high-stability atomic clock (such as a rubidium clock) for timekeeping to maintain the operation of the system.

[0060] 2. Communication interruption: If the communication link between the edge layer and the terminal is interrupted, the terminal enters the short-term autonomous mode and continues to work for a period of time relying on its local hardware clock to ensure that the sampling is not offset.

[0061] Finally, different-level clock mechanisms are provided: 1. Terminal layer (μs-level hardware synchronization) Clock drive: The local high-stability crystal oscillator drives the hardware timer to directly control the ADC sampling pulse.

[0062] Time marking: The FPGA is used to implement the nanosecond-level time stamp to accurately lock each sampling moment.

[0063] Power-off holding ability: After losing the external clock input, it can still maintain the self-synchronization ability with μs-level accuracy within a few minutes.

[0064] 2. Edge layer (sub-ms-level collaborative synchronization): Clock source: Based on the PTP timing signal sent by the master station (transmitted by wireless or optical fiber).

[0065] Synchronization mechanism: The "sliding time window + confidence interval verification" method is used for multi-node data alignment; dynamically identify and eliminate abnormal time points to ensure data consistency among multi-nodes.

[0066] 3. Master station layer (ns-level global timing): Clock source configuration: Dual-redundant atomic clocks (cesium clock + rubidium clock) are used as the core reference; the synchronization combines the GNSS satellite signal to tame the clock to improve the long-term stability and reliability.

[0067] Timing architecture: Adopt a hierarchical timing system to support the efficient time synchronization management of large-scale systems.

[0068] In a possible implementation, the edge layer node performs cross-level clock synchronization on the received initial power waveform based on the reference clock. When obtaining the synchronized power waveform, the reference clock signal provided by the master station layer can be used as a parameter to adjust its own internal clock to obtain the synchronized local clock; using the synchronized local clock, the edge layer node realigns the received initial power waveform according to the accurate time stamp to eliminate the error caused by the acquisition time difference. The "sliding time window + confidence interval verification" technology can also be used to identify and correct the data inconsistency among multi-nodes.

[0069] In a possible implementation, when the master station layer node performs synchronous analysis on the synchronous power waveform based on the reference clock according to the set time synchronization accuracy and obtains the synchronous monitoring result of the power waveform, the master station layer usually has the highest-level reference clock source, which can provide global timing services and can fine-tune the data of the edge layer nodes according to this clock to meet higher time synchronization accuracy requirements. In addition, the master station layer node can execute specific synchronous analysis algorithms, such as harmonic analysis, spectrum analysis, etc., according to the preset time synchronization accuracy standard, evaluate the quality of the power waveform, and detect abnormal conditions such as harmonic distortion and frequency offset. According to the analysis results, the master station layer node can also generate a detailed synchronous monitoring report of the power waveform, including but not limited to key indicators such as voltage and current values, power factors, and harmonic components, providing a scientific basis for power grid operation status monitoring and fault diagnosis.

[0070] This hierarchical architecture not only improves the overall synchronization accuracy of the system but also enhances the ability to cope with local failures. When a problem occurs at a certain level, the lower level can temporarily maintain the basic functions until the problem is solved.

[0071] Embodiment 2: Based on the same inventive concept, a wide-area power disturbance and fluctuation synchronous monitoring method provided by the present invention has a process schematic diagram as Figure 8 shown, including: Step 801: Perform multi-channel synchronous sampling based on the reference clock to obtain multiple sampling results; Step 802: Perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; Step 803: Perform correction filtering and delay compensation on the multiple error feedback sampling results, and upload the initial power waveform to the edge layer node for the edge layer node to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain the synchronous power waveform, and for the master station layer node to perform synchronous analysis on the synchronous power waveform according to the set time synchronization accuracy based on the reference clock to obtain the synchronous monitoring result of the power waveform.

[0072] Optionally, the performing multi-channel synchronous sampling based on the reference clock to obtain multiple sampling results includes: Obtain the reference clock provided by the GPS / PTP clock source, and use the DPLL digital phase-locked loop to lock the local clock with the reference clock to obtain a clock signal; Use a calibrated clock distributor to adjust the clock signal to obtain a unified time reference; Perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0073] Optionally, the cross - calibration and phase error detection of the multiple sampling results to obtain multiple error feedback sampling results include: Calculating the correlation between the multiple sampling results using a cross - correlator; Based on the correlation between the multiple sampling results, using a phase error detection unit to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

[0074] Optionally, the correction filtering and delay compensation of the multiple error feedback sampling results to obtain an initial power waveform include: Reading the filter coefficients corresponding to the multiple error feedback sampling results from a coefficient memory; Using a shift register chain to transfer the multiple error feedback sampling results to a MAC operation unit array in a set order; Based on the filter coefficients, using the MAC operation unit array to perform filtering to obtain a corrected filtering result; performing delay compensation on the corrected filtering result to obtain an initial power waveform.

[0075] Optionally, the delay compensation of the corrected filtering result to obtain an initial power waveform includes: Performing error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, adjusting the delay line to perform delay compensation on the corrected filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and taking the corrected filtering result after delay compensation at this time as the initial power waveform.

[0076] Optionally, the adjustment of the delay line includes: Based on a proportional - integral algorithm, adjusting the delay amount of an initial delay value to generate a new delay value, and updating the new delay value to a delay register to achieve dynamic calibration of the delay line.

[0077] Optionally, the edge - layer nodes are configured in a substation and are interconnected with the master - station layer nodes through a 5G network, and the terminal - layer nodes in the substation are interconnected with the edge - layer nodes through optical fibers and network cables; and / or The edge - layer nodes are configured in a distribution area and are interconnected with the master - station layer nodes through optical fibers, and the terminal - layer nodes in the distribution area are interconnected with the edge - layer nodes through power - line carrier PLC and optical fibers.

[0078] Optionally, the initial power waveform is fused with an energy flow and an information flow, and the information flow is a multi - dimensional time - frequency domain characteristic quantity of the energy flow reflecting the system operation state.

[0079] Embodiment 3: Based on the same inventive concept, the present invention also provides a wide-area power disturbance and fluctuation synchronous monitoring system, as Figure 9 shown, including: A multi-channel synchronous sampling module, configured to perform multi-channel synchronous sampling based on a reference clock to obtain a plurality of sampling results; An error feedback module, configured to perform cross-calibration and phase error detection on the plurality of sampling results to obtain a plurality of error feedback sampling results; A power waveform generation module, configured to perform correction filtering and delay compensation on the plurality of error feedback sampling results to obtain an initial power waveform and upload it to an edge layer node, so that the edge layer node performs cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronous power waveform, and the master station layer node performs synchronous analysis on the synchronous power waveform according to a set time synchronization accuracy based on the reference clock to obtain a synchronous monitoring result of the power waveform.

[0080] Optionally, the multi-channel synchronous sampling module includes: A clock locking unit, configured to obtain a reference clock provided by a GPS / PTP clock source, and lock a local clock with the reference clock by using a DPLL digital phase-locked loop to obtain a clock signal; A clock synchronization unit, configured to adjust the clock signal by using a calibrated clock distributor to obtain a unified time reference; A multi-channel sampling unit, configured to perform multi-channel synchronous sampling under the unified time reference to obtain a plurality of sampling results.

[0081] Optionally, the error feedback module includes: A cross-correlation calculation unit, configured to calculate the correlation between the plurality of sampling results by using a cross-correlator; An error feedback unit, configured to analyze the phase deviation between different channels by using a phase error detection unit based on the correlation between the plurality of sampling results to obtain a plurality of error feedback sampling results.

[0082] Optionally, the power waveform generation module includes: A coefficient reading unit, configured to read filter coefficients corresponding to the plurality of error feedback sampling results in a coefficient memory; An error transfer unit, configured to transfer the plurality of error feedback sampling results to a MAC operation unit array in a set order by using a shift register chain; A filtering and compensation unit, configured to perform filtering based on the filter coefficients by using the MAC operation unit array to obtain a corrected filtering result; perform delay compensation on the corrected filtering result to obtain an initial power waveform.

[0083] Optionally, the filtering and compensation unit is specifically configured to: Calculate the error based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, adjust the delay line to perform delay compensation on the corrected filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and use the corrected filtering result after delay compensation at this time as the initial power waveform.

[0084] Optionally, the filtering compensation unit is specifically configured to: Adjust the delay amount of the initial delay value based on the proportional integral algorithm to generate a new delay value, and update the new delay value to the delay register to achieve dynamic calibration of the delay line.

[0085] Optionally, the edge layer node is configured in a substation and is interconnected with the master station layer node through a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer node through optical fibers and network cables; and / or The edge layer node is configured in a distribution area and is interconnected with the master station layer node through an optical fiber, and the terminal layer nodes in the distribution area are interconnected with the edge layer node through power line carrier PLC and optical fibers.

[0086] Optionally, the initial power waveform is fused with an energy flow and an information flow, and the information flow is a multi-dimensional time-frequency domain feature quantity of the energy flow reflecting the system operation state.

[0087] Embodiment 4: As Figure 10 shown, the present invention further provides an electronic device, which may be a computer device, a single-chip microcomputer device, a smart mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, the processor, and the transceiver component are connected through a bus; the memory can be used to store an execution program, and an exemplary execution program may include instructions; the processor is used to execute the instructions stored in the memory. The memory can also be used to store data, and this data can be called and / or modified when the instructions are executed.

[0088] The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of a wide-area power disturbance and fluctuation synchronous monitoring method in the above embodiments.

[0089] Embodiment 5: Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device-readable storage medium (Memory). The electronic device-readable storage medium is a memory device in the electronic device, used to store programs and data. It can be understood that the storage medium here can include both the built-in storage medium in the electronic device, and of course, can also include the extended storage medium supported by the electronic device. The storage medium provides a storage space, and this storage space stores the operating system of the terminal. And, in this storage space, there are also stored one or more instructions suitable for being loaded and executed by the processor. These instructions can be one or more execution programs (including program codes). It should be noted that the storage medium here can be a high-speed RAM memory, or a non-volatile memory, such as at least one disk memory. By the processor loading and executing one or more instructions stored in the storage medium, the steps of a wide-area power disturbance and fluctuation synchronous monitoring method in the above embodiments can be implemented.

[0090] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0091] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce a means for implementing the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more blocks.

[0092] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction means that implements the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more blocks.

[0093] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more blocks.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the scope of its protection. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that after reading the present invention, various changes, modifications, or equivalent replacements can still be made to the specific implementation manners of the invention, but these changes, modifications, or equivalent replacements are all within the scope of the protection of the claims pending for the invention.

Claims

1. A wide-area power waveform synchronous monitoring system, characterized in that, It includes a master station layer node, an edge layer node, and multiple terminal layer nodes that communicate with each other. Each of the terminal layer nodes is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results. Cross calibration and phase error detection are performed on the multiple sampling results to obtain multiple error feedback sampling results. Correction filtering and delay compensation are performed on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node. The edge layer node is used to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform and upload it to the master station layer node. The master station layer node is used to perform synchronous analysis on the synchronized power waveform based on the reference clock according to the set time synchronization accuracy to obtain a synchronous monitoring result of the power waveform.

2. The system according to claim 1, wherein, Specifically, the terminal layer node is used to obtain a reference clock provided by a Global Positioning System (GPS) / Precision Time Protocol (PTP) clock source, and use a Digital Phase Locked Loop (DPLL) to lock the local clock with the reference clock to obtain a clock signal. The clock signal is adjusted by a calibration clock distributor to obtain a unified time reference; multi-channel synchronous sampling is performed under the unified time reference to obtain multiple sampling results.

3. The system according to claim 1, wherein Specifically, the terminal layer node is used to calculate the correlation between the multiple sampling results by using a cross-correlator; based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

4. The system according to claim 1, wherein Specifically, the terminal layer node is used to read filter coefficients corresponding to the multiple error feedback sampling results from a coefficient memory; a shift register chain is used to transfer the multiple error feedback sampling results to a multiplier-accumulator (MAC) operation unit array in a set order. Based on the filter coefficients, filtering is performed by using the MAC operation unit array to obtain a correction filtering result; delay compensation is performed on the correction filtering result to obtain an initial power waveform.

5. The system according to claim 4, wherein Specifically, the terminal layer node is used to perform error calculation based on the multiple sampling results to obtain an error calculation result; if the error calculation result is greater than a preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

6. The system according to claim 5, characterized in that, Specifically, the terminal layer node is used to adjust the delay amount of the initial delay value based on a proportional-integral algorithm to generate a new delay value, and update the new delay value to a delay register to realize dynamic calibration of the delay line.

7. The system according to claim 1, wherein The edge layer node is configured in a substation and is interconnected with the master station layer node through a 5G network. The terminal layer nodes in the substation are interconnected with the edge layer node through optical fibers and network cables; and / or The edge layer node is configured in a distribution substation area and is interconnected with the master station layer node through an optical fiber. The terminal layer nodes in the distribution substation area are interconnected with the edge layer node through Power Line Carrier (PLC) and optical fibers.

8. The system according to claim 1, characterized in that The initial power waveform is fused with energy flow and information flow, and the information flow is the multi-dimensional time-frequency domain characteristic quantity of the energy flow reflecting the system operation state.

9. A wide-area power waveform synchronous monitoring method, characterized in that, It includes: Performing multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; Performing cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; Performing calibration filtering and delay compensation on the multiple error feedback sampling results, and uploading the initial power waveform to the edge layer node, so that the edge layer node performs cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master station layer node performs synchronous analysis on the synchronized power waveform based on the reference clock according to the set time synchronization accuracy to obtain a synchronous monitoring result of the power waveform.

10. The method according to claim 9, wherein The performing multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results includes: Obtaining a reference clock provided by a Global Positioning System (GPS) / Precision Time Protocol (PTP) clock source, and locking the local clock to the reference clock by using a Digital Phase Locked Loop (DPLL) to obtain a clock signal; Adjusting the clock signal by using a calibrated clock distributor to obtain a unified time reference; Performing multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

11. The method according to claim 9, wherein The performing cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results includes: Calculating the correlation between the multiple sampling results by using a cross-correlator; Based on the correlation between the multiple sampling results, using a phase error detection unit to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

12. The method according to claim 9, wherein The performing calibration filtering and delay compensation on the multiple error feedback sampling results to obtain the initial power waveform includes: Reading the filter coefficients corresponding to the multiple error feedback sampling results in a coefficient memory; Using a shift register chain to transfer the multiple error feedback sampling results to a MAC operation unit array in a set order; Based on the filter coefficients, performing filtering by using the MAC operation unit array to obtain a calibration filtering result; performing delay compensation on the calibration filtering result to obtain the initial power waveform.

13. The method according to claim 12, characterized in that, The performing delay compensation on the calibration filtering result to obtain the initial power waveform includes: Performing error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, adjusting a delay line to perform delay compensation on the calibration filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and taking the calibration filtering result after delay compensation at this time as the initial power waveform.

14. The method according to claim 13, wherein The adjusting the delay line includes: Adjusting the delay amount of an initial delay value based on a proportional-integral algorithm to generate a new delay value, and updating the new delay value to a delay register to realize dynamic calibration of the delay line.

15. The method according to claim 9, wherein The edge layer nodes are configured in a substation and are interconnected with the master station layer nodes through a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; and / or The edge layer nodes are configured in the distribution transformer area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution transformer area are interconnected with the edge layer nodes through power line carrier PLC and optical fibers.

16. The method according to claim 9, wherein The initial power waveform is fused with energy flow and information flow, and the information flow is the multi-dimensional time-frequency domain characteristic quantity of the energy flow reflecting the system operation state.

17. A wide-area power waveform synchronous monitoring system, characterized in that It includes: A multi-channel synchronous sampling module, which is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; An error feedback module, which is used to perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; A power waveform generation module, which is used to perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node. The edge layer node is used to perform cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master station layer node is used to perform synchronous analysis on the synchronized power waveform based on the reference clock according to the set time synchronization accuracy to obtain a synchronous monitoring result of the power waveform.

18. The system according to claim 17, wherein The multi-channel synchronous sampling module includes: A clock locking unit, which is used to obtain a reference clock provided by a GPS / PTP clock source and lock the local clock with the reference clock using a DPLL digital phase-locked loop to obtain a clock signal; A clock synchronization unit, which is used to adjust the clock signal using a calibrated clock distributor to obtain a unified time reference; A multi-channel sampling unit, which is used to perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

19. The system according to claim 17, wherein The error feedback module includes: A cross-correlation calculation unit, which is used to calculate the correlation between the multiple sampling results using a cross-correlator; An error feedback unit, which is used to analyze the phase deviation between different channels using a phase error detection unit based on the correlation between the multiple sampling results to obtain multiple error feedback sampling results.

20. The system according to claim 17, wherein The power waveform generation module includes: A coefficient reading unit, which is used to read the filter coefficients corresponding to the multiple error feedback sampling results in a coefficient memory; An error transfer unit, which is used to transfer the multiple error feedback sampling results to a MAC operation unit array in a set order using a shift register chain; A filtering and compensation unit, which is used to perform filtering on the basis of the filter coefficients using the MAC operation unit array to obtain a corrected filtering result; and perform delay compensation on the corrected filtering result to obtain an initial power waveform.

21. The system according to claim 20, wherein The filtering and compensation unit is specifically used for: Performing error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than a preset error threshold, adjusting the delay line to perform delay compensation on the corrected filtering result until the error calculation result after delay compensation is not greater than the preset error threshold, and taking the corrected filtering result after delay compensation at this time as the initial power waveform.

22. The system according to claim 20, wherein The filtering and compensation unit is specifically used for: Adjusting the delay amount of the initial delay value based on a proportional-integral algorithm to generate a new delay value, and updating the new delay value to a delay register to realize dynamic calibration of the delay line.

23. The system according to claim 17, wherein The edge layer nodes are configured in a substation and interconnected with the master station layer nodes through a 5G network. The terminal layer nodes in the substation are interconnected with the edge layer nodes through optical fibers and network cables; and / or The edge layer nodes are configured in a distribution transformer area and interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution transformer area are interconnected with the edge layer nodes through power line carrier PLC and optical fibers.

24. The system according to claim 17, wherein, The initial power waveform is fused with an energy flow and an information flow, and the information flow is a multi-dimensional time-frequency domain feature quantity of the energy flow reflecting the system operation state.

25. An electronic device, characterized in that, Comprising: At least one processor and a memory; The memory and the processor are connected by a bus; The memory is used for storing one or more programs; When the one or more programs are executed by the at least one processor, the wide-area power waveform synchronous monitoring method according to any one of claims 9 to 16 is implemented.

26. A readable storage medium, characterized in that, There is an execution program stored thereon, and when the execution program is executed, the wide-area power waveform synchronous monitoring method according to any one of claims 9 to 16 is implemented.

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