Signal switching circuit and display panel

Abstract

A signal switching circuit and a display panel, the signal switching circuit comprises a time sequence control module, a level conversion module, a pulse generation module and a signal switching module, the level conversion module is electrically connected with the time sequence control module and used for being electrically connected with a gate drive circuit, and the pulse generation module is electrically connected with the level conversion module and used for being electrically connected with the gate drive circuit. The signal switching module is electrically connected with the time sequence control module, the level conversion module and the pulse generation module, and before the display panel is powered on and initialization of the time sequence control module is completed, the pulse generation module is used for outputting square-wave pulses to the gate drive circuit through the signal switching module and the level conversion module; the timing control module is used for outputting a display timing signal to the gate drive circuit through the signal switching module and the level conversion module to eliminate the residual voltage of the gate drive circuit, after the timing control module is initialized, the timing control module is used for outputting the display timing signal to the gate drive circuit through the signal switching module and the level conversion module, the denoising effect of the display panel is improved, and the production cost of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a signal switching circuit and a display panel. Background Art

[0002] In a gate driver circuit (Gate on Array, GOA) using oxide thin-film transistors (Oxide TFTs), since the leakage current of the oxide thin-film transistors is small, there is residual charge in the gate driver circuit when the previous shutdown occurs. Therefore, a square wave pulse is output between the display screens of the display through a level shifter (Level Shifter, L / S) to perform noise removal processing on the gate driver circuit, avoiding abnormal images when powering on. Since the level shifter does not have the ability to generate pulses spontaneously, in the prior art, a timing controller (Timing Controller, TCON), a microcontroller unit (Microcontroller Unit, MCU), or a dedicated initialization chip is usually used to control the level shifter to output a square wave pulse, but there are problems of poor noise removal effect and high production cost. Summary of the Invention

[0003] The objective of this application is to provide a signal switching circuit and a display panel to solve the problems of poor noise removal effect and high production cost.

[0004] To achieve the objective of this application, the following technical solutions are provided: In a first aspect, the present invention provides a signal switching circuit for a display panel, where the display panel includes a gate driver circuit, and the signal switching circuit includes: a timing control module; a level conversion module electrically connected to the timing control module and used to be electrically connected to the gate driver circuit; a pulse generation module electrically connected to the level conversion module; and a signal switching module electrically connected to the timing control module, the level conversion module, and the pulse generation module; wherein, before the display panel is powered on and the initialization of the timing control module is completed, the pulse generation module is used to output a square wave pulse to the gate driver circuit through the signal switching module and the level conversion module to eliminate the residual voltage of the gate driver circuit, and after the initialization of the timing control module is completed, the timing control module is used to output a display timing signal to the gate driver circuit through the signal switching module and the level conversion module.

[0005] In one implementation, the pulse generation module includes a sampling unit, a reference unit, a comparison unit, and an output unit. The sampling unit and the reference unit are both electrically connected to the comparison unit. The comparison unit is electrically connected to the output unit. The output unit is electrically connected to the signal switching module. The sampling unit is configured to receive an enabling voltage. Among them, the sampling unit is configured to output a sampling voltage to the comparison unit according to the enabling voltage. The reference unit is configured to output a first reference voltage and a second reference voltage to the comparison unit. The comparison unit is configured to output a comparison voltage to the output unit according to the sampling voltage, the first reference voltage, and the second reference voltage. The output unit is configured to output the square-wave pulse to the gate drive circuit through the signal switching module and the level conversion module according to the comparison voltage.

[0006] In one implementation, the sampling unit includes a first input terminal, a first resistor, and a second resistor connected in series in sequence. The first input terminal is configured to receive an enabling voltage. The first resistor and the second resistor are connected to a first node. The second resistor is connected in series between the first node and the ground terminal. The first node is electrically connected to the comparison unit.

[0007] In one implementation, the reference unit includes a first capacitor and a third resistor, a fourth resistor, a fifth resistor, and a second input terminal connected in series in sequence. The second input terminal is configured to receive a logic voltage. The first capacitor is connected in parallel with the fourth resistor. The third resistor and the fourth resistor are connected to a second node. The fourth resistor and the fifth resistor are connected to a third node. The third resistor is connected in series between the third node and the ground terminal. Both the second node and the third node are electrically connected to the comparison unit. The second node is configured to output the first reference voltage. The third node is configured to output the second reference voltage.

[0008] In one implementation, the comparison unit includes a first comparator and a second comparator. The positive power supply terminals of the first comparator and the second comparator are both configured to receive a logic voltage. The negative power supply terminals of the first comparator and the second comparator are both connected to the ground terminal. The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are both electrically connected to the first node. The inverting input terminal of the first comparator is electrically connected to the second node. The non-inverting input terminal of the second comparator is electrically connected to the third node. The output terminals of the first comparator and the second comparator are connected to a fourth node. The fourth node is electrically connected to the output unit.

[0009] In one embodiment, the output unit includes a first triode, a first transistor, a second transistor, a third input terminal, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The third input terminal is used to receive a logic voltage. The sixth resistor is connected in series between the fourth node and the base of the first triode. The seventh resistor is connected in series between the emitter of the first triode and the ground terminal. The eighth resistor is connected in series between the collector of the first triode and the third input terminal. The collector of the first triode, the gate of the first transistor, and the gate of the second transistor are connected to a fifth node. The source of the first transistor is electrically connected to the third input terminal. The ninth resistor is connected in series between the source of the second transistor and the ground terminal. The drain of the first transistor and the drain of the second transistor are connected to a sixth node. The sixth node is electrically connected to the signal switching module.

[0010] In one embodiment, the signal switching module includes a driving unit and a switching unit. The driving unit is electrically connected to both the timing control module and the switching unit. The switching unit is electrically connected to the pulse generating module, the timing control module, and the level conversion module.

[0011] In one embodiment, the driving unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a second triode, and a fourth input terminal. The tenth resistor is connected in series between the base of the second triode and the timing control module. The eleventh resistor is connected in series between the fourth input terminal and the collector of the second triode. The twelfth resistor is connected in series between the emitter of the second triode and the ground terminal. The emitter of the second triode is electrically connected to the switching unit.

[0012] In one embodiment, the switching unit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a third transistor, and a fourth transistor. One end of the thirteenth resistor is electrically connected to the emitter of the second triode. The other end of the thirteenth resistor is connected to the fourteenth resistor and the fifteenth resistor at a seventh node. The fourteenth resistor is connected in series between the seventh node and the gate of the third transistor. The fifteenth resistor is connected in series between the gate of the fourth transistor. The sixteenth resistor is connected in series between the source of the third transistor and the pulse generating module. The source of the fourth transistor is electrically connected to the timing control module. The drains of the third transistor and the fourth transistor are both electrically connected to the level conversion module.

[0013] In a second aspect, the present invention further provides a display panel, including a gate driving circuit and the signal switching circuit according to any one of the embodiments in the first aspect. The gate driving circuit is electrically connected to the level conversion module.

[0014] By setting a pulse generation module and a signal switching module, the pulse module is electrically connected to both the level conversion module and the signal switching module, and the signal switching module is also electrically connected to the timing control module and the level conversion module. Before the display panel is powered on and the timing control module is initialized, the pulse generation module is used to output square wave pulses to the gate driver circuit through the signal switching module and the level conversion module to eliminate the residual voltage of the gate driver circuit. After the timing control module is initialized, the timing control module is used to output display timing signals to the gate driver circuit through the signal switching module and the level conversion module, so that the display panel can eliminate the residual voltage of the gate driver circuit between power-on and the completion of the initialization of the timing control module, and after the initialization of the timing control module is completed, it can normally output display timing signals to the level conversion module through the signal switching module, improving the noise reduction effect of the display panel and reducing the production cost of the display panel. Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 is a schematic diagram of a signal switching circuit of an embodiment; Figure 2 is a circuit diagram of a signal switching circuit of an embodiment; Figure 3 is a schematic diagram of a display panel of an embodiment.

[0017] Description of the Reference Numerals: 1000 - Display panel; 100 - Signal switching circuit, TCON - Timing control module, L / S - Level conversion module, 10 - Pulse generation module, 11 - Sampling unit, IN1 - First input terminal, R1 - First resistor, R2 - Second resistor, 12 - Reference unit, C1 - First capacitor, R3 - Third resistor, R4 - Fourth resistor, R5 - Fifth resistor, IN2 - Second input terminal, 13 - Comparison unit, U1 - First comparator, U2 - Second comparator, 14 - Output unit, K1 - First triode, M1 - First transistor, M2 - Second transistor, IN3 - Third input terminal, R6 - Sixth resistor, R7 - Seventh resistor, R8 - Eighth resistor, R9 - Ninth resistor, 20 - Signal switching module, 21 - Driving unit, R10 - Tenth resistor, R11 - Eleventh resistor, R12 - Twelfth resistor, K2 - Second triode, IN4 - Fourth input terminal, 22 - Switching unit, R13 - Thirteenth resistor, R14 - Fourteenth resistor, R15 - Fifteenth resistor, R16 - Sixteenth resistor, M3 - Third transistor, M4 - Fourth transistor, GND - Ground terminal; 200 - Gate driving circuit, GOA - Gate driving unit, P - Pixel unit, MB - Main board, SC - Data driver, AA - Display area, NA - Non - display area; PWM - Square wave pulse, TS - Display timing signal, SV - Sampling voltage, REF1 - First reference voltage, REF2 - Second reference voltage, VCMP - Comparison voltage, VDD - Logic voltage, VGH - Turn - on voltage, GPIO - Control signal, PSV - Power supply voltage, Q1 - First node, Q2 - Second node, Q3 - Third node, Q4 - Fourth node, Q5 - Fifth node, Q6 - Sixth node, Q7 - Seventh node. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0019] It should be noted that when a component is referred to as being "fixed to" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intermediate component at the same time.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in the specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items.

[0021] The following will describe in detail some embodiments of this application in conjunction with the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0022] Please refer to Figure 1 , the present invention provides a signal switching circuit 100 for a display panel 1000. The display panel 1000 includes a gate driving circuit 200. The signal switching circuit 100 includes a timing control module TCON, a level conversion module L / S, a pulse generating module 10, and a signal switching module 20. The level conversion module L / S is electrically connected to the timing control module TCON and is used to be electrically connected to the gate driving circuit 200. The pulse generating module 10 is electrically connected to the level conversion module L / S. The signal switching module 20 is electrically connected to the timing control module TCON, the level conversion module L / S, and the pulse generating module 10. Among them, before the display panel 1000 is powered on and the timing control module TCON is initialized, the pulse generating module 10 is used to output a square wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S to eliminate the residual voltage of the gate driving circuit 200. After the timing control module TCON is initialized, the timing control module TCON is used to output a display timing signal TS to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S.

[0023] Optionally, both the pulse generating module 10 and the signal switching module 20 can adopt discrete devices such as triodes, P-type MOSFETs, N-type MOSFETs, and RC delay circuits, so that after the display panel 1000 is powered on, the pulse generating module 10 and the signal switching module 20 can automatically generate a square wave pulse PWM without setting an additional control module or control chip, saving production costs and improving stability.

[0024] After the timing control module TCON is initialized, the timing control module TCON is used to sequentially output a display timing signal TS to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S, so that the gate driving circuit 200 outputs a scanning signal row by row to turn on the pixels row by row.

[0025] When the display panel 1000 is powered on, the oxide thin-film transistors in the gate driving circuit 200 have a small leakage current, and there is residual charge remaining on the display panel 1000 after a single power-off. When the display panel 1000 is powered on again, the residual charge will cause abnormal picture display. Therefore, a square-wave pulse PWM needs to be input to the gate driving circuit 200 to eliminate its residual charge.

[0026] In the solution of using a timing controller to cooperate with a level converter to output a square-wave pulse PWM, since the timing controller requires a long initialization time and cannot output a valid signal within a preset time, there is abnormal picture display after the display panel 1000 is powered on.

[0027] In the solution of using a micro-control unit or a dedicated initialization chip to cooperate with a level converter to output a square-wave pulse PWM, it outputs a square-wave pulse PWM after the display panel 1000 is powered on by programming a specific program to avoid abnormal picture display, but it increases the production cost, control complexity and power consumption.

[0028] The signal switching circuit 100 provided by the present application, by setting a pulse generating module 10 and a signal switching module 20, the pulse module is electrically connected to both the level conversion module L / S and the signal switching module 20, and the signal switching module 20 is also electrically connected to the timing control module TCON and the level conversion module L / S. Before the display panel 1000 is powered on and the initialization of the timing control module TCON is completed, the pulse generating module 10 is used to output a square-wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S to eliminate the residual voltage of the gate driving circuit 200. After the initialization of the timing control module TCON is completed, the timing control module TCON is used to output a display timing signal TS to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S, so that the display panel 1000 can eliminate the residual voltage of the gate driving circuit 200 after being powered on and before the initialization of the timing control module TCON is completed, and the timing control module TCON can normally output a display timing signal TS to the level conversion module L / S through the signal switching module 20 after the initialization is completed, improving the denoising effect of the display panel 1000 and reducing the production cost of the display panel 1000.

[0029] Please refer to Figure 1 and Figure 2, the pulse generation module 10 includes a sampling unit 11, a reference unit 12, a comparison unit 13 and an output unit 14. The sampling unit 11 and the reference unit 12 are both electrically connected to the comparison unit 13, the comparison unit 13 is electrically connected to the output unit 14, and the output unit 14 is electrically connected to the signal switching module 20. The sampling unit 11 is used to receive the turn-on voltage VGH. Among them, the sampling unit 11 is used to output a sampling voltage SV to the comparison unit 13 according to the turn-on voltage VGH. The reference unit 12 is used to output a first reference voltage REF1 and a second reference voltage REF2 to the comparison unit 13. The comparison unit 13 is used to output a comparison voltage VCMP to the output unit 14 according to the sampling voltage SV, the first reference voltage REF1 and the second reference voltage REF2. The output unit 14 is used to output a square wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S according to the comparison voltage VCMP.

[0030] Optionally, the reference unit 12 is used to input a logic voltage VDD. The reference unit 12 is used to output a first reference voltage REF1 and a second reference voltage REF2 to the comparison unit 13 according to the voltage of the logic voltage VDD. Exemplarily, the voltage value of the logic voltage VDD is 3.3V. Among them, the first reference voltage REF1 is used to control the rising edge position of the square wave pulse PWM, and the second reference voltage REF2 is used to control the falling edge position of the square wave pulse PWM. The width and duration of the square wave pulse PWM can be controlled by controlling the rising time of the first reference voltage REF1.

[0031] Before the display panel 1000 is powered on, the turn-on voltage VGH is 0V (volt). When the display panel 1000 is powered on, the turn-on voltage VGH gradually rises to a preset value. Exemplarily, the turn-on voltage VGH gradually rises to 25V. During the gradual rise of the turn-on voltage VGH, the sampling voltage SV output by the sampling unit 11 also gradually rises. When the sampling voltage SV rises to a preset value, the comparison unit 13 outputs a comparison voltage VCMP according to the sampling voltage SV, the first reference voltage REF1 and the second reference voltage REF2. Secondly, the output unit 14 outputs a square wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S according to the comparison voltage VCMP.

[0032] By setting the pulse generation module 10 to include a sampling unit 11, a reference unit 12, a comparison unit 13, and an output unit 14, the sampling unit 11 and the reference unit 12 are both electrically connected to the comparison unit 13, the comparison unit 13 is electrically connected to the output unit 14, and the output unit 14 is electrically connected to the signal switching module 20. The sampling unit 11 is configured to receive the turn-on voltage VGH. Among them, the sampling unit 11 is configured to output a sampling voltage SV to the comparison unit 13 according to the turn-on voltage VGH. The reference unit 12 is configured to output a first reference voltage REF1 and a second reference voltage REF2 to the comparison unit 13. The comparison unit 13 is configured to output a comparison voltage VCMP to the output unit 14 according to the sampling voltage SV, the first reference voltage REF1, and the second reference voltage REF2. The output unit 14 is configured to output a square-wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S according to the comparison voltage VCMP, so that a square-wave pulse PWM can be automatically generated when the display panel 1000 is powered on, thereby eliminating the residual voltage of the gate driving circuit 200, improving the denoising effect of the display panel 1000, and the structure of the pulse generation module 10 is simple, reducing the production cost of the display panel 1000.

[0033] Please refer to Figure 2 , the sampling unit 11 includes a first input terminal IN1, a first resistor R1, and a second resistor R2 connected in series in sequence. The first input terminal IN1 is configured to receive the turn-on voltage VGH. The first resistor R1 and the second resistor R2 are connected to a first node Q1. The second resistor R2 is connected in series between the first node Q1 and the ground terminal GND. The first node Q1 is electrically connected to the comparison unit 13.

[0034] Among them, since the turn-on voltage VGH is relatively large, in order to avoid large DC power consumption in the first resistor R1 and the second resistor R2, the value range of the resistance of the first resistor R1 and the second resistor R2 can be greater than 100 KΩ (kiloohm).

[0035] By setting the sampling unit 11 to include a first input terminal IN1, a first resistor R1, and a second resistor R2 connected in series in sequence, the first input terminal IN1 is configured to receive the turn-on voltage VGH, the first resistor R1 and the second resistor R2 are connected to a first node Q1, the second resistor R2 is connected in series between the first node Q1 and the ground terminal GND, and the first node Q1 is electrically connected to the comparison unit 13, so that the sampling unit 11 can convert the turn-on voltage VGH with a relatively large voltage value into a sampling voltage SV with a relatively small voltage value, so as to avoid the comparison module being broken down by a large voltage. At the same time, the structure of the sampling unit 11 is simple, with high stability and low production cost.

[0036] Please refer to Figure 2, the reference unit 12 includes a first capacitor C1, and a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a second input terminal IN2 connected in series in sequence. The second input terminal IN2 is used to receive a logic voltage VDD. The first capacitor C1 is connected in parallel with the fourth resistor R4. The third resistor R3 and the fourth resistor R4 are connected to a second node Q2. The fourth resistor R4 and the fifth resistor R5 are connected to a third node Q3. The third resistor R3 is connected in series between the third node Q3 and the ground terminal GND. Both the second node Q2 and the third node Q3 are electrically connected to the comparison unit 13. The second node Q2 is used to output a first reference voltage REF1, and the third node Q3 is used to output a second reference voltage REF2.

[0037] Among them, the voltage values of the first reference voltage REF1 and the second reference voltage REF2 can be adjusted by adjusting the resistance values of the third resistor R3, the fourth resistor R4, and the fifth resistor R5. Among them, the voltage of the first reference voltage REF1 determines the rising edge position of the square wave pulse PWM, and the voltage value of the second reference voltage REF2 determines the falling edge position of the square wave pulse PWM. Exemplarily, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are all digital potentiometers to facilitate adjusting the resistance values of the third resistor R3, the fourth resistor R4, and the fifth resistor R5.

[0038] Optionally, since the first capacitor C1 is connected in parallel with the fourth resistor R4, the reference unit 12 can control the rising time of the first reference voltage REF1 through the first capacitor C1 with different capacitance values, that is, control the position of the rising edge of the square wave pulse PWM or the width of the square wave pulse PWM. Among them, when the second reference voltage REF2 is constant, when the capacitance value of the first capacitor C1 decreases, the rising time of the first reference voltage REF1 advances, and the width of the square wave pulse PWM increases. When the capacitance value of the first capacitor C1 increases, the rising time of the first reference voltage REF1 delays, and the width of the square wave pulse PWM decreases.

[0039] By setting the reference unit 12 to include a first capacitor C1 and a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a second input terminal IN2 connected in series in sequence, the second input terminal IN2 is used to receive a logic voltage VDD, the first capacitor C1 is connected in parallel with the fourth resistor R4, the third resistor R3 and the fourth resistor R4 are connected to a second node Q2, the fourth resistor R4 and the fifth resistor R5 are connected to a third node Q3, the third resistor R3 is connected in series between the third node Q3 and the ground terminal GND, both the second node Q2 and the third node Q3 are electrically connected to the comparison unit 13, the second node Q2 is used to output a first reference voltage REF1, and the third node Q3 is used to output a second reference voltage REF2, so that the reference power supply can output the first reference voltage REF1 and the second reference voltage REF2 required by the display panel 1000 through the third resistor R3, the fourth resistor R4, the fifth resistor R5 with different resistance values and the first capacitor C1 with different capacitance values, which improves the flexibility and device adaptability of the pulse generation module 10. At the same time, the structure of the reference unit 12 is simple and the production cost is low.

[0040] Please refer to Figure 2 , the comparison unit 13 includes a first comparator U1 and a second comparator U2. The positive power supply terminals of the first comparator U1 and the second comparator U2 are both used to receive the logic voltage VDD. The negative power supply terminals of the first comparator U1 and the second comparator U2 are both connected to the ground terminal GND. The non-inverting input terminals of the first comparator U1 and the second comparator U2 are both electrically connected to a first node Q1. The inverting input terminal of the first comparator U1 is electrically connected to the second node Q2. The non-inverting input terminal of the second comparator U2 is electrically connected to the third node Q3. The output terminals of the first comparator U1 and the second comparator U2 are connected to a fourth node Q4, and the fourth node Q4 is electrically connected to the output unit 14.

[0041] Optionally, to avoid voltage fluctuations generated during the rising process of the aforementioned turn-on voltage VGH, both the first comparator U1 and the second comparator U2 can be Schmitt triggers with a hysteresis function.

[0042] Specifically, when the sampling voltage SV is less than the first reference voltage REF1, the output of the first comparator U1 is at a low level, that is, the first comparator U1 outputs the voltage of its negative power supply terminal. Since the negative power supply terminal of the first comparator U1 is connected to the ground terminal GND, the voltage value output by the first comparator U1 is 0V. When the sampling voltage SV is greater than the first reference voltage REF1, the output of the first comparator U1 is at a high level, that is, the first comparator U1 outputs the voltage of its positive power supply terminal. Since the voltage input to the positive power supply terminal of the first comparator U1 is the logic voltage VDD, the first comparator U1 outputs the logic voltage VDD.

[0043] When the sampling voltage SV is less than the second reference voltage REF2, the output of the second comparator U2 is at a high level, that is, the second comparator U2 outputs the voltage of its positive power supply terminal. Since the voltage input to the positive power supply terminal of the second comparator U2 is the logic voltage VDD, the second comparator U2 outputs the logic voltage VDD. When the sampling voltage SV is greater than the second reference voltage REF2, the output of the second comparator U2 is at a low level, that is, the second comparator U2 outputs the voltage of its negative power supply terminal. Since the negative power supply terminal of the second comparator U2 is connected to the ground terminal GND, the voltage value output by the second comparator U2 is 0V.

[0044] The fourth node Q4 receives the voltages from the first comparator U1 and the second comparator U2 and has a comparison voltage VCMP that switches between the logic voltage VDD and 0V. Therefore, when the voltage value of the turn-on voltage VGH rises to a preset value, that is, when the voltage value of the sampling voltage SV rises to a preset value, the comparison unit 13 can output an effective comparison voltage VCMP to the output unit 14. Furthermore, the output module outputs a square-wave pulse PWM to the gate driving circuit 200 through the signal switching module 20 and the level conversion module L / S, enabling the display panel 1000 to automatically generate a square-wave pulse PWM when powering on to eliminate the residual voltage of the gate driving circuit 200, improving the denoising effect of the display panel 1000. Moreover, the structure of the comparison unit 13 is simple, with strong stability and low production cost.

[0045] Please refer to Figure 2 The output unit 14 includes a first triode K1, a first transistor M1, a second transistor M2, a third input terminal IN3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The third input terminal IN3 is used to receive the logic voltage VDD. The sixth resistor R6 is connected in series between the fourth node Q4 and the base of the first triode K1. The seventh resistor R7 is connected in series between the emitter of the first triode K1 and the ground terminal GND. The eighth resistor R8 is connected in series between the collector of the first triode K1 and the third input terminal IN3. The collector of the first triode K1, the gate of the first transistor M1, and the gate of the second transistor M2 are connected to the fifth node Q5. The source of the first transistor M1 is electrically connected to the third input terminal IN3. The ninth resistor R9 is connected in series between the source of the second transistor M2 and the ground terminal GND. The drain of the first transistor M1 and the drain of the second transistor M2 are connected to the sixth node Q6, and the sixth node Q6 is electrically connected to the signal switching module 20.

[0046] Among them, the first transistor M1 is a P-type MOS transistor, and the second transistor M2 is an N-type MOS transistor. When the comparison voltage VCMP is at a low level, that is, the voltage of the fourth node Q4 is 0V, the first triode K1 is not conducting, that is, there is an open circuit between the emitter and the collector of the first triode K1. At this time, the voltage of the fifth node Q5 is the logic voltage VDD, which is a high level. The first transistor M1 is turned off, and the second transistor M2 is turned on. The output voltage value of the sixth node Q6 is a low level of 0V, corresponding to the low level of the square wave pulse PWM.

[0047] When the comparison voltage VCMP is at a high level, that is, the voltage of the fourth node Q4 is the logic voltage VDD, the first triode K1 is conducting, that is, there is a conduction between the emitter and the collector of the first triode K1. At this time, the voltage of the fifth node Q5 is the voltage of the ground terminal GND, which is a low level. The first transistor M1 is turned on, and the second transistor M2 is turned off. The output voltage value of the sixth node Q6 is a high level of the logic voltage VDD, corresponding to the high level of the square wave pulse PWM.

[0048] Therefore, the output unit 14 can generate the square wave pulse PWM according to the change of the comparison voltage VCMP and through the level conversion module L / S, so that the square wave pulse PWM can be automatically generated when the display panel 1000 is powered on, to eliminate the residual voltage of the gate driving circuit 200, improving the denoising effect of the display panel 1000. Moreover, the structure of the output unit 14 is simple, with strong stability and low production cost.

[0049] Please refer to Figure 1 , the signal switching module 20 includes a driving unit 21 and a switching unit 22. The driving unit 21 is electrically connected to both the timing control module TCON and the switching unit 22. The switching unit 22 is electrically connected to the pulse generating module 10, the timing control module TCON, and the level conversion module L / S.

[0050] Among them, the timing control module TCON is used to output a control signal GPIO to the driving unit 21. Before the initialization of the timing control module TCON is completed, the control signal GPIO is at a low level. At this time, the pulse generating module 10 is electrically connected to the level conversion module L / S through the switching unit 22, and there is an open circuit between the timing control module TCON and the level conversion module L / S. After the initialization of the timing control module TCON is completed, the control signal GPIO is at a high level. At this time, the timing control module TCON is electrically connected to the level conversion module L / S through the switching unit 22, and there is an open circuit between the pulse generating module 10 and the level conversion module L / S.

[0051] By setting the signal switching module 20 to include a driving unit 21 and a switching unit 22, the driving unit 21 is electrically connected to both the timing control module TCON and the switching unit 22, and the switching unit 22 is electrically connected to the pulse generation module 10, the timing control module TCON, and the level conversion module L / S, so that the display panel 1000 can eliminate the residual voltage of the gate driving circuit 200 after power-on and before the initialization of the timing control module TCON is completed. And when the initialization of the timing control module TCON is completed, the display timing signal TS can be automatically output to the level conversion module L / S through the signal switching module 20 normally, without setting an additional control module or control chip, saving production costs and improving stability at the same time.

[0052] Please refer to Figure 2 , the driving unit 21 includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a second triode K2, and a fourth input terminal IN4. The tenth resistor R10 is connected in series between the base of the second triode K2 and the timing control module TCON. The eleventh resistor R11 is connected in series between the fourth input terminal IN4 and the collector of the second triode K2. The twelfth resistor R12 is connected in series between the emitter of the second triode K2 and the ground terminal GND. The emitter of the second triode K2 is electrically connected to the switching unit 22. Optionally, the fourth input terminal IN4 is used to input a power supply voltage PSV with a high level. Exemplarily, the voltage of the power supply voltage PSV is 12V.

[0053] The timing control module TCON is used to input a control signal GPIO to the base of the second triode K2 through the tenth resistor R10. When the control signal GPIO is at a low level, the second triode K2 is turned off, and the voltage at the emitter of the second triode K2 is the voltage of the ground terminal GND, which is 0V. At this time, the switching unit 22 controls the pulse generation module 10 to be electrically connected to the level conversion module L / S. When the control signal GPIO is at a high level, the second triode K2 is turned on, and the voltage at the emitter of the second triode K2 is the voltage of the fourth input terminal IN4, that is, the power supply voltage PSV. At this time, the switching unit 22 controls the timing control module TCON to be electrically connected to the level conversion module L / S.

[0054] By setting the driving unit 21 to include a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a second triode K2, and a fourth input terminal IN4, the tenth resistor R10 is connected in series between the base of the second triode K2 and the timing control module TCON, the eleventh resistor R11 is connected in series between the fourth input terminal IN4 and the collector of the second triode K2, the twelfth resistor R12 is connected in series between the emitter of the second triode K2 and the ground terminal GND, and the emitter of the second triode K2 is electrically connected to the switching unit 22, so that the driving unit 21 can drive the switching unit 22 according to whether the timing control module TCON has completed initialization, enabling the level conversion module L / S to automatically switch between being electrically connected to the pulse generating module 10 and being electrically connected to the timing control module TCON.

[0055] Please refer to Figure 2 , the switching unit 22 includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third transistor M3, and a fourth transistor M4. One end of the thirteenth resistor R13 is electrically connected to the emitter of the second triode K2, and the other end of the thirteenth resistor R13 is connected to the fourteenth resistor R14 and the fifteenth resistor R15 at a seventh node Q7. The fourteenth resistor R14 is connected in series between the seventh node Q7 and the gate of the third transistor M3, the fifteenth resistor R15 is connected in series between the seventh node Q7 and the gate of the fourth transistor M4, the sixteenth resistor R16 is connected in series between the source of the third transistor M3 and the pulse generating module 10, the source of the fourth transistor M4 is electrically connected to the timing control module TCON, and the drains of both the third transistor M3 and the fourth transistor M4 are electrically connected to the level conversion module L / S.

[0056] Among them, the third transistor M3 is a P-type MOS transistor, and the fourth transistor M4 is an N-type MOS transistor. When the voltage at the emitter of the second triode K2 is at a low level, the voltage at the seventh node Q7 is also at a low level, causing the third transistor M3 to turn on and the fourth transistor M4 to turn off, and the switching unit 22 outputs a voltage signal from the pulse generating module 10 to the level conversion module L / S. When the voltage at the emitter of the second triode K2 is at a high level, the voltage at the seventh node Q7 is also at a high level, causing the third transistor M3 to turn off and the fourth transistor M4 to turn on, and the switching unit 22 outputs a display timing signal TS from the timing control module TCON to the level conversion module L / S.

[0057] By setting the switching unit 22 to include a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third transistor M3, and a fourth transistor M4, one end of the thirteenth resistor R13 is electrically connected to the emitter of the second triode K2, and the other end of the thirteenth resistor R13 is connected to the fourteenth resistor R14 and the fifteenth resistor R15 at a seventh node Q7. The fourteenth resistor R14 is connected in series between the seventh node Q7 and the gate of the third transistor M3, the fifteenth resistor R15 is connected in series between the gate of the fourth transistor M4, the sixteenth resistor R16 is connected in series between the source of the third transistor M3 and the pulse generating module 10, the source of the fourth transistor M4 is electrically connected to the timing control module TCON, and the drains of the third transistor M3 and the fourth transistor M4 are both electrically connected to the level conversion module L / S, so that the switching module can drive the switching unit 22 according to whether the timing control module TCON has completed initialization, so that the level conversion module L / S can automatically switch between being electrically connected to the pulse generating module 10 and being electrically connected to the timing control module TCON.

[0058] Please refer to Figure 3 , the present invention also provides a display panel 1000, including a gate driving circuit 200 and the signal switching circuit 100 in the embodiment of the present invention, and the gate driving circuit 200 is electrically connected to the level conversion module L / S. Optionally, the display panel 1000 can be an OLED display panel or an LCD display panel using oxide thin film transistor technology, etc., without limitation.

[0059] Among them, the gate driving circuit 200 includes a plurality of gate driving units GOA, and the plurality of gate driving units GOA are electrically connected to a plurality of rows of pixel units P in a one-to-one correspondence. Before the display panel 1000 is powered on and the timing control module TCON completes initialization, the pulse generating module 10 outputs a square wave pulse PWM to the plurality of gate driving units GOA through the signal switching module 20 and the level conversion module L / S to eliminate the residual charges in the plurality of gate driving units GOA. After the timing control module TCON completes initialization, the timing control module TCON is used to output a display timing signal TS to the plurality of gate driving units GOA through the signal switching module 20 and the level conversion module L / S, so that the plurality of gate driving units GOA output scan signals row by row to turn on the plurality of rows of pixels row by row.

[0060] In addition, the display panel 1000 further includes a main board MB and a data driver SC. The main board MB and the data driver SC are both electrically connected to the timing control module TCON. The main board MB is used to process image data and output the image data to the timing control module TCON. The timing data module converts the image data from the main board MB into a data signal to the data driver SC, and the data driver SC outputs a data voltage to the pixel unit P according to the data signal.

[0061] Among them, the display panel 1000 includes a display area AA and a non-display area NA. The pixel unit P is disposed in the display area AA. In the embodiment of the present invention, the signal switching circuit 100, the gate driving circuit 200, the main board MB, and the data driver SC are all disposed in the non-display area NA.

[0062] For the display panel 1000 provided by the present invention, by adopting the gate driving circuit 200 and the signal switching circuit 100 in the embodiment of the present invention, and the gate driving circuit 200 is electrically connected to the level conversion module L / S, it realizes automatically eliminating the residual voltage of the gate driving circuit 200 when the display panel 1000 is powered on. At the same time, after the timing control module TCON is initialized, the display panel 1000 can automatically switch to the state where the timing control module TCON is electrically connected to the level conversion module L / S to perform a normal display control process, improving the noise reduction effect of the display panel 1000 and reducing the production cost of the display panel 1000.

[0063] In the description of the embodiments of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application.

[0064] The above-disclosed is only a preferred embodiment of the present application. Of course, it cannot be used to limit the scope of rights of the present application. Those of ordinary skill in the art can understand all or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A signal switching circuit, characterized in that, For a display panel, the display panel includes a gate driving circuit, and the signal switching circuit includes: A timing control module; A level conversion module, electrically connected to the timing control module and configured to be electrically connected to the gate driving circuit; A pulse generation module, electrically connected to the level conversion module; A signal switching module, electrically connected to the timing control module, the level conversion module, and the pulse generation module; Wherein, before the display panel is powered on and the initialization of the timing control module is completed, the pulse generation module is configured to output a square wave pulse to the gate driving circuit through the signal switching module and the level conversion module to eliminate the residual voltage of the gate driving circuit. After the initialization of the timing control module is completed, the timing control module is configured to output a display timing signal to the gate driving circuit through the signal switching module and the level conversion module.

2. The signal switching circuit according to claim 1, wherein The pulse generation module includes a sampling unit, a reference unit, a comparison unit, and an output unit. The sampling unit and the reference unit are both electrically connected to the comparison unit. The comparison unit is electrically connected to the output unit. The output unit is electrically connected to the signal switching module. The sampling unit is configured to receive a turn-on voltage; Wherein, the sampling unit is configured to output a sampling voltage to the comparison unit according to the turn-on voltage. The reference unit is configured to output a first reference voltage and a second reference voltage to the comparison unit. The comparison unit is configured to output a comparison voltage to the output unit according to the sampling voltage, the first reference voltage, and the second reference voltage. The output unit is configured to output the square wave pulse to the gate driving circuit through the signal switching module and the level conversion module according to the comparison voltage.

3. The signal switching circuit according to claim 2, wherein The sampling unit includes a first input terminal, a first resistor, and a second resistor connected in series in sequence. The first input terminal is configured to receive the turn-on voltage. The first resistor and the second resistor are connected to a first node. The second resistor is connected in series between the first node and the ground terminal. The first node is electrically connected to the comparison unit.

4. The signal switching circuit according to claim 3, wherein The reference unit includes a first capacitor and a third resistor, a fourth resistor, a fifth resistor, and a second input terminal connected in series in sequence. The second input terminal is configured to receive a logic voltage. The first capacitor is connected in parallel with the fourth resistor. The third resistor and the fourth resistor are connected to a second node. The fourth resistor and the fifth resistor are connected to a third node. The third resistor is connected in series between the third node and the ground terminal. The second node and the third node are both electrically connected to the comparison unit. The second node is configured to output the first reference voltage. The third node is configured to output the second reference voltage.

5. The signal switching circuit according to claim 4, wherein The comparison unit includes a first comparator and a second comparator. The positive power supply terminals of the first comparator and the second comparator are both used to receive a logic voltage. The negative power supply terminals of the first comparator and the second comparator are both connected to the ground terminal. The non-inverting input terminals of the first comparator and the second comparator are both electrically connected to the first node. The inverting input terminal of the first comparator is electrically connected to the second node. The non-inverting input terminal of the second comparator is electrically connected to the third node. The output terminals of the first comparator and the second comparator are connected to the fourth node, and the fourth node is electrically connected to the output unit.

6. The signal switching circuit according to claim 5, wherein The output unit includes a first triode, a first transistor, a second transistor, a third input terminal, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The third input terminal is used to receive a logic voltage. The sixth resistor is connected in series between the fourth node and the base of the first triode. The seventh resistor is connected in series between the emitter of the first triode and the ground terminal. The eighth resistor is connected in series between the collector of the first triode and the third input terminal. The collector of the first triode, the gate of the first transistor, and the gate of the second transistor are connected to the fifth node. The source of the first transistor is electrically connected to the third input terminal. The ninth resistor is connected in series between the source of the second transistor and the ground terminal. The drain of the first transistor and the drain of the second transistor are connected to the sixth node, and the sixth node is electrically connected to the signal switching module.

7. The signal switching circuit according to claim 1, wherein The signal switching module includes a driving unit and a switching unit. The driving unit is electrically connected to both the timing control module and the switching unit. The switching unit is electrically connected to the pulse generating module, the timing control module, and the level conversion module.

8. The signal switching circuit according to claim 7, wherein The driving unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a second triode, and a fourth input terminal. The tenth resistor is connected in series between the base of the second triode and the timing control module. The eleventh resistor is connected in series between the fourth input terminal and the collector of the second triode. The twelfth resistor is connected in series between the emitter of the second triode and the ground terminal. The emitter of the second triode is electrically connected to the switching unit.

9. The signal switching circuit according to claim 8, wherein The switching unit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a third transistor, and a fourth transistor. One end of the thirteenth resistor is electrically connected to the emitter of the second triode. The other end of the thirteenth resistor is connected to the fourteenth resistor and the fifteenth resistor at the seventh node. The fourteenth resistor is connected in series between the seventh node and the gate of the third transistor. The fifteenth resistor is connected in series to the gate of the fourth transistor. The sixteenth resistor is connected in series between the source of the third transistor and the pulse generating module. The source of the fourth transistor is electrically connected to the timing control module. The drains of the third transistor and the fourth transistor are both electrically connected to the level conversion module.

10. A display panel, characterized in that, It includes a gate drive circuit and a signal switching circuit as described in any one of claims 1-9, and the gate drive circuit is electrically connected to the level conversion module.

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