Method and system for realizing AES based on FPGA

Abstract

The invention provides a method and a system for realizing AES (Advanced Encryption Standard) based on an FPGA (Field Programmable Gate Array), and relates to the field of channel transmission encryption and decryption, the method comprises the following steps: a plaintext is subjected to byte replacement, row shift, column mixing and round key addition circulation (N-1) rounds based on the FPGA, the Nth round is subjected to byte replacement, row shift and round key addition to obtain a ciphertext, and the number N of circulation rounds is designed according to the length of a key. The byte replacement comprises the following steps of: storing a byte lookup table by using an RAM (Random Access Memory) in an FPGA chip, and mapping a new byte in the lookup table according to each byte of the state equation to replace an original byte; the row shifting comprises the step of respectively circularly shifting the second row, the third row and the fourth row of the 4 * 4 state equation leftwards by 1, 2 and 3 bytes; column mixing comprises the following steps: left-multiplying a matrix of the state equation by a fixed matrix; the round key addition comprises the steps that the state equation and the round key are subjected to bitwise exclusive OR, a new state equation is obtained, and the round key is obtained through key expansion. According to the invention, the AES can be realized on the FPGA with fewer logic resources.

Description

Technical Field

[0001] The present invention relates to the field of channel transmission encryption and decryption, and particularly to a method and system for implementing AES based on FPGA. Background Art

[0002] In the fields of information security and cryptography, there are many application fields that require ensuring transmission security and efficient encryption and decryption performance, such as satellite communication, virtual private network, hard disk encryption, and digital signature. During the information transmission process, if there is a leakage or misjudgment, serious consequences will occur. Especially in the military industry, the absolute security of information transmission must be guaranteed. With the increasing development of information technology, the DES (Data Encryption Standard) encryption and decryption algorithm has become less secure. To replace the DES algorithm, a new generation of AES (Advanced Encryption Standard) algorithm has been introduced. The computing power of the AES algorithm has been improved. Compared with the 56-bit key of the DES algorithm, AES has three key types: 128-bit, 192-bit, and 256-bit, and its security performance is higher than that of DES, and it can be applied to more scenarios.

[0003] In many application scenarios, the design of the AES algorithm is implemented on an FPGA (Field Programmable Gate Array). When implementing AES with an FPGA as the design platform, it has advantages such as high performance, low latency, parallelism, and high stability. Different from the serial processing of general-purpose processors, FPGA is parallel processing, and different stages of AES such as byte substitution, row shift, column mixing, and round key addition can be processed in parallel, reducing the processing time and improving the processing efficiency, thereby increasing the throughput of data processing.

[0004] Although the implementation of the traditional AES algorithm on FPGA has improved in performance, it consumes a large amount of FPGA logic resources. Because the parallel processing of different stages of AES such as byte substitution, row shift, column mixing, and round key addition consumes a lot of FPGA logic resources. If the FPGA chip used needs to consider cost performance, or the FPGA chip is applied to aerospace and industrial levels with stronger stability, the logic resources of these FPGA chips are generally less, and it is often encountered that the logic resources are insufficient when designing the AES algorithm on such FPGA chips. Therefore, according to the current high-resource design of the AES algorithm on FPGA, it is necessary to optimize the design of the AES algorithm to more effectively utilize the resources of FPGA.

[0005] There have been many technical attempts to implement the AES algorithm on FPGAs. For example, Chinese Patent CN119210696A, "A Hardware AES-GCM Method and System Based on FPGA," discloses a hardware AES-GCM method and system based on FPGA, which realizes the design of the AES algorithm on FPGA but ignores the logical resource consumption of FPGA during the implementation of the AES algorithm, reducing the actual application scenario types. Summary of the Invention

[0006] The object of the present invention is to: To solve the problem of low hardware resource implementation of the AES algorithm on FPGA, a method for implementing AES based on FPGA is proposed, including: Byte substitution based on FPGA, including: Using the on-chip RAM of FPGA to store the byte lookup table, mapping each byte of the state equation to a new byte in the lookup table, and replacing the original byte; Row shift based on FPGA, including: Not shifting the first row of the 4×4 matrix of the state equation, circularly shifting the second row left by 1 byte, circularly shifting the third row left by 2 bytes, and circularly shifting the fourth row left by 3 bytes; Column mixing based on FPGA, including: Left multiplying the 4×4 matrix of the state equation by a fixed 4×4 matrix; Round key addition based on FPGA, including: Performing bitwise exclusive OR on the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion; The plaintext is cycled N - 1 rounds in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, column mixing based on FPGA, and round key addition based on FPGA. In the Nth round, the ciphertext is obtained in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, and round key addition based on FPGA. The number of loop rounds N is designed according to different key lengths.

[0007] Further, the byte substitution based on FPGA specifically includes: After the FPGA is powered on and starts up, within 256 clock cycles, store the 256-byte lookup table into 16 on-chip RAMs of FPGA; The state equation has a total of 16 bytes. In one clock cycle, each byte maps a new byte in 16 on-chip RAMs of FPGA in parallel with the high 4 bits as the row and the low 4 bits as the column, and replaces the original byte in the state equation.

[0008] Further, the row shift based on FPGA specifically includes: According to the rule that the first row of the state equation is not shifted, the second row is circularly shifted left by 1 byte, the third row is circularly shifted left by 2 bytes, and the fourth row is circularly shifted left by 3 bytes, connect the 16 bytes storing the state equation to another register of 16 bytes in size through 128 parallel lines.

[0009] Further, the column mixing based on FPGA specifically includes: left-multiplying a 4×4 state matrix S by a 4×4 fixed matrix K, and storing the fixed matrix K in a register through 128 parallel lines within one clock cycle; after each byte of the state equation undergoes left-multiplication operation to obtain a new byte to replace the original byte, a total of 16 calculations are performed to obtain a new state equation.

[0010] Further, the formula for left-multiplying a 4×4 state matrix S by a 4×4 fixed matrix K is: , where, represents the new element obtained after left-multiplication operation for the element at the i-th row and j-th column of the state matrix S, , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the j-th column of the state matrix S, , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the i-th row of the fixed matrix K, represents multiplication, represents the exclusive OR operation; the multiplication among them adopts the binary operation based on GF(28).

[0011] Further, the round key addition based on FPGA specifically includes: performing bitwise exclusive OR on the 16 bytes storing the state equation through 128 parallel lines with the round key of the current round, and after the calculation is completed, connecting the data to another register with a size of 16 bytes.

[0012] Further, the key expansion of 256 bits is specifically as follows: If the number of columns i of the key to be expanded is not a multiple of 4, then W[i] = W[i - 8] ⊕ W[i - 1], where W[i] represents the i-th column of the expanded key, W[i - 8] represents the i - 8-th column of the expanded key, ⊕ represents bitwise exclusive OR, and W[i - 1] represents the i - 1-th column of the expanded key; If the number of columns i of the key to be expanded is a multiple of 4 but not a multiple of 8, then W[i] = W[i - 8] ⊕ S(W[i - 1]), where S( ) represents the byte substitution based on FPGA; If the number of columns i of the key to be expanded is a multiple of 8, then W[i] = W[i - 8] ⊕ T(W[i - 1]), where T( ) is the T function.

[0013] Further, The T function consists of three parts, namely byte substitution, column shift, and bitwise XOR with the constant T matrix; The byte substitution is implemented according to the FPGA-based byte substitution described above; The column shift is to shift each column up by one position, and the first bit is filled with the last bit; After the byte substitution and column shift are completed, the matrix is bitwise XORed with the j-th column of the constant T matrix according to the number of AES rounds. The j-th round corresponds to the j-th column of the T matrix, and the T function operation is completed.

[0014] The present invention also proposes a system for implementing AES based on FPGA, including: A byte substitution module for implementing FPGA-based byte substitution, including: using the on-chip RAM of the FPGA to store the byte lookup table, mapping each byte of the state equation to a new byte in the lookup table, and replacing the original byte; A row shift module for implementing FPGA-based row shift, including: not shifting the first row of the 4×4 matrix of the state equation, circularly shifting the second row left by 1 byte, circularly shifting the third row left by 2 bytes, and circularly shifting the fourth row left by 3 bytes; A column mixing module for implementing FPGA-based column mixing, including: left multiplying the 4×4 matrix of the state equation by a fixed 4×4 matrix; A round key addition module for implementing FPGA-based round key addition, including: performing bitwise XOR between the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion; A plaintext encryption module for cyclically performing the plaintext in the order of FPGA-based byte substitution, FPGA-based row shift, FPGA-based column mixing, and FPGA-based round key addition for N - 1 rounds. In the N-th round, the ciphertext is obtained in the order of FPGA-based byte substitution, FPGA-based row shift, and FPGA-based round key addition, and the number of cyclic rounds N is designed according to different key lengths.

[0015] The beneficial effects brought by the technical solution provided by the present invention are: The present invention provides an AES implementation method and system with low hardware resources based on FPGA. According to the basic principle of the AES algorithm, with FPGA as the design platform, the low-resource implementation of the AES algorithm on FPGA is realized. The core design contents of the algorithm include: byte substitution, row shift, column mixing, round key addition, key expansion, etc. Different numbers of round loops are designed according to different key lengths to complete encryption and decryption. Compared with other AES implementation systems on FPGA, the present invention uses parallel on-chip RAM of FPGA to store lookup tables, greatly reducing the logic resources used by the system, shortening the logic levels of the system, and reducing the clock delay time. At the same time, the design of the AES algorithm can be realized on FPGA with less logic resources, increasing the actual application scenarios of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is the flowchart of the encryption method for implementing AES based on FPGA in an embodiment of the present invention; Figure 2 is the flowchart of the parallel on-chip RAM of FPGA for storing lookup tables in an embodiment of the present invention; Figure 3 is the flowchart of substituting bytes by the parallel on-chip RAM of FPGA in an embodiment of the present invention; Figure 4 is the schematic diagram of row shift in an embodiment of the present invention; Figure 5 is the schematic diagram of column mixing in an embodiment of the present invention; Figure 6 is the schematic diagram of round key addition in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0018] The present invention provides an AES implementation method with low hardware resources based on FPGA. The flowchart of the encryption method refers to Figure 1 , and the plaintext is cycled N - 1 rounds according to byte substitution based on FPGA, row shift based on FPGA, column mixing based on FPGA, and round key addition based on FPGA. In the Nth round, the ciphertext is obtained in the order of byte substitution based on FPGA, row shift based on FPGA, and round key addition based on FPGA. N is the number of round loops, and different numbers of round loops are designed according to different key lengths. The AES block length is 128 bits, and the key length can be selected as 128 bits, 192 bits or 256 bits, corresponding to 10 rounds, 12 rounds or 14 rounds of encryption processes respectively. The embodiment of the present invention uses a 256-bit key and adopts the key expansion method for 256-bit keys.

[0019] The byte substitution based on FPGA, the row shift based on FPGA, the column mixing based on FPGA, and the round key addition based on FPGA are specifically as follows: (1) The byte substitution based on FPGA includes: using the on-chip RAM of the FPGA to store the byte lookup table, mapping each byte in the state equation to a new byte in the lookup table, and replacing the original byte.

[0020] The byte lookup table is usually stored using Reg registers. When the lookup tables of 256 bytes are all stored through Reg registers, it will consume a large amount of the logic resources of the FPGA. If the byte lookup table is stored using Reg registers, it generally accounts for about half of the resources of the entire AES design. Using 16 parallel on-chip RAMs of the FPGA to store the byte lookup table can complete the substitution of 16 bytes in the state equation in one cycle, and only occupies the RAM resources of the FPGA, basically does not consume the logic resources of the FPGA, and does not affect the throughput and rate of the AES algorithm. The state equation is a 4×4 byte matrix, with a total of 16 bytes (128 bits).

[0021] After the FPGA is powered on and starts up, the lookup table of 256 bytes is immediately stored in 16 appropriately sized on-chip RAMs of the FPGA within 256 clock cycles. This lookup table is a 16×16 table; the state equation has a total of 16 bytes. In one clock cycle, each byte maps to a new byte in 16 on-chip RAMs of the FPGA with the high 4 bits as the row and the low 4 bits as the column in parallel, and replaces the original byte in the state equation.

[0022] Reference Figure 2 , Figure 2 is the flowchart of storing the lookup table in parallel on-chip RAM of the embodiment of the present invention. The present invention provides a flowchart of storing the lookup table in parallel on-chip RAM. After the system is powered on and stable, the write enable of the RAM is pulled high, and the lookup table of 256 bytes is sequentially stored in the on-chip RAM of the FPGA and stored within 128 clock cycles.

[0023] Reference Figure 3 , Figure 3 is the flowchart of replacing bytes using the parallel on-chip RAM of the embodiment of the present invention. When the state equation reaches the byte substitution module, the byte substitution module is enabled to work. After the byte substitution module works, the read function of the on-chip RAM of the FPGA is enabled. The state equation has a total of 16 bytes, and each byte corresponds to a read address of an on-chip RAM of the FPGA. In this process, the read enable needs to be synchronized with the read address. The data read out for each byte replaces the original byte to complete the byte substitution, thus forming a new state equation.

[0024] (2) Row shift based on FPGA, including: leaving the first row of the 4×4 matrix of the state equation unshifted, circularly shifting the second row left by 1 byte, circularly shifting the third row left by 2 bytes, and circularly shifting the fourth row left by 3 bytes. During this process, the highest bit shifted out is successively filled at the end. For example, a row left shift of 3 bits is represented as: .

[0025] The 16 bytes storing the state equation are connected through 128 parallel lines. According to the rule that the first row of the state equation is unshifted, the second row is circularly shifted left by 1 byte, the third row is circularly shifted left by 2 bytes, and the fourth row is circularly shifted left by 3 bytes, and during this process, the highest bit shifted out is successively filled at the end, the data is connected to another register with a size of 16 bytes.

[0026] Reference Figure 4 , Figure 4 is the schematic diagram of row shift in the embodiment of the present invention. In the general design process, only the thread docking between the state equation registers needs to be completed, so basically no logic resources of the FPGA are consumed.

[0027] (3) Column mixing based on FPGA, including: left multiplying the 4×4 matrix of the state equation by a fixed 4×4 matrix, using shift and exclusive OR logic. The multiplication of two 4×4 matrices requires that the number of columns of the first matrix must be equal to the number of rows of the second matrix; their product results in a new matrix, where the number of rows of each number in the new matrix is equal to the number of rows of the first matrix, and the number of columns is equal to the number of columns of the second matrix.

[0028] Left multiply the 4×4 state matrix S by a 4×4 fixed matrix K. This fixed matrix is stored in the register through 128 parallel lines within one clock cycle; each byte of the state equation after left multiplication operation to obtain a new byte will replace the original byte, and a total of 16 calculations are performed to obtain a new state equation. The left multiplication operation is expressed as: , where, represents the new element obtained after the left multiplication operation of the i-th row and j-th column of the state matrix S, , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the j-th column of the state matrix S, , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the i-th row of the fixed matrix K, represents multiplication, represents the bitwise exclusive OR (XOR) operation of two bytes.

[0029] The multiplication among them Adopts a binary operation based on GF(2 8 ). A finite field is a field containing a finite number of elements. Represent the field containing 2 M elements by GF(2 M ). There are multiple primitive polynomials in each field. When M = 8, the primitive polynomial in AES is an irreducible polynomial . The main process is to regard two bytes as the coefficients of a polynomial, and then multiply them according to the polynomial rules. If the highest power of the resulting polynomial reaches or exceeds 8, divide the result by f(x) and take the remainder as the final result. Repeat dividing by f(x) until the highest power of the resulting polynomial is less than 8.

[0030] Reference Figure 5 , Figure 5 is the schematic diagram of column mixing in the embodiment of the present invention. Column mixing is to left-multiply the state equation by a fixed matrix, and the four arithmetic operations used in matrix multiplication are carried out in the Galois field (GF(2 8 )). There are a total of sixteen groups of data operations, mainly using shift and exclusive OR calculations.

[0031] (4) Round key addition based on FPGA includes: performing bitwise exclusive OR on the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion. The round key is a 4×4 byte matrix, with a total of 16 bytes and 128 bits.

[0032] Perform bitwise exclusive OR on the 16 bytes storing the state equation through 128 parallel lines with the round key of the current round. After the calculation is completed, connect the data to another register with a size of 16 bytes.

[0033] The 256-bit key expansion is specifically divided into three cases: (1) If the number of columns i of the key to be expanded is not a multiple of 4, lead out the (i - 8)-th column of the expanded key through 32 parallel lines, and perform bitwise exclusive OR with the (i - 1)-th column of the expanded key. The exclusive OR result is output bitwise through 32 parallel lines to replace the original bytes in the i-th column of the expanded key. Expressed by the formula as: W[i]=W[i - 8]⊕W[i - 1], where, W[i] represents the i-th column of the expanded key, W[i - 8] represents the (i - 8)-th column of the expanded key, ⊕ represents bitwise exclusive OR, and W[i - 1] represents the (i - 1)-th column of the expanded key.

[0034] (2) If the number of columns of the key to be expanded, i, is a multiple of 4 but not a multiple of 8, the (i - 8)-th column of the expanded key is led out through 32 parallel lines and bitwise XORed with the (i - 1)-th column of the expanded key after performing the S transformation. The XOR result is output bitwise through 32 parallel lines to the i-th column of the expanded key to replace the original bytes. It is expressed by the formula: W[i]=W[i - 8]⊕S(W[i - 1]), where S( ) represents the byte substitution based on FPGA.

[0035] (3) If the number of columns of the key to be expanded, i, is a multiple of 8, the (i - 8)-th column of the expanded key is led out through 32 parallel lines and bitwise XORed with the (i - 1)-th column of the expanded key after performing the T transformation. The XOR result is output bitwise through 32 parallel lines to the i-th column of the expanded key to replace the original bytes. It is expressed by the formula: W[i]=W[i - 8]⊕T(W[i - 1]), where T( ) is the T function. The T function consists of three parts, namely byte substitution, column shift, and bitwise XOR with the constant T matrix. The byte substitution is implemented according to the byte substitution based on FPGA; the column shift is to shift the whole column up by one bit, and the first bit is filled with the last bit. For example: , the unshifted column is led out through 32 parallel lines, where the 1st - 8th parallel lines are connected to the 25th - 32nd bits of the new register, and the 9th - 32nd parallel lines are connected to the 1st - 24th bits of the new register; after completing the byte substitution and column shift, it is bitwise XORed with the j-th column of the T matrix according to the number of rounds of AES. The j-th round corresponds to the j-th column of the T matrix to complete the T function operation.

[0036] Reference Figure 6 , Figure 6 is the schematic diagram of the round key addition in the embodiment of the present invention. The round key addition is to perform XOR operation on a certain column of the state equation according to the number of rounds of encryption and decryption with the corresponding column number of the key expansion to obtain a new state matrix.

[0037] The present invention also proposes a system for implementing AES based on FPGA, including: A byte substitution module for implementing byte substitution based on FPGA, including: using the on-chip RAM of the FPGA to store the byte lookup table, mapping a new byte for each byte of the state equation in the lookup table, and replacing the original byte; A row shift module for implementing row shift based on FPGA, including: not shifting the first row of the 4×4 matrix of the state equation, circularly shifting the second row left by 1 byte, circularly shifting the third row left by 2 bytes, and circularly shifting the fourth row left by 3 bytes; A column mixing module for implementing column mixing based on FPGA, including: multiplying the 4×4 matrix of the state equation on the left by a fixed 4×4 matrix; The round key addition module is used to implement round key addition based on FPGA, including: performing bitwise exclusive OR on the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion; The plaintext encryption module is used to cyclically encrypt the plaintext for N - 1 rounds in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, column mixing based on FPGA, and round key addition based on FPGA. In the Nth round, the ciphertext is obtained in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, and round key addition based on FPGA. The number of cyclic rounds N is designed according to different key lengths.

[0038] Compared with the prior art, the present invention has the following advantages: 1. Compared with the implementation of other AES algorithms on FPGA, the present invention uses the on-chip RAM of parallel FPGAs to store the byte lookup table, avoiding the use of FPGA logic registers for storage, and greatly reducing the FPGA logic resources used.

[0039] 2. Since the present invention uses the on-chip RAM of parallel FPGAs to store the byte lookup table, the use of many registers is reduced. While reducing the logic resources, the logical levels of the system are also reduced, optimizing the pipeline link of the system. Therefore, the delay per clock cycle is reduced; 3. The present invention uses the on-chip RAM of parallel FPGAs to store the byte lookup table, optimizing the pipeline link of the system. Therefore, the delay per clock cycle is reduced, the maximum frequency of the system design is increased, and thus the throughput of encrypted and decrypted data can be improved.

[0040] 4. The present invention uses less logic resources, has a short pipeline link, small clock delay, optimized algorithm throughput, and increases the actual application scenarios of the system.

[0041] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for implementing AES based on FPGA, characterized in that, Including: Byte substitution based on FPGA, including: using the on-chip RAM of the FPGA to store the byte lookup table, mapping each byte in the state equation to a new byte in the lookup table, and replacing the original byte; Row shift based on FPGA, including: leaving the first row of the 4×4 matrix of the state equation unshifted, cyclically shifting the second row left by 1 byte, the third row left by 2 bytes, and the fourth row left by 3 bytes; Column mixing based on FPGA, including: left multiplying the 4×4 matrix of the state equation by a fixed 4×4 matrix; Round key addition based on FPGA, including: performing bitwise exclusive OR on the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion; The plaintext is cycled N - 1 rounds in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, column mixing based on FPGA, and round key addition based on FPGA. In the Nth round, the ciphertext is obtained in sequence according to the order of byte substitution based on FPGA, row shift based on FPGA, and round key addition based on FPGA. The number of round cycles N is designed according to different key lengths.

2. The method for implementing AES based on FPGA according to claim 1, characterized in that The byte substitution based on FPGA specifically includes: after the FPGA is powered on and started, within 256 clock cycles, store the 256-byte lookup table into 16 on-chip RAMs of the FPGA; the state equation has a total of 16 bytes. In one clock cycle, each byte maps to a new byte in the 16 on-chip RAMs in parallel with the high 4 bits as the row and the low 4 bits as the column, and replaces the original byte in the state equation.

3. The method for implementing AES based on FPGA according to claim 1, characterized in that The row shift based on FPGA specifically includes: according to the rule that the first row of the state equation is not shifted, the second row is cyclically shifted left by 1 byte, the third row is cyclically shifted left by 2 bytes, and the fourth row is cyclically shifted left by 3 bytes, connect the 16 bytes storing the state equation to another register of 16 bytes in size through 128 parallel lines.

4. The method for implementing AES based on FPGA according to claim 1, characterized in that The column mixing based on FPGA specifically includes: left multiplying the 4×4 state matrix S by a 4×4 fixed matrix K. The fixed matrix K is stored in the register through 128 parallel lines within one clock cycle; each byte of the state equation is left multiplied to obtain a new byte to replace the original byte, and a total of 16 calculations are performed to obtain a new state equation.

5. A method for implementing AES based on FPGA according to claim 4, characterized in that, The formula for left multiplying the 4×4 state matrix S by a 4×4 fixed matrix K is: ， Among them, represents the new element obtained after the left multiplication operation on the \(i\)-th row and \(j\)-th column of the state matrix \(S\), , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the \(j\)-th column of the state matrix \(S\), , , , respectively represent the 0th, 1st, 2nd, and 3rd elements of the \(i\)-th row of the fixed matrix \(K\), represents multiplication, represents the exclusive-or operation; the multiplication among them adopts the binary operation based on GF(2 8 ).

6. The method for implementing AES based on FPGA according to claim 1, characterized in that The round key addition based on FPGA specifically includes: performing bitwise exclusive OR on the 16 bytes storing the state equation through 128 parallel lines with the round key of the current round. After the calculation is completed, the data is connected to another register of 16 bytes in size.

7. A method for implementing AES based on FPGA according to claim 1, wherein: The 256-bit key expansion is specifically as follows: If the number of columns i of the key to be expanded is not a multiple of 4, then W[i]=W[i - 8]⊕W[i - 1], where W[i] represents the i-th column of the expanded key, W[i - 8] represents the (i - 8)-th column of the expanded key, ⊕ represents bitwise exclusive OR, and W[i - 1] represents the (i - 1)-th column of the expanded key; If the number of columns i of the key to be expanded is a multiple of 4 but not a multiple of 8, then W[i]=W[i - 8]⊕S(W[i - 1]), where S( ) represents byte substitution based on FPGA; If the number of columns i of the key to be expanded is a multiple of 8, then W[i]=W[i - 8]⊕T(W[i - 1]), where T( ) is the T function.

8. A method for implementing AES based on FPGA according to claim 7, wherein: The T function consists of three parts, namely byte substitution, row shift, and bitwise exclusive OR with the constant T matrix; Byte substitution is implemented according to the byte substitution based on FPGA; Row shift is to shift the whole row up by one bit, and the first bit is filled with the last bit; After byte substitution and row shift are completed, the matrix is bitwise exclusive OR with the j-th column of the constant T matrix according to the number of AES rounds. The j-th round corresponds to the j-th column of the T matrix, and the T function operation is completed.

9. A system for implementing AES based on FPGA, characterized in that, Including: Byte substitution module, used to implement byte substitution based on FPGA, including: using the on-chip RAM of FPGA to store the byte lookup table, mapping each byte of the state equation to a new byte in the lookup table, and replacing the original byte; Row shift module, used to implement row shift based on FPGA, including: not shifting the first row of the 4×4 matrix of the state equation, circularly shifting the second row left by 1 byte, circularly shifting the third row left by 2 bytes, and circularly shifting the fourth row left by 3 bytes; Column mixing module, used to implement column mixing based on FPGA, including: multiplying the 4×4 matrix of the state equation on the left by a fixed 4×4 matrix; Round key addition module, used to implement round key addition based on FPGA, including: performing bitwise exclusive OR on the state equation and the round key to obtain a new state equation, where the round key is obtained through key expansion; Plaintext encryption module, used to cycle N - 1 rounds of the plaintext in the order of byte substitution based on FPGA, row shift based on FPGA, column mixing based on FPGA, and round key addition based on FPGA in sequence. In the N-th round, the ciphertext is obtained in the order of byte substitution based on FPGA, row shift based on FPGA, and round key addition based on FPGA in sequence. The number of loop rounds N is designed according to different key lengths.

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