N-type TOPCon battery and preparation method thereof

Abstract

The embodiment of the invention provides an N-type TOPCon battery and a preparation method thereof, and the preparation method of the N-type TOPCon battery provided by the embodiment of the invention comprises the following steps: after texturing treatment, firstly forming a first mask oxide layer in a non-grid line region on the front surface of a silicon wafer, and then carrying out boron diffusion treatment, as the first mask oxide layer exists in the first region serving as the non-grid line region, boron atoms can be prevented from entering, and the requirement for low doping concentration can be met; boron atoms can be doped at a high concentration due to exposure and no oxidation layer obstruction of the second region serving as the grid line region, and the sheet resistance can be as low as 60 ohms, so that the purpose of boron atom high-low concentration doping in the grid line region and the non-grid line region is achieved, damage of laser doping to the silicon substrate is avoided, and the service life of the silicon substrate is prolonged. And the open voltage and the photoelectric conversion efficiency of the cell can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and particularly to an N-type TOPCon cell and a method for preparing the same. Background Art

[0002] Currently, N-type TOPCon cells in crystalline silicon solar cells are widely used due to their advantages such as small attenuation, obvious overall efficiency and power generation advantages of the cells.

[0003] In order to effectively reduce surface recombination and reduce metal contact resistance, the front side of the N-type TOPCon cell forms a boron-doped layer by means of boron diffusion, laser doping and oxidation propulsion.

[0004] Although the above method can reduce the sheet resistance in the grid line area, it causes great damage to the silicon substrate, and the boron atom content in the non-grid line area is relatively high after oxidation, resulting in a lower sheet resistance and larger surface recombination in this area, and the photoelectric conversion efficiency of the cell cannot be effectively improved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an N-type TOPCon cell and a method for preparing the same, so as to solve the problem that the formation method of the boron-doped layer in the existing N-type TOPCon cell causes great damage to the silicon substrate, and the boron atom content in the non-grid line area is relatively high after oxidation, and the photoelectric conversion efficiency of the cell cannot be effectively improved.

[0006] To solve the above problems, the present invention is realized by the following technical solutions:

[0007] The present invention provides a method for preparing an N-type TOPCon cell, which includes:

[0008] After texturing the N-type silicon wafer, a first mask oxide layer is formed in a first region on the front side; wherein, the front grid line is projected outside the range of the first region;

[0009] The front side of the silicon wafer is subjected to boron diffusion treatment to form a boron-doped layer in a second region on the front side; wherein, the second region is the front region not covered by the first mask oxide layer;

[0010] A tunneling oxide layer is formed on the back side, and a phosphorus-doped polysilicon layer is formed on the back side;

[0011] After forming the phosphorus-doped polysilicon layer on the back side, the first mask oxide layer is removed, and a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer, a front grid line in contact with the boron-doped layer, and a back grid line in contact with the phosphorus-doped polysilicon layer are sequentially formed.

[0012] Further, in the preparation method, forming the first mask oxide layer in the first region on the front side includes:

[0013] Form a second mask oxide layer covering the front side of the silicon wafer;

[0014] Perform laser grooving on a third region of the second mask oxide layer, where the third region is opposite to the second region.

[0015] Further, in the preparation method, forming the second mask oxide layer covering the front side of the silicon wafer includes:

[0016] Form a silicon dioxide layer with a thickness of 10 - 30 nm on the front side as the second mask oxide layer.

[0017] Further, in the preparation method, forming the second mask oxide layer covering the front side of the silicon wafer includes:

[0018] Under the conditions of a temperature of 850 - 950 °C, an oxygen flow rate of 10000 - 20000 sccm / min, and a pressure of 600 - 900 mbar, oxidize the front side of the silicon wafer for 20 - 40 min.

[0019] Further, in the preparation method, performing boron diffusion treatment on the front side of the silicon wafer includes:

[0020] Deposit for 15 - 25 min under the conditions of a temperature of 830 - 870 °C, a BCl3 flow rate of 300 - 400 sccm / min, an oxygen flow rate of 800 - 1000 sccm / min, a nitrogen flow rate of 1500 - 3000 sccm / min, and a pressure of 150 - 200 mbar, then raise the temperature of the silicon wafer to 1020 - 1050 °C and perform high-temperature promotion treatment for 40 - 80 min under the conditions of a nitrogen flow rate of 8000 - 15000 sccm / min and a pressure of 700 - 950 mbar.

[0021] Further, in the preparation method, removing the first mask oxide layer includes:

[0022] Perform chain acid pickling on the front side of the silicon wafer to remove the phosphosilicate glass layer on the front side;

[0023] After removing the phosphosilicate glass layer on the front side, perform alkali etching treatment on the front side of the silicon wafer to remove the deposited polysilicon layer on the front side;

[0024] After removing the deposited polysilicon layer on the front side, perform chain acid pickling on the front side and the back side of the silicon wafer to remove the borosilicate glass layer on the front side, the first mask oxide layer, and the phosphosilicate glass layer on the back side.

[0025] Further, in the preparation method, during the process of removing the phosphosilicate glass layer on the front side, chain pickling is performed using hydrofluoric acid with a mass percentage of 8-15%; and / or

[0026] During the process of removing the polycrystalline silicon layer on the front side, the front side of the silicon wafer is subjected to alkaline etching treatment using KOH and a texturing additive; and / or

[0027] During the process of removing the borosilicate glass layer on the front side, the first mask oxide layer, and the phosphosilicate glass layer on the back side, the chain pickling is performed using hydrofluoric acid with a mass percentage of 25-40%.

[0028] Further, in the preparation method, texturing the N-type silicon wafer includes:

[0029] Performing double-sided texturing treatment on the silicon wafer using a texturing solution at 75-85°C. By volume, the texturing solution includes 20-25 parts of a KOH solution with a mass percentage of 45%, 3-7 parts of a texturing additive, and 450-500 parts of water. The texturing additive includes a surfactant with a mass percentage of 2-3.5%, a defoaming agent with a mass percentage of 1-3%, a nucleating agent with a mass percentage of 1-1.5%, sodium benzoate with a mass percentage of 4-6%, and water with a mass percentage of 86-90%.

[0030] Further, in the preparation method, the front gate line projection coincides with the second region range.

[0031] The present invention also provides an N-type TOPCon battery, which is prepared by the above method.

[0032] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0033] In the embodiments of the present invention, in the preparation method of the N-type TOPCon battery, after texturing treatment, a first mask oxide layer is first formed in the non-gate line region on the front side of the silicon wafer, and then boron diffusion treatment is performed. Since there is a first mask oxide layer in the first region as the non-gate line region, it can block the entry of boron atoms and achieve the requirement of a lower doping concentration; while the second region as the gate line region is exposed and there is no oxide layer barrier, boron atoms can be doped at a high concentration, and its sheet resistance can be as low as 60Ω. It not only achieves the purpose of high and low concentration doping of boron atoms in the gate line region and the non-gate line region, but also avoids damage to the silicon substrate by laser doping, and can effectively improve the open-circuit voltage and photoelectric conversion efficiency of the battery chip.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0035] Figure 1 It is a flowchart of the preparation method of the N-type TOPCon battery provided by the embodiment of the present invention. Specific embodiments

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The applicant of the present invention found that when preparing the N-type TOPCon battery, the boron doping layer is formed on the front side by boron diffusion, laser doping, and oxidation promotion. Although the sheet resistance in the gate line region can be reduced to 60-80 Ω, the damage to the silicon substrate is relatively large, and the boron atom content in the non-gate line region is relatively high after oxidation, resulting in its sheet resistance remaining at a relatively low level of 200-240 Ω, and the surface recombination is relatively large, so the photoelectric conversion efficiency of the battery chip cannot be effectively improved.

[0038] In order to solve the above problems in the embodiments of the present invention, the embodiments of the present invention provide a preparation method of an N-type TOPCon battery, as Figure 1 shown, including step 101 to step 104:

[0039] Step 101, after texturing the N-type silicon wafer, form a first mask oxide layer in the first region on the front side; wherein, the front gate line is projected outside the range of the first region;

[0040] Step 102, perform boron diffusion treatment on the front side of the silicon wafer to form a boron doping layer in the second region on the front side; wherein, the second region is the front region not covered by the first mask oxide layer;

[0041] Step 103, form a tunneling oxide layer on the back side and form a phosphorus-doped polysilicon layer on the back side;

[0042] Step 104, after forming the phosphorus-doped polysilicon layer on the back side, remove the first mask oxide layer, and sequentially form a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer, a front gate line in contact with the boron doping layer, and a back gate line in contact with the phosphorus-doped polysilicon layer.

[0043] The preparation method of the N-type TOPCon battery provided by the embodiments of the present invention, after the texturing treatment, first forms a first mask oxide layer in the non-grid line area on the front side of the silicon wafer, and then performs boron diffusion treatment. Among them, because there is a first mask oxide layer in the first area as the non-grid line area, boron atoms can be blocked from entering, and the requirement of a lower doping concentration can be achieved, and its sheet resistance can reach more than 300 Ω; while the second area as the grid line area is exposed and there is no oxide layer barrier, boron atoms can be doped at a high concentration, and the sheet resistance of the formed boron-doped layer can be as low as 60 Ω. It not only achieves the purpose of high and low concentration doping of boron atoms in the grid line area and the non-grid line area, but also avoids the damage to the silicon substrate by laser doping, and can effectively improve the open voltage and photoelectric conversion efficiency of the battery chip.

[0044] In the above step 101, a certain size of N-type original silicon is selected for double-sided texturing treatment, that is, the preparation of a double-sided pyramid structure is carried out to ensure that the surface reflectivity of the texture is between 9% and 10%, for example, 9.4%; among them, the N-type original silicon can specifically be a silicon wafer of 182 mm × 182 mm. Optionally, the original silicon wafer is subjected to double-sided texturing treatment with a texturing solution at 75-85 °C. Among them, by volume, the above texturing solution includes 20-25 parts of a KOH solution with a mass percentage of 45%, 3-7 parts of a texturing additive, and 450-500 parts of water. Among them, the texturing additive includes a surfactant with a mass percentage of 2-3.5%, a defoaming agent with a mass percentage of 1-3%, a nucleating agent with a mass percentage of 1-1.5%, sodium benzoate with a mass percentage of 4-6%, and water with a mass percentage of 86-90%. The surfactant can be sodium lauryl polyoxyethylene ether or triglyceride, the defoaming agent can be oxypropylene glycerol ether or oxypropylene glycerol ether, and the nucleating agent can be sodium citrate.

[0045] In the above step 101, the textured silicon wafer is subjected to an oxidation process, and an oxide layer is formed in the first area outside the projection of the front grid line as the above first mask oxide layer, that is, the first mask oxide layer has a hollow area, and the hollow area is opposite to the front grid line, and the first area covers the non-grid line area.

[0046] Optionally, in one embodiment, forming the first mask oxide layer in the first area on the front side includes steps 111 to 112:

[0047] Step 111, forming a second mask oxide layer covering the front side of the silicon wafer;

[0048] Step 112, performing laser grooving treatment on the third area of the second mask oxide layer, and the third area is opposite to the second area.

[0049] In this embodiment, a second mask oxide layer covering the entire front surface is first formed on the front surface of the silicon wafer, and then the third region for forming the gate line is subjected to laser ablation treatment to form the above-mentioned hollowed-out region in the second mask oxide layer, thereby converting the second mask oxide layer into a first mask oxide layer that only covers the non-gate line region on the front surface.

[0050] Among them, when performing laser grooving on the third region of the second mask oxide layer, a laser is used to perform laser grooving in the form of laser marking with picosecond green light, and the laser power is 10 - 25 W, for example, it can be 13 W.

[0051] Optionally, in a specific embodiment, the above step 111 includes:

[0052] A silicon dioxide layer with a thickness of 10 - 30 nm is formed on the front surface as the second mask oxide layer.

[0053] In this specific embodiment, the textured silicon wafer is subjected to an oxidation process to grow a silicon dioxide mask layer with a thickness of 10 - 30 nm as the above-mentioned second mask oxide layer. This thickness can effectively block boron diffusion and is also convenient for subsequent removal. Optionally, the thickness of the second mask oxide layer can be one of 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm or a range value between any two of them.

[0054] Optionally, in a specific embodiment, the above step 111 specifically includes:

[0055] The front surface of the silicon wafer is oxidized for 20 - 40 min under the conditions of a temperature of 850 - 950 °C, an oxygen flow rate of 10000 - 20000 sccm / min, and a pressure of 600 - 900 mbar.

[0056] In this specific embodiment, by introducing oxygen with a flow rate of 10000 - 20000 sccm / min and continuously acting for 20 - 40 min under the conditions of a temperature of 850 - 950 °C and a pressure of 600 - 900 mbar, a silicon dioxide layer with a thickness of 10 - 30 nm can be formed on the front surface of the silicon wafer as the mask oxide layer.

[0057] In the above step 102, the textured silicon wafer is sent into a furnace tube for boron doping to form a boron-doped layer in the second region as the gate line region, thereby preparing a PN junction. Among them, since the second region as the gate line region is bare and there is no oxide layer barrier, boron atoms can be doped at a high concentration, and the sheet resistance of the formed boron-doped layer can be as low as 60 Ω, which is convenient for subsequent printing to form the front gate line; while in the first region as the non-gate line region, there is a first mask oxide layer, which can block boron atoms from entering, and can meet the requirement of a lower doping concentration, and its sheet resistance can reach more than 300 Ω. Subsequently, a boron-doped layer with a high concentration of boron doping is formed by boron diffusion.

[0058] Optionally, the surface boron doping concentration of the above boron-doped layer reaches 8E18 - 2E19 atoms / cm 3 , and the diffusion junction depth reaches between 0.6 and 1.2 μm.

[0059] Exemplarily, the textured silicon wafer is diffused. First, it is deposited for 15 - 25 min under the conditions of a temperature of 830 - 870 °C, a flow rate of BCl3 of 300 - 4000 sccm / min, an oxygen flow rate of 800 - 1000 sccm / min, a nitrogen flow rate of 1500 - 3000 sccm / min, and a pressure of 150 - 200 mbar. Then the silicon wafer is heated to 1020 - 1050 °C and treated for 40 - 80 min under a pressure of 700 - 950 mbar and an oxygen flow rate of 8000 - 15000 sccm / min to complete the boron diffusion treatment.

[0060] Since the boron diffusion treatment will form a borosilicate glass layer on the back of the silicon wafer, in the above step 103, before forming the tunneling oxide layer on the back, it is also necessary to remove the borosilicate glass layer on the back.

[0061] Optionally, removing the borosilicate glass layer on the back includes:

[0062] The back of the silicon wafer after boron diffusion treatment is subjected to chain pickling and alkali polishing treatment. Among them, by volume, the chain pickling solution includes 500 - 600 parts of hydrofluoric acid with a mass percentage of 49% and 50 - 100 parts of water. The temperature of the above alkali polishing treatment is 70 - 80 °C, and the alkali polishing solution includes 19 - 26 parts of a KOH solution with a mass percentage of 45%, 3 - 6 parts of an alkali polishing additive, and 450 - 500 parts of water. Among them, the alkali polishing additive includes a surfactant with a mass percentage of 2 - 3%, a defoaming agent with a mass percentage of 2 - 3%, an antifoaming agent with a mass percentage of 2 - 4%, glucose with a mass percentage of 2 - 3%, sodium polystyrene sulfonate with a mass percentage of 2 - 3%, and water with a mass percentage of 80 - 85%. The surfactant can be sodium lauryl polyoxyethylene sulfate or triglyceride, the defoaming agent can be oxypropylene glycerol ether or oxypropylene glycerol ether, and the antifoaming agent can be octylphenol polyoxyethylene ether.

[0063] In the above step 103, the N-type silicon wafer after removing the borosilicate glass layer on the back is subjected to low pressure chemical vapor deposition (LPCVD), first forming an ultra-thin silicon dioxide layer on the back of the N-type silicon wafer as an ultra-thin tunneling oxide layer, and then preparing a polysilicon layer with a thickness that can meet the transition passivation effect on both sides. Among them, because the preparation of the polysilicon layer on both sides is conducive to the subsequent removal of the front polysilicon layer, it is not easy to have the two extreme situations of excessive removal or insufficient removal, and the yield is better controlled.

[0064] Optionally, in one embodiment, a tunnel oxide layer is formed on the back side, and a phosphorus-doped polysilicon layer is formed on the back side, including steps 131 to 133:

[0065] Step 131, forming a silicon dioxide layer with a thickness of 2 to 3 nm on the back side as the tunneling oxide layer;

[0066] Step 132, forming a polysilicon layer with a thickness of 110-140 nm on the surface of the tunnel oxide layer;

[0067] Step 133 , phosphorus-doping the polysilicon layer to form the phosphorus-doped polysilicon layer.

[0068] In step 131, the N-type silicon wafer after forming the PN junction and removing the borosilicate glass layer on the back is subjected to low pressure chemical vapor deposition (LPCVD) and subjected to an oxygen volume of 250-350 L, a temperature of 590-610° C., and a pressure of 650-900 mbar for 20-35 minutes to form a silicon dioxide layer with a thickness of 2-3 nm on the back as a tunneling oxide layer. The oxygen flow rate is 40 L / min.

[0069] In step 132, after the tunneling oxide layer is formed, silane is introduced at a flow rate of 800 to 1200 sccm for 1700 to 2100 seconds at a temperature of 600 to 630°C and a pressure of 25 to 30 mbar, and a polysilicon layer having a thickness sufficient for the passivation effect is prepared on both sides or on a single side; the thickness can specifically be 110 to 140 nm.

[0070] Optionally, in one implementation, in the above step 133, phosphorus-doping the polysilicon layer to form a phosphorus-doped polysilicon layer includes:

[0071] Deposit for 14 - 20 min under the conditions of a temperature of 785 - 805 °C, a flow rate of POCl3 of 1100 - 1500 sccm / min, an oxygen flow rate of 500 - 700 sccm / min, and a pressure of 120 - 180 mbar. Then, heat the silicon wafer to 870 - 890 °C for high - temperature driving treatment for 25 - 35 min to obtain a phosphorus - doped polysilicon layer.

[0072] In this embodiment, by depositing for 14 - 20 min under the conditions of a temperature of 785 - 805 °C, a flow rate of POCl3 of 1100 - 1500 sccm / min, an oxygen flow rate of 500 - 700 sccm / min, and a pressure of 120 - 180 mbar, and then heating the silicon wafer to 870 - 890 °C for high - temperature driving treatment for 25 - 35 min, high - concentration doping of the polysilicon passivation layer can be completed, and a phosphorus - doped polysilicon layer with a phosphorus atom doping concentration of 6E20 - 8E20 / cm 3 is obtained.

[0073] In the embodiment of the present invention, the first mask oxide layer can be removed by pickling with HF during the subsequent BOE cleaning process.

[0074] Optionally, in one embodiment, in step 104 above, removing the first mask oxide layer includes:

[0075] Perform chain - type pickling on the front side of the silicon wafer to remove the phosphosilicate glass layer on the front side;

[0076] After removing the phosphosilicate glass layer on the front side, perform alkaline etching treatment on the front side of the silicon wafer to remove the deposited polysilicon layer on the front side;

[0077] After removing the deposited polysilicon layer on the front side, perform chain - type pickling on the front and back sides of the silicon wafer to remove the borosilicate glass layer on the front side, the first mask oxide layer, and the phosphosilicate glass layer on the back side.

[0078] In this embodiment, the front side of the silicon wafer after phosphorus doping is facing upwards and undergoes chain - type pickling to remove the phosphosilicate glass layer on the front side. Among them, the pickling solution in the chain - type pickling can be hydrofluoric acid with a mass percentage of 8 - 15%.

[0079] In this embodiment, after removing the phosphosilicate glass layer on the front side, an alkali etching treatment is continued to remove the polysilicon layer electroplated around the front side. Among them, by volume, the above alkali etching solution includes 16-24 parts of a KOH solution with a mass percentage of 45%, 3-7 parts of an etching additive, and 400-500 parts of water. Among them, the etching additive includes a surfactant with a mass percentage of 1-2%, a defoaming agent with a mass percentage of 2-3%, an antifoaming agent with a mass percentage of 1-3%, glucose with a mass percentage of 2-4%, sodium dodecyl sulfate with a mass percentage of 1-3%, and water with a mass percentage of 85-90%. The surfactant can be sodium lauryl polyoxyethylene ether sulfate or triglyceride, the defoaming agent can be oxypropylene glycerol ether or oxypropylene glycerol ether, and the antifoaming agent can be octylphenol polyoxyethylene ether.

[0080] In this embodiment, since a borosilicate glass layer is also formed on the front side of the silicon wafer during boron doping, which can protect the internal textured surface from damage during alkali polishing or alkali etching treatment. Therefore, after removing the polysilicon layer electroplated around the front side, a chain acid washing is used to remove the borosilicate glass layer on the front side of the silicon wafer, and the first mask oxide layer used to block boron doping in the non-grid line area can also be removed; in addition, a phosphosilicate glass layer is also formed on the back side of the silicon wafer during phosphorus doping, which also needs to be removed by chain acid washing after removing the polysilicon layer electroplated around the front side. Among them, the acid washing solution in the chain acid washing can be hydrofluoric acid with a mass percentage of 25-40%.

[0081] In step 104 above, an aluminum oxide film layer is deposited on the front side or both the front and back sides of the product by atomic layer deposition (ALD) process as a passivation layer to form field passivation. Among them, the thickness of the aluminum oxide film layer can be 2.5-5 nm;

[0082] After forming the aluminum oxide film layer, a silicon nitride layer is first deposited on the front side of the battery, with a comprehensive refractive index between 1.98 and 2.1 and the film thickness controlled at 70-84 nm; then a silicon nitride layer is deposited on the back side, with a comprehensive refractive index between 1.98 and 2.1 and the film thickness controlled at 75-90 nm; then positive and negative metal electrodes are prepared by printing and sintering. Among them, silver paste is used for the positive and negative main grids, silver-aluminum paste is used for the positive sub-grids, and silver paste is used for the back sub-grids. The sintering temperature is 780-840 °C, the time is 40-70 s, and the total consumption is controlled at 90-200 mg.

[0083] The present invention also proposes an N-type TOPCon battery, which is prepared by the above method.

[0084] For the above N-type TOPCon battery embodiment, it is prepared by the above method and can achieve the same technical effects. To avoid repetition, it will not be elaborated here. For relevant parts, refer to the partial description of the preparation method embodiment.

[0085] To make the invention object, technical solution and beneficial effects of the present invention clearer, the present invention will be further described below in conjunction with embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention.

[0086] Embodiment 1

[0087] (1) Select an N-type silicon wafer with a size of 182 mm × 182 mm, and perform double-sided texturing treatment on the original silicon wafer with a texturing solution at 82 °C. Among them, by volume, the texturing solution includes 23 parts of a KOH solution with a mass percentage of 45%, 5 parts of a texturing additive, and 470 parts of water. Among them, the texturing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 2%, a nucleating agent with a mass percentage of 1.2%, sodium benzoate with a mass percentage of 5.0%, and water with a mass percentage of 88.8%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the nucleating agent is sodium citrate;

[0088] (2) Oxidize the textured silicon wafer at a temperature of 900 °C, an oxygen flow rate of 15000 sccm / min, and a pressure of 700 mbar for 25 min to form a silicon dioxide mask layer;

[0089] (3) Perform laser grooving treatment on the silicon dioxide mask layer. The laser grooving position is the printed electrode area, and the laser power is 13 W;

[0090] (4) Feed the textured silicon wafer into the furnace tube, deposit for 20 min under the conditions of a temperature of 860 °C, a BCl3 flow rate of 350 sccm / min, an oxygen flow rate of 850 sccm / min, a nitrogen flow rate of 2000 sccm / min, and a pressure of 180 mbar, then raise the temperature of the silicon wafer to 1040 °C, and treat it at a pressure of 800 mbar and a nitrogen flow rate of 10000 sccm / min for 50 min to complete boron diffusion;

[0091] (5) Perform chain pickling on the back side of the silicon wafer after boron diffusion and perform alkaline polishing treatment to remove the boron-silicate glass layer on the back side. Among them, by volume, the chain pickling solution includes 550 parts of hydrofluoric acid with a mass percentage of 49% and 50 parts of water; the temperature of the above alkaline polishing treatment is 75 °C, and the alkaline polishing solution includes 22 parts of KOH solution with a mass percentage of 45%, 4 parts of alkaline polishing additive, and 470 parts of water. Among them, the alkaline polishing additive includes a surfactant with a mass percentage of 2.5%, a defoaming agent with a mass percentage of 2.5%, an antifoaming agent with a mass percentage of 3%, glucose with a mass percentage of 2.5%, sodium polystyrene sulfonate with a mass percentage of 2.5%, and water with a mass percentage of 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is polydimethylsiloxane;

[0092] (6) Perform Low Pressure Chemical Vapor Deposition (LPCVD) on the N-type silicon wafer after boron doping, and introduce 300 L of oxygen at a flow rate of 40 L / min, and act at a temperature of 600 °C and a pressure of 850 mbar for 22 min, then a silicon dioxide layer with a thickness of 2.3 nm can be formed on the back side as the tunneling oxide layer;

[0093] (7) After forming the tunneling oxide layer, at a temperature of 610 °C and a pressure of 27 mbar, introduce silane with a flow rate of 1150 sccm and continue for 1900 s to prepare a polysilicon layer with a thickness of 130 nm;

[0094] (8) After forming the polysilicon layer, deposit the silicon wafer at a temperature of 795 °C, a POCl3 flow rate of 1350 sccm / min, an oxygen flow rate of 650 sccm / min, and a pressure of 150 mbar for 16 min, and then heat the silicon wafer to 885 °C for high-temperature drive-in treatment for 30 min to complete high-concentration doping of the polysilicon passivation layer and obtain a phosphorus-doped polysilicon layer;

[0095] (9) Face the front side of the silicon wafer after phosphorus doping and perform chain pickling to remove the phosphorus-silicate glass layer on the front side. Among them, the pickling solution in the chain pickling uses hydrofluoric acid with a mass percentage of 9%;

[0096] (10) After removing the phosphosilicate glass layer on the front side, the silicon wafer is subjected to alkaline etching to remove the polysilicon layer electroplated on the front side. Among them, by volume, the above alkaline etching solution includes 17 parts of a KOH solution with a mass percentage of 45%, 4 parts of an etching additive, and 450 parts of water. Among them, the etching additive includes a surfactant with a mass percentage of 1.5%, a defoaming agent with a mass percentage of 2.5%, an antifoaming agent with a mass percentage of 2%, glucose with a mass percentage of 3%, sodium dodecyl sulfate with a mass percentage of 2%, and water with a mass percentage of 89%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is octylphenol polyoxyethylene ether;

[0097] (11) After removing the polysilicon layer electroplated on the front side, the front and back sides of the silicon wafer are subjected to chain pickling to remove the borosilicate glass layer on the front side, the silicon dioxide mask layer, and the phosphosilicate glass layer on the back side. Among them, in the chain pickling, the pickling solution uses hydrofluoric acid with a mass percentage of 30%;

[0098] (12) The silicon wafer is subjected to ALD process to deposit aluminum oxide film layers on both sides, with a thickness maintained at 3.5 nm;

[0099] (13) Deposit a silicon nitride layer with a thickness of 76 nm on the front side; deposit a silicon nitride layer with a thickness of 80 nm on the back side;

[0100] (14) Prepare the front and back metal electrodes. The front and back main grids use silver paste, the front sub-grid uses silver-aluminum paste, and the back sub-grid uses silver paste, and then sinter at 810 °C for 50 s.

[0101] Among them, after the test step (4), the sheet resistance of the laser-treated area and the non-laser-treated area is measured, and the results are shown in Table 1.

[0102] Example 2

[0103] The difference between Example 2 and Example 1 is that step (2) is adjusted to oxidize the textured silicon wafer under the conditions of a temperature of 850 °C, an oxygen flow rate of 10000 sccm / min, and a pressure of 600 mbar for 20 min to form a silicon dioxide mask layer.

[0104] Example 3

[0105] The difference between Example 3 and Example 1 is that step (2) is adjusted to oxidize the textured silicon wafer under the conditions of a temperature of 950 °C, an oxygen flow rate of 20000 sccm / min, and a pressure of 900 mbar for 40 min to form a silicon dioxide mask layer.

[0106] Example 4

[0107] Example 4 is different from Example 1 in that step (4) is adjusted as follows: the textured silicon wafer is fed into a furnace tube and deposited for 15 minutes under the conditions of a temperature of 830 °C, a BCl3 flow rate of 300 sccm / min, an oxygen flow rate of 800 sccm / min, a nitrogen flow rate of 1500 sccm / min, and a pressure of 150 mbar. Then, the silicon wafer is heated to 1020 °C and processed for 40 minutes under a pressure of 700 mbar and a nitrogen flow rate of 8000 sccm / min to complete boron diffusion.

[0108] Example 5

[0109] Example 5 is different from Example 1 in that step (4) is adjusted as follows: the textured silicon wafer is fed into a furnace tube and deposited for 25 minutes under the conditions of a temperature of 870 °C, a BCl3 flow rate of 400 sccm / min, an oxygen flow rate of 1000 sccm / min, a nitrogen flow rate of 3000 sccm / min, and a pressure of 200 mbar. Then, the silicon wafer is heated to 1050 °C and processed for 80 minutes under a pressure of 950 mbar and a nitrogen flow rate of 15000 sccm / min to complete boron diffusion.

[0110] Comparative Example 1

[0111] (1) Select an N-type silicon wafer with a size of 182 mm × 182 mm and perform double-sided texturing treatment on the original silicon wafer with a texturing solution at 82 °C. Among them, by volume, the texturing solution includes 23 parts of a KOH solution with a mass percentage of 45%, 5 parts of a texturing additive, and 470 parts of water. The texturing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 2%, a nucleating agent with a mass percentage of 1.2%, sodium benzoate with a mass percentage of 5.0%, and water with a mass percentage of 88.8%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the nucleating agent is sodium citrate;

[0112] (2) Feed the textured silicon wafer into a furnace tube and deposit for 20 minutes under the conditions of a temperature of 860 °C, a BCl3 flow rate of 350 sccm / min, an oxygen flow rate of 850 sccm / min, a nitrogen flow rate of 2000 sccm / min, and a pressure of 180 mbar. Then, heat the silicon wafer to 1040 °C and process for 50 minutes under a pressure of 800 mbar and a nitrogen flow rate of 10000 sccm / min to complete boron diffusion treatment;

[0113] (3) Perform laser doping on the back of the silicon wafer after boron diffusion treatment, and control the laser power to be 62 W;

[0114] (4) Oxidize the laser-doped silicon wafer: Place the silicon wafer in a furnace tube, heat it to 1045 °C, and introduce oxygen with a flow rate of 22000 sccm / min for oxidation treatment for 70 min to complete the boron doping process;

[0115] (5) Perform chain acid pickling and alkaline polishing on the back of the boron-doped silicon wafer to remove the borosilicate glass layer on the back,

[0116] Among them, by volume, the chain acid pickling solution includes 550 parts of hydrofluoric acid with a mass percentage of 49% and 50 parts of water; the temperature of the above alkaline polishing treatment is 75 °C, and the alkaline polishing solution includes 22 parts of KOH solution with a mass percentage of 45%, 4 parts of alkaline polishing additive, and 470 parts of water. Among them, the alkaline polishing additive includes a surfactant with a mass percentage of 2.5%, a defoaming agent with a mass percentage of 2.5%, an antifoaming agent with a mass percentage of 3%, glucose with a mass percentage of 2.5%, sodium polystyrene sulfonate with a mass percentage of 2.5%, and water with a mass percentage of 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is polydimethylsiloxane;

[0117] (6) Perform Low Pressure Chemical Vapor Deposition (LPCVD) on the boron-doped N-type silicon wafer, introduce 300 L of oxygen at a flow rate of 40 L / min, and act at a temperature of 600 °C and a pressure of 850 mbar for 22 min to form a silicon dioxide layer with a thickness of 2.3 nm on the back as the tunneling oxide layer;

[0118] (7) After forming the tunneling oxide layer, at a temperature of 610 °C and a pressure of 27 mbar, introduce silane with a flow rate of 1150 sccm and continue for 1900 s to prepare a polysilicon layer with a thickness of 130 nm;

[0119] (8) After forming the polysilicon layer, deposit the silicon wafer at a temperature of 795 °C, a POCl3 flow rate of 1350 sccm / min, an oxygen flow rate of 650 sccm / min, and a pressure of 150 mbar for 16 min, and then heat the silicon wafer to 885 °C for high-temperature diffusion treatment for 30 min to complete high-concentration doping of the polysilicon passivation layer to obtain a phosphorus-doped polysilicon layer;

[0120] (9) Face the front of the silicon wafer after phosphorus doping and perform chain acid pickling to remove the phosphorus silicate glass layer on the front. Among them, the acid pickling solution in the chain acid pickling uses hydrofluoric acid with a mass percentage of 9%;

[0121] (10) After removing the phosphosilicate glass layer on the front side, the silicon wafer is subjected to alkali etching treatment to remove the polysilicon layer plated around the front side. Among them, by volume, the above alkali etching solution includes 17 parts of a KOH solution with a mass percentage of 45%, 4 parts of an etching additive, and 450 parts of water. Among them, the etching additive includes a surfactant with a mass percentage of 1.5%, a defoaming agent with a mass percentage of 2.5%, an antifoaming agent with a mass percentage of 2%, glucose with a mass percentage of 3%, sodium dodecyl sulfate with a mass percentage of 2%, and water with a mass percentage of 89%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is octylphenol polyoxyethylene ether;

[0122] (11) After removing the polysilicon layer plated around the front side, the front and back sides of the silicon wafer are subjected to chain acid washing to remove the borosilicate glass layer on the front side, the silicon dioxide mask layer, and the phosphosilicate glass layer on the back side. Among them, in the chain acid washing, the acid washing solution uses hydrofluoric acid with a mass percentage of 30%;

[0123] (12) The silicon wafer is subjected to ALD process to deposit aluminum oxide film layers on both sides, and the thickness is maintained at 3.5 nm;

[0124] (13) Deposit a silicon nitride layer with a thickness of 76 nm on the front side; deposit a silicon nitride layer with a thickness of 80 nm on the back side;

[0125] (14) Prepare the front and back metal electrodes. The front and back main grids use silver paste, the front sub-grid uses silver-aluminum paste, and the back sub-grid uses silver paste, and then sinter at 810 °C for 50 s.

[0126] Among them, the sheet resistance of the laser-treated area and the non-laser-treated area is measured after step (4), and the results are shown in Table 1.

[0127] Table 1

[0128]

[0129] Among them, Eta is the photoelectric conversion efficiency, Uoc is the open-circuit voltage, Isc is the short-circuit current, and FF is the fill factor.

[0130] Experiments show that the preparation method of the N-type TOPCon battery provided by the embodiment of the present invention can block the entry of boron atoms by additionally setting a mask oxide layer in the non-grid line area before boron diffusion treatment, and can achieve a lower doping concentration in the non-grid line area, so that its sheet resistance is increased to more than 310 Ω, the open voltage is increased by 2.1 mV, the current is increased by 14 mA, the fill factor is increased by 0.46%, and the photoelectric conversion efficiency is increased by 0.08%.

[0131] In summary, in this embodiment, for the provided method for manufacturing an N-type TOPCon cell, after the texturing treatment, a first mask oxide layer is first formed in the non-grid line region on the front side of the silicon wafer, and then boron diffusion treatment is performed. Among them, due to the presence of the first mask oxide layer in the first region, which is the non-grid line region, boron atoms can be blocked from entering, and the requirement for a low doping concentration can be achieved; while in the second region, which is the grid line region, since it is exposed and there is no oxide layer barrier, boron atoms can be doped at a high concentration, and its sheet resistance can be as low as 60 Ω. This not only achieves the purpose of high and low concentration doping of boron atoms in the grid line region and the non-grid line region, but also avoids damage to the silicon substrate caused by laser doping, and can effectively improve the open voltage and photoelectric conversion efficiency of the cell.

[0132] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0133] The above provides a detailed introduction to an N-type TOPCon cell and its manufacturing method provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A preparation method of an N-type TOPCon battery, characterized in that, Comprising: After texturing the N-type silicon wafer, a first mask oxide layer is formed in a first region on the front side; wherein, the front gate line is projected outside the range of the first region; Perform boron diffusion treatment on the front side of the silicon wafer to form a boron-doped layer in a second region on the front side; wherein, the second region is the front region not covered by the first mask oxide layer; Form a tunneling oxide layer on the back side and form a phosphorus-doped polysilicon layer on the back side; After forming the phosphorus-doped polysilicon layer on the back side, remove the first mask oxide layer, and sequentially form a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer, a front gate line in contact with the boron-doped layer, and a back gate line in contact with the phosphorus-doped polysilicon layer.

2. The preparation method according to claim 1, characterized in that, Forming a first mask oxide layer in a first region on the front side includes: Form a second mask oxide layer covering the front side of the silicon wafer; Perform laser grooving treatment on a third region of the second mask oxide layer, and the third region is opposite to the second region.

3. The preparation method according to claim 2, characterized in that, Forming a second mask oxide layer covering the front side of the silicon wafer includes: Form a silicon dioxide layer with a thickness of 10 - 30 nm on the front side as the second mask oxide layer.

4. The preparation method according to claim 2, characterized in that, Forming a second mask oxide layer covering the front side of the silicon wafer includes: Under the conditions of a temperature of 850 - 950 °C, an oxygen flow rate of 10000 - 20000 sccm / min, and a pressure of 600 - 900 mbar, perform oxidation treatment on the front side of the silicon wafer for 20 - 40 min.

5. The preparation method according to claim 1, characterized in that, Performing boron diffusion treatment on the front side of the silicon wafer includes: Deposit for 15 - 25 min under the conditions of a temperature of 830 - 870 °C, a BCl3 flow rate of 300 - 400 sccm / min, an oxygen flow rate of 800 - 1000 sccm / min, a nitrogen flow rate of 1500 - 3000 sccm / min, and a pressure of 150 - 200 mbar, then raise the temperature of the silicon wafer to 1020 - 1050 °C and perform high-temperature push treatment for 40 - 80 min under the conditions of a nitrogen flow rate of 8000 - 15000 sccm / min and a pressure of 700 - 950 mbar.

6. The preparation method according to claim 1, characterized in that, Removing the first mask oxide layer includes: Perform chain pickling on the front side of the silicon wafer to remove the phosphosilicate glass layer on the front side; After removing the phosphosilicate glass layer on the front side, perform alkali etching treatment on the front side of the silicon wafer to remove the plated polysilicon layer on the front side; After removing the plated polysilicon layer on the front side, perform chain pickling on the front side and the back side of the silicon wafer to remove the borosilicate glass layer on the front side, the first mask oxide layer, and the phosphosilicate glass layer on the back side.

7. The preparation method according to claim 6, characterized in that, During the process of removing the phosphosilicate glass layer on the front side, perform chain pickling with hydrofluoric acid with a mass percentage of 8 - 15%; and / or During the process of removing the plated polysilicon layer on the front side, perform alkali etching treatment on the front side of the silicon wafer with KOH and a texturing additive; And / or During the process of removing the borosilicate glass layer on the front side, the first mask oxide layer, and the phosphosilicate glass layer on the back side, perform the chain pickling with hydrofluoric acid with a mass percentage of 25 - 40%.

8. The preparation method according to claim 1, characterized in that Texturing the N-type silicon wafer includes: The silicon wafer is subjected to double-sided texturing treatment with a texturing solution at 75-85 °C. Among them, by volume, the texturing solution includes 20-25 parts of a KOH solution with a mass percentage of 45%, 3-7 parts of a texturing additive, and 450-500 parts of water. Among them, the texturing additive includes a surfactant with a mass percentage of 2-3.5%, a defoaming agent with a mass percentage of 1-3%, a nucleating agent with a mass percentage of 1-1.5%, sodium benzoate with a mass percentage of 4-6%, and water with a mass percentage of 86-90%.

9. The preparation method according to claim 1, wherein, The projection of the front grid line coincides with the second region range.

10. A type-N TOPCon battery, characterized in that, Prepared by the method according to any one of claims 1 to 9.

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