Preparation method of heterojunction solar cell and heterojunction solar cell

Abstract

The invention provides a preparation method of a heterojunction solar cell and the heterojunction solar cell. The preparation method comprises the following steps: firstly, providing a monocrystalline silicon wafer and carrying out texturing cleaning on the monocrystalline silicon wafer, then respectively forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back surfaces of the monocrystalline silicon wafer, then forming an N-type amorphous / microcrystalline silicon layer on the first intrinsic amorphous silicon layer, then forming a P-type amorphous / microcrystalline silicon layer on the second intrinsic amorphous silicon layer, and finally forming a P-type amorphous / microcrystalline silicon layer on the P-type amorphous / microcrystalline silicon layer on the N-type amorphous / microcrystalline silicon layer. Respectively forming a first transparent conductive film layer and a second transparent conductive film layer on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer, then forming a first anti-reflection film layer and a second anti-reflection film layer on the first transparent conductive film layer and the second transparent conductive film layer, and then forming a first groove and a second groove penetrating through the first anti-reflection film layer and the second anti-reflection film layer; respectively forming a first electrode and a second electrode in the first groove and the second groove through an electroplating process; and finally, carrying out an annealing process. The mass production of the heterojunction solar cell with the anti-reflection film can be realized, and the contact between the metal electrode and the transparent conductive layer is not influenced.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic manufacturing, and particularly to a method for preparing a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] Thin film / crystalline silicon heterojunction solar cells (hereinafter referred to as heterojunction solar cells, also known as HIT or HJT or SHJ solar cells) belong to the third generation of high-efficiency solar cell technologies. They combine the advantages of crystalline silicon and silicon thin films, and have characteristics such as high conversion efficiency and low temperature coefficient. They will gradually replace PERC (Passivated Emitter and Rear Cell) cells and become the mainstream of photovoltaic cells.

[0003] In order to improve the efficiency and reduce the cost of heterojunction solar cells, an antireflection film layer is usually added on indium tin oxide (ITO) doped with tin on the surface of the cell. However, the non-conductive antireflection film layer will affect the electrical connection between the ITO and the electrode. In the prior art, when forming the antireflection film layer on the ITO, a mask is usually used to cover the electrode area, and the antireflection film layer is formed in other areas. Then, the mask is removed and an electroplated electrode is formed in the electrode area through an electroplating process.

[0004] However, the method of covering the electrode area with a mask when depositing the antireflection film layer in the above prior art has problems that are difficult to mass-produce. Specifically: First, when depositing the antireflection film layer, a mask needs to be used to cover each silicon wafer at the same time, and the loading, unloading, and alignment of the mask are very difficult in actual applications; Second, in order to improve the carrier collection efficiency, the pitch of the electrode fine grid lines is only 0.6 mm - 0.9 mm. When the antireflection film layer is formed, the presence of the mask will bring edge effects. The influence range of the edge effects on both sides of each fine grid of the mask is 2 - 6 mm, which will cause the antireflection film layer to not be deposited normally. Even if the deposition is completed, it will not have the antireflection effect and there will be serious color differences.

[0005] Therefore, how to provide a method for preparing a heterojunction solar cell and a heterojunction solar cell to achieve the mass production of heterojunction solar cells with an antireflection film and not affect the contact between the metal electrode and the transparent conductive layer has become an urgent technical problem in the industry. Summary of the Invention

[0006] In view of the above problems in the prior art, the present invention proposes a method for preparing a heterojunction solar cell, characterized in that the preparation method includes the following steps:

[0007] (1). Provide a single crystal silicon wafer and perform texturing cleaning on it;

[0008] (2). Form a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the single-crystalline silicon wafer respectively by the intrinsic PECVD process;

[0009] (3). Form an N-type amorphous / microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front side of the single-crystalline silicon wafer by the N-type PECVD process;

[0010] (4). Form a P-type amorphous / microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the single-crystalline silicon wafer by the P-type PECVD process;

[0011] (5). Form a first transparent conductive film layer and a second transparent conductive film layer on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer respectively by the first PVD process;

[0012] (6). Form a first antireflection film layer and a second antireflection film layer on the first transparent conductive film layer and the second transparent conductive film layer respectively;

[0013] (7). Form a first groove and a second groove passing through the first antireflection film layer and the second antireflection film layer respectively by the laser grooving process;

[0014] (8). Form a first electrode and a second electrode electrically connected to the first transparent conductive film layer and the second transparent conductive film layer respectively in the first groove and the second groove by the electroplating process; and

[0015] (9). Perform an annealing process.

[0016] In one embodiment, both the first antireflection film layer and the second antireflection film layer are silicon oxide, and the thickness ranges of both the first antireflection film layer and the second antireflection film layer are 80 nm - 100 nm.

[0017] In one embodiment, both the first antireflection film layer and the second antireflection film layer are a stack of silicon nitride and silicon oxide, wherein the thickness range of the silicon nitride is 50 nm - 70 nm, and the thickness range of the silicon oxide is 15 nm - 20 nm.

[0018] In a further embodiment, the silicon oxide is deposited and formed by the second PVD process. The radio frequency power range of the second PVD process is 200 W - 3000 W, the ratio range of the process gas Ar / O2 is 1:1 - 1:4, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the second PVD process is a silicon target.

[0019] In a further embodiment, the silicon nitride is formed by deposition through a third PVD process. The radio frequency power of the third PVD process ranges from 200 W to 3000 W, the flow rate of the process gas nitrogen ranges from 50 sccm to 500 sccm, the deposition temperature ranges from 25 °C to 180 °C, the deposition pressure ranges from 0.1 Pa to 2 Pa, and the target of the third PVD process is a silicon target.

[0020] In one embodiment, the annealing temperature in step (9) ranges from 150 °C to 250 °C.

[0021] In one embodiment, the thickness of the N-type amorphous / microcrystalline silicon layer ranges from 10 nm to 30 nm, the thickness of the P-type amorphous / microcrystalline silicon layer ranges from 10 nm to 30 nm, the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer both range from 2 nm to 10 nm, and the thicknesses of the first transparent conductive film layer and the second transparent conductive film layer both range from 10 nm to 100 nm.

[0022] In one embodiment, the materials of the first transparent conductive film layer and the second transparent conductive film layer are each selected from one or more of indium tin oxide, indium tungsten oxide, indium cerium oxide, and aluminum-doped zinc oxide.

[0023] In one embodiment, the first electrode and the second electrode are both copper electrodes. The width of the copper electrode ranges from 10 μm to 50 μm, the height ranges from 5 μm to 30 μm. The widths of the first groove and the second groove are the same as those of the copper electrode, and their height ranges from 70 nm to 100 nm.

[0024] The present invention also provides a heterojunction solar cell formed by the above preparation method. The heterojunction solar cell includes a single crystal silicon wafer. On the front surface of the single crystal silicon wafer, a first intrinsic amorphous silicon layer, an N-type amorphous / microcrystalline silicon layer, a first transparent conductive film layer, a first antireflection film layer, and a first electrode are sequentially formed. On the back surface of the single crystal silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous / microcrystalline silicon layer, a second transparent conductive film layer, a second antireflection film layer, and a second electrode are sequentially formed. First grooves and second grooves are respectively formed through the first antireflection film layer and the second antireflection film layer. The first electrode and the second electrode are respectively formed in the first groove and the second groove and are electrically connected to the first transparent conductive film layer and the second transparent conductive film layer.

[0025] Compared with the prior art where using a mask in the antireflection film layer of a heterojunction solar cell results in abnormal deposition of the antireflection film layer and inability to mass-produce, the method for preparing a heterojunction solar cell of the present invention first provides a monocrystalline silicon wafer and performs texturing cleaning on it. Then, a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are respectively formed on the front and back sides of the monocrystalline silicon wafer through an intrinsic PECVD process. Next, an N-type amorphous / microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the front side of the monocrystalline silicon wafer through an N-type PECVD process. After that, a P-type amorphous / microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer on the back side of the monocrystalline silicon wafer through a P-type PECVD process. Then, a first transparent conductive film layer and a second transparent conductive film layer are respectively formed on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer through a first PVD process. After that, a first antireflection film layer and a second antireflection film layer are respectively formed on the first transparent conductive film layer and the second transparent conductive film layer. Then, a first groove and a second groove passing through the first antireflection film layer and the second antireflection film layer are respectively formed through a laser grooving process. Then, a first electrode and a second electrode electrically connected to the first transparent conductive film layer and the second transparent conductive film layer are respectively formed in the first groove and the second groove through an electroplating process. Finally, an annealing process is performed. The present invention can achieve mass production of a heterojunction solar cell with an antireflection film and does not affect the contact between the metal electrode and the transparent conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] After reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings, the above features and advantages of the present invention can be better understood. In the drawings, the components are not necessarily drawn to scale, and components having similar relevant characteristics or features may have the same or similar reference numerals.

[0027] Figure 1 It is a schematic structural diagram of the composition of an embodiment of the method for preparing a heterojunction solar cell of the present invention.

[0028] Figure 2 It is a schematic structural diagram of the composition of a heterojunction solar cell of the present invention.

[0029] Figure 3 After completing Figure 1 It is a schematic structural diagram of the composition of a heterojunction solar cell after step S150.

[0030] Figure 4 After completing Figure 1 It is a schematic structural diagram of the composition of a heterojunction solar cell after step S150. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The following specific embodiments illustrate the implementation manners of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention will be introduced in combination with preferred embodiments, this does not mean that the features of this invention are limited to this implementation manner. On the contrary, the purpose of introducing the invention in combination with the implementation manner is to cover other alternatives or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, many specific details will be included in the following description. The present invention can also be implemented without using these details. In addition, in order to avoid confusing or obscuring the key points of the present invention, some specific details will be omitted in the description.

[0032] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0033] In addition, the "upper", "lower", "left", "right", "top", "bottom", "horizontal", and "vertical" used in the following description should be understood as the orientations shown in this section and the related drawings. This relative term is only for convenience of description, and it does not mean that the device described needs to be manufactured or operated in a specific orientation, so it should not be understood as a limitation to the present invention.

[0034] It can be understood that although terms such as "first", "second", and "third" can be used here to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first component, region, layer, and / or part discussed below can be called the second component, region, layer, and / or part without departing from some embodiments of the present invention. The amorphous / microcrystalline silicon layer in the P-type amorphous / microcrystalline silicon layer and the N-type amorphous / microcrystalline silicon layer described in the present invention includes an amorphous silicon layer, a microcrystalline silicon layer, and a mixture layer of amorphous silicon and microcrystalline silicon in any proportion.

[0035] See Figure 1 , which is a schematic flow chart of the preparation method of the heterojunction solar cell of the present invention. As Figure 1As shown, the preparation method S10 of the heterojunction solar cell first performs step S100, providing a single-crystalline silicon wafer and performing texturing cleaning on it. In this embodiment, the single-crystalline silicon wafer in step S100 is an N-type single-crystalline silicon wafer, and the N-type single-crystalline silicon wafer can be etched with an alkaline etching solution (such as a sodium hydroxide solution or a potassium hydroxide solution, a mixture of isopropyl alcohol and Na2SiO3) to remove the damaged layer and form a textured surface similar to a pyramid shape.

[0036] Then continue with step S110, forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the single-crystalline silicon wafer respectively through an intrinsic PECVD process. In step S110, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be formed simultaneously on the front and back sides of the N-type single-crystalline silicon wafer respectively through an intrinsic PECVD process carried out in the same PECVD reaction chamber, or the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be formed successively on the front and back sides of the N-type single-crystalline silicon wafer respectively through an intrinsic PECVD process in different PECVD reaction chambers; the thickness ranges of both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are 2nm - 10nm, and the process gas for the intrinsic PECVD process can be silane or a mixed gas of silane and hydrogen.

[0037] Then continue with step S120, forming an N-type amorphous / microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front side of the single-crystalline silicon wafer through an N-type PECVD process. In this embodiment, the process gas for the N-type PECVD process in step S120 can include hydrogen, silane, and phosphine or other gases suitable for N-type doping; the thickness range of the N-type amorphous / microcrystalline silicon layer is 10nm - 30nm.

[0038] Then continue with step S130, forming a P-type amorphous / microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the single-crystalline silicon wafer through a P-type PECVD process. In this embodiment, the process gas for the P-type PECVD process in step S130 includes hydrogen, silane, and a reaction gas of diborane or trimethylboron; the thickness range of the P-type amorphous / microcrystalline silicon layer is 10nm - 30nm.

[0039] Then continue with step S140, forming a first transparent conductive film layer and a second transparent conductive film layer on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer respectively through a first PVD process. In this embodiment, the thickness ranges of both the first transparent conductive film layer and the second transparent conductive film layer are 10nm - 100nm; the materials of both the first transparent conductive film layer and the second transparent conductive film layer are selected from one or more of indium tin oxide, indium tungsten oxide, indium cerium oxide, and aluminum-doped zinc oxide.

[0040] Next, continue with step S150 to form a first anti-reflection film layer and a second anti-reflection film layer on the first transparent conductive film layer and the second transparent conductive film layer respectively. In this embodiment, both the first anti-reflection film layer and the second anti-reflection film layer are silicon oxide, and the thickness range of both the first anti-reflection film layer and the second anti-reflection film layer is 80 nm - 100 nm; the silicon oxide is deposited by a second PVD process, the radio frequency power range of the second PVD process is 200 W - 3000 W, the ratio range of the process gas Ar / O2 is 1:1 - 1:4, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the second PVD process is a silicon target.

[0041] In another embodiment of the present invention, both the first anti-reflection film layer and the second anti-reflection film layer are a stack of silicon nitride and silicon oxide, wherein the thickness range of the silicon nitride is 50 nm - 70 nm, and the thickness range of the silicon oxide is 15 nm - 20 nm; in step S150, first, the silicon oxide is deposited by a second PVD process, the radio frequency power range of the second PVD process is 200 W - 3000 W, the ratio range of the process gas Ar / O2 is 1:1 - 1:4, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the second PVD process is a silicon target; then in step S150, the silicon nitride is deposited by a third PVD process, the radio frequency power range of the third PVD process is 200 W - 3000 W, the flow rate range of the process gas nitrogen is 50 sccm - 500 sccm, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the third PVD process is a silicon target.

[0042] Next, continue with step S160 to form a first groove and a second groove respectively passing through the first anti-reflection film layer and the second anti-reflection film layer by a laser grooving process. In this embodiment, in step S160, for example, a 532 nm green laser can be used for grooving, the pulse width is 10 - 20 ns, the energy density is 1.2 - 1.5 J / cm 2 , and the scanning speed is 30 mm / s; step S160 may further include wet cleaning of the first groove and the second groove.

[0043] Next, continue with step S170 to form a first electrode and a second electrode electrically connected to the first transparent conductive film layer and the second transparent conductive film layer respectively in the first groove and the second groove by an electroplating process. Both the first electrode and the second electrode are copper electrodes, the width range of the copper electrode is 10 μm - 50 μm, the height range is 5 μm - 30 μm, the width of the first groove and the second groove is the same as that of the copper electrode, and its height range is 70 nm - 100 nm.

[0044] Next, continue with step S180 to perform an annealing process. The annealing temperature range in step S180 is 150°C - 250°C, and annealing can be carried out in an annealing furnace.

[0045] See Figure 2 , which shows the compositional structure of a heterojunction solar cell. The heterojunction solar cell is formed by Figure 1 the preparation method of the heterojunction solar cell. As Figure 2 shown, the heterojunction solar cell 2 includes a single-crystalline silicon wafer 20. On the front surface of the single-crystalline silicon wafer 20, a first intrinsic amorphous silicon layer 21, an N-type amorphous / microcrystalline silicon layer 23, a first transparent conductive film layer 25, a first antireflection film layer 27, and a first electrode 29 are sequentially formed. On the back surface of the single-crystalline silicon wafer 20, a second intrinsic amorphous silicon layer 22, a P-type amorphous / microcrystalline silicon layer 24, a second transparent conductive film layer 26, a second antireflection film layer 28, and a second electrode 30 are sequentially formed. A first groove 270 and a second groove 280 are respectively formed through the first antireflection film layer 27 and the second antireflection film layer 28 (see Figure 4 ), and the first electrode 29 and the second electrode 30 are respectively formed in the first groove 270 and the second groove 280 and are electrically connected to the first transparent conductive film layer 26 and the second transparent conductive film layer 27.

[0046] The single-crystalline silicon wafer 20 can be an N-type single-crystalline silicon wafer with a resistivity of 0.5 - 3 Ω·cm, a thickness of 100 - 130 micrometers (μm), and a size of 125mm × 125mm, 156mm × 156mm, 166mm × 166mm, 210mm × 210mm, or 182mm × 210mm, etc., which are commonly used sizes now or general sizes in the future. On the front and back surfaces of the single-crystalline silicon wafer 20, a pyramidal-like textured surface can be formed by an alkaline solution such as sodium hydroxide or potassium hydroxide.

[0047] The thickness ranges of both the first intrinsic amorphous silicon layer 21 and the second intrinsic amorphous silicon layer 22 are 2nm - 10nm, the thickness range of the N-type amorphous / microcrystalline silicon layer 23 is 10nm - 30nm, the thickness range of the P-type amorphous / microcrystalline silicon layer 24 is 10nm - 30nm, and the thickness ranges of both the first transparent conductive film layer 25 and the second transparent conductive film layer 26 are 10nm - 100nm.

[0048] In this embodiment, both the first antireflection film layer 27 and the second antireflection film layer 28 are silicon oxide, and the thickness ranges of both the first antireflection film layer 27 and the second antireflection film layer 28 are 80nm - 100nm.

[0049] In another embodiment, both the first antireflection film layer 27 and the second antireflection film layer 28 are stacked silicon nitride and silicon oxide, wherein the thickness range of the silicon nitride is 50 nm - 70 nm, and the thickness range of the silicon oxide is 15 nm - 20 nm.

[0050] See Figure 3 and Figure 4 , which are respectively schematic diagrams of the compositional structures of the heterojunction solar cell after completing Figure 1 step S150 and step S160. As Figure 3 shown, the first antireflection film layer 27 and the second antireflection film layer 28 are respectively formed on the first transparent conductive film layer 25 and the second transparent conductive film layer 26. As Figure 4 shown, a laser grooving process is performed on the first antireflection film layer 27 and the second antireflection film layer 28, thereby forming a first groove 270 and a second groove 280 that penetrate through the first antireflection film layer 27 and the second antireflection film layer 28. The width range of the first groove 270 and the second groove 280 is 10 μm - 50 μm, and the height range is 3 μm - 28 μm.

[0051] Due to the processing error of the laser grooving process, the first groove 270 and the second groove 280 may slightly extend into the first transparent conductive film layer 25 and the second transparent conductive film layer 26.

[0052] In summary, the preparation method of the heterojunction solar cell of the present invention first provides a single crystal silicon wafer and performs texturing cleaning on it, then respectively forms a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the single crystal silicon wafer through an intrinsic PECVD process, then forms an N-type amorphous / microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front side of the single crystal silicon wafer through an N-type PECVD process, then forms a P-type amorphous / microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the single crystal silicon wafer through a P-type PECVD process, then respectively forms a first transparent conductive film layer and a second transparent conductive film layer on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer through a first PVD process, then respectively form a first antireflection film layer and a second antireflection film layer on the first transparent conductive film layer and the second transparent conductive film layer, then respectively form a first groove and a second groove that penetrate through the first antireflection film layer and the second antireflection film layer through a laser grooving process, then respectively form a first electrode and a second electrode that are electrically connected to the first transparent conductive film layer and the second transparent conductive film layer in the first groove and the second groove through an electroplating process, and finally perform an annealing process. The present invention can achieve mass production of heterojunction solar cells with antireflection films and does not affect the contact between the metal electrodes and the transparent conductive layer.

[0053] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein. The above embodiments are provided for those skilled in the art to implement or use the present invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited by the above embodiments, but should be the maximum scope that conforms to the innovative features mentioned in the claims.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that, The described preparation method includes the following steps: (1) Provide a single-crystalline silicon wafer and perform texturing cleaning on it; (2) Form a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the single-crystalline silicon wafer respectively through an intrinsic PECVD process; (3) Form an N-type amorphous / microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front side of the single-crystalline silicon wafer through an N-type PECVD process; (4) Form a P-type amorphous / microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the single-crystalline silicon wafer through a P-type PECVD process; (5) Form a first transparent conductive film layer and a second transparent conductive film layer on the N-type amorphous / microcrystalline silicon layer and the P-type amorphous / microcrystalline silicon layer respectively through a first PVD process; (6) Form a first antireflection film layer and a second antireflection film layer on the first transparent conductive film layer and the second transparent conductive film layer respectively; (7) Form a first groove and a second groove passing through the first antireflection film layer and the second antireflection film layer respectively through a laser grooving process; (8) Form a first electrode and a second electrode electrically connected to the first transparent conductive film layer and the second transparent conductive film layer respectively in the first groove and the second groove through an electroplating process; And (9) Perform an annealing process.

2. The preparation method according to claim 1, characterized in that, Both the first antireflection film layer and the second antireflection film layer are silicon oxide, and the thickness ranges of both the first antireflection film layer and the second antireflection film layer are 80 nm - 100 nm.

3. The preparation method according to claim 1, characterized in that, Both the first antireflection film layer and the second antireflection film layer are a stack of silicon nitride and silicon oxide, wherein the thickness range of the silicon nitride is 50 nm - 70 nm, and the thickness range of the silicon oxide is 15 nm - 20 nm.

4. The preparation method according to claim 2 or 3, characterized in that The silicon oxide is deposited and formed through a second PVD process. The radio frequency power range of the second PVD process is 200 W - 3000 W, the ratio range of the process gas Ar / O2 is 1:1 - 1:4, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the second PVD process is a silicon target.

5. The preparation method according to claim 3, characterized in that, The silicon nitride is deposited and formed through a third PVD process. The radio frequency power range of the third PVD process is 200 W - 3000 W, the flow rate range of the process gas nitrogen is 50 sccm - 500 sccm, the deposition temperature range is 25 °C to 180 °C, the deposition pressure range is 0.1 Pa - 2 Pa, and the target of the third PVD process is a silicon target.

6. The preparation method according to claim 1, characterized in that, The annealing temperature range in step (9) is 150 °C - 250 °C.

7. The preparation method according to claim 1, wherein The thickness range of the N-type amorphous / microcrystalline silicon layer is 10 nm - 30 nm, the thickness range of the P-type amorphous / microcrystalline silicon layer is 10 nm - 30 nm, the thickness ranges of both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are 2 nm - 10 nm, and the thickness ranges of both the first transparent conductive film layer and the second transparent conductive film layer are 10 nm - 100 nm.

8. The preparation method according to claim 1, characterized in that, The materials of both the first transparent conductive film layer and the second transparent conductive film layer are selected from one or more of indium tin oxide, indium tungsten oxide, indium cerium oxide, and zinc oxide doped with aluminum.

9. The preparation method according to claim 1, characterized in that, The first electrode and the second electrode are both copper electrodes. The width range of the copper electrode is 10 μm - 50 μm, and the height range is 5 μm - 30 μm. The widths of the first groove and the second groove are the same as those of the copper electrode, and the height range is 70 nm - 100 nm.

10. A heterojunction solar cell formed by the preparation method according to claims 1 to 9, characterized in that, The heterojunction solar cell includes a single-crystalline silicon wafer. A first intrinsic amorphous silicon layer, an N-type amorphous / microcrystalline silicon layer, a first transparent conductive film layer, a first antireflection film layer, and a first electrode are sequentially formed on the front surface of the single-crystalline silicon wafer. A second intrinsic amorphous silicon layer, a P-type amorphous / microcrystalline silicon layer, a second transparent conductive film layer, a second antireflection film layer, and a second electrode are sequentially formed on the back surface of the single-crystalline silicon wafer. A first groove and a second groove are respectively formed through the first antireflection film layer and the second antireflection film layer. The first electrode and the second electrode are respectively formed in the first groove and the second groove and are electrically connected to the first transparent conductive film layer and the second transparent conductive film layer.

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