Modem chip and operation method of turbo decoder

Abstract

The invention discloses a modem chip and an operation method of a turbo decoder. The modem chip may include: a turbo decoding circuit configured to: receive a plurality of channel log-likelihood ratios respectively corresponding to a plurality of bits included in a symbol; based on the plurality of channel log-likelihood ratios, generating a plurality of first posterior log-likelihood ratios respectively corresponding to the plurality of bits in the Nth iterative loop, where N is greater than or equal to 1; and generate a first input / output count value by counting a number of first posterior log-likelihood ratios different in sign from a corresponding channel log-likelihood ratio among the plurality of first posterior log-likelihood ratios; and a decoding control circuit configured to stop decoding of the plurality of bits in the turbo decoding circuit based on a first input / output count value being greater than or equal to a first threshold value.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0012665, filed with the Korean Intellectual Property Office on January 26, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices and methods consistent with one or more embodiments relate to a receiver and an operating method of the receiver, and more particularly, to a modem chip including a turbo decoder and an operating method of the turbo decoder, the turbo decoder being configured to reduce power consumed in decoding based on a conversion of log-likelihood ratios. Background Art

[0003] Recently, as wired communication technologies, wireless communication technologies, and technologies related to intelligent devices have rapidly developed, there has been an increasing need for a method of performing low-power decoding with high decoding accuracy on signals received by a receiver in a wireless communication system.

[0004] Generally, a receiver may receive an encoded signal from a transmitter, decode the received signal, and obtain information transmitted by the transmitter. The receiver may repeatedly generate log-likelihood ratios to decode the received signal. When the decoding is correctly performed, the signs of multiple log-likelihood ratios corresponding to multiple bits may be the same. On the other hand, when the decoding is not correctly performed, the signs of multiple log-likelihood ratios corresponding to multiple bits may be different from each other. Therefore, when the signs of multiple corresponding log-likelihood ratios are different, the receiver may not be able to decode multiple bits. Therefore, when decoding failure is expected (i.e., when the signs of the log-likelihood ratios are different), a method of stopping decoding in advance before a predetermined number of times is required to reduce power consumption. Summary of the Invention

[0005] One or more example embodiments provide a modem chip capable of performing low-power decoding based on a sign conversion of log-likelihood ratios and an operating method of a turbo decoder.

[0006] According to one aspect of the present disclosure, a modem chip may include: a turbo decoding circuit configured to: receive a plurality of channel log-likelihood ratios respectively corresponding to a plurality of bits included in a symbol; generate, based on the plurality of channel log-likelihood ratios, a plurality of first posterior log-likelihood ratios respectively corresponding to the plurality of bits in an Nth iteration loop, where N is greater than or equal to 1; and generate a first input / output count value by counting the number of first posterior log-likelihood ratios among the plurality of first posterior log-likelihood ratios that are different from the corresponding channel log-likelihood ratios in terms of sign; and a decoding control circuit configured to: stop decoding the plurality of bits in the turbo decoding circuit based on the first input / output count value being greater than or equal to a first threshold.

[0007] According to one aspect of the present disclosure, a modem chip may include: a turbo decoding circuit configured to: receive a plurality of channel log-likelihood ratios respectively corresponding to a plurality of bits included in a symbol; generate, based on the plurality of channel log-likelihood ratios, a plurality of first extrinsic log-likelihood ratios respectively corresponding to the plurality of bits in an Nth iteration loop, where N is greater than or equal to 1; generate a plurality of second extrinsic log-likelihood ratios respectively corresponding to the plurality of bits in an (N + 1)th iteration loop; and generate a first extrinsic count value by counting the number of second extrinsic log-likelihood ratios among the plurality of second extrinsic log-likelihood ratios that are different from the corresponding first extrinsic log-likelihood ratios in terms of sign; and a decoding control circuit configured to: stop decoding the plurality of bits in the turbo decoding circuit based on the first extrinsic count value being greater than or equal to a first threshold.

[0008] According to one aspect of the present disclosure, a method of operating a turbo decoder may include: receiving a plurality of bits included in a symbol; generating a plurality of channel log-likelihood ratios respectively corresponding to the plurality of bits; generating at least one log-likelihood ratio respectively corresponding to the plurality of bits based on the plurality of channel log-likelihood ratios; generating a count value by counting the number of bits among the plurality of bits for which two corresponding log-likelihood ratios have different signs; and stopping decoding the plurality of bits based on the count value being greater than or equal to a preset threshold, where the two different log-likelihood ratios may include the at least one log-likelihood ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a communication system according to one or more embodiments; Figure 2 is a block diagram of a transmitter; Figure 3 is a block diagram of a receiver according to one or more embodiments; Figures 4A to 4C is a block diagram of a turbo decoder according to one or more embodiments; Figure 5 is a block diagram of an external symbol comparator according to one or more embodiments; Figure 6 is a table showing symbol conversion of an external log-likelihood ratio according to one or more embodiments; Figure 7A and Figure 7B is a block diagram of a turbo decoder according to one or more embodiments; Figure 8 is a table showing symbol conversion of a posterior log-likelihood ratio with respect to a symbol of a channel log-likelihood ratio according to one or more embodiments; Figure 9 is a block diagram of a turbo decoder according to one or more embodiments; Figure 10 is a flowchart of an operation method of a turbo decoder according to one or more embodiments; and Figure 11 is a block diagram of a wireless communication device according to one or more embodiments. Detailed Description

[0010] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0011] In the following description, even in different drawings, the same reference numerals are used for the same elements. Matters defined in the description (such as detailed configurations and elements) are provided to help a comprehensive understanding of example embodiments. However, it is clear that example embodiments can be practiced without those specific defined matters. In addition, since well-known functions or configurations would obscure the description with unnecessary detail, they are not described in detail.

[0012] Figure 1 is a block diagram of a communication system according to one or more embodiments. Referring to Figure 1 , communication system 10 may include a transmitter (Tx) 100 and a receiver (Rx) 200 that perform wireless communication through a multiple-input multiple-output (MIMO) channel 300.

[0013] Communication system 10 can be any system including MIMO channel 300. In some embodiments, communication system 10 may include, but is not limited to, wireless communication systems (such as 5th generation (5G) wireless systems, long term evolution (LTE) systems, and WiFi). In some embodiments, communication system 10 may include wired communication systems (such as storage systems, network systems, etc.). Hereinafter, communication system 10 is mainly described as a wireless communication system, but is not limited thereto.

[0014] For example, the transmitter 100 may be a base station or a component included in a base station. A base station may refer to a fixed station that communicates with terminals and / or other base stations, and may transmit / receive data and / or control information by communicating with terminals and / or other base stations. A base station may be referred to as a Node B, an evolved Node B (eNB), a base transceiver system (BTS), and an access point (AP).

[0015] For example, the receiver 200 may be a terminal or a component provided in a terminal. A terminal as a wireless communication device may refer to various devices capable of transmitting / receiving data and / or control information by communicating with the transmitter 100. For example, a terminal may be referred to as a user equipment, a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), a wireless device, a portable device, etc.

[0016] The wireless communication network between the transmitter 100 and the receiver 200 may support communication between multiple users by sharing available network resources. For example, in a wireless communication network, information may be transmitted in various ways such as code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), etc.

[0017] The transmitter 100 may be provided with a plurality of transmit antennas 102-1 to 102-M (hereinafter, M is a positive integer), and may transmit symbols x1 to xM through the plurality of transmit antennas 102-1 to 102-M, respectively. In addition, the receiver 200 may be provided with a plurality of receive antennas 202-1 to 202-N (hereinafter, N is a positive integer), and may receive a plurality of symbols y1 to yN through the plurality of receive antennas 202-1 to 202-N, respectively.

[0018] For example, the symbol vector "x" transmitted from the transmitter 100 is represented by and the symbol vector "y" received by the receiver 200 may be expressed as Equation 1 below.

[0019] [Equation 1]

[0020] In Equation 1, hi,j may represent the effective channel gain between the jth (j is an integer from 1 to M) transmit antenna and the ith (i is an integer from 1 to N) receive antenna, and xj may represent the transmitted symbol from the jth transmit antenna (or transmit layer).

[0021] The transmitted symbol xj can be one of the constellation points. The constellation points can refer to the points on the complex plane that the transmitter 100 uses to map the transmitted signal. The number and position of the constellation points on the complex plane can vary according to the method of modulating the transmitted signal. For example, when the transmitter 100 uses the quadrature phase shift keying (QPSK) method to modulate the transmitted signal, one constellation point can be located in each quadrant of the complex plane. That is, four constellation points can be used to modulate the transmitted signal. The transmitter 100 that modulates the transmitted signal using the QPSK method can map the transmitted signal to one of the four constellation points and transmit it to the receiver 200. However, the modulation method of the transmitter 100 is not limited to this. It can be easily understood that the transmitted signal can be modulated by using 16 quadrature amplitude modulation (QAM), 64QAM, 256QAM, and 1024QAM methods.

[0022] In addition, in Equation 1, ni represents the additive white Gaussian noise (AWGN) from the i-th receiving antenna, and ni can have the power (or variance). The AWGN can also include interference signals. In the communication system 10, the noise from the receiving antenna can be considered together with the influence of the interference signals. However, hereinafter, it is assumed that the power of the AWGN for each receiving antenna is the same and not spatially correlated.

[0023] The receiver 200 can include a turbo decoder 230 for decoding multiple bits. The turbo decoder 230 can generate a log-likelihood ratio (LLR) for each of the multiple bits based on the similarity between multiple candidate points and the received signal. For example, the turbo decoder 230 can calculate the Euclidean distance between the multiple candidate points and the received signal and calculate the log-likelihood ratio based on the Euclidean distance. The multiple candidate points can be determined according to the modulation method of the transmitter 100. For example, when the transmitter 100 uses the QPSK method to modulate the transmitted signal and the symbols are transmitted from two transmitting antennas to one receiving antenna, there can be 16 candidate points. The turbo decoder 230 can calculate the log-likelihood ratio based on the Euclidean distance between the multiple candidate points and the received symbol. For example, when the Euclidean distance between the candidate point corresponding to 0 among the multiple candidate points and the received symbol is less than the Euclidean distance between the candidate point corresponding to 1 among the multiple candidate points and the received symbol, the log-likelihood ratio can be negative.

[0024] The receiver 200 may decode the corresponding bit based on the log-likelihood ratio. As described above, when the log-likelihood ratio is negative, the corresponding bit may be decoded as '0' among '1' and '0'. When the log-likelihood ratio is positive, the corresponding bit may be decoded as '1' among '1' and '0'. However, this is merely an example, and one or more embodiments are not limited thereto. The log-likelihood ratio may refer to a soft value indicating the probability that the received signal will be decoded as '0' or '1'. Thus, the turbo decoder 230 may iteratively refine the log-likelihood ratio by decoding the received signal via a plurality of iterative loops until the log-likelihood ratio drops below a preset threshold, indicating a confident decoding decision based on the last-generated log-likelihood ratio. The turbo decoder 230 may decode the received signal based on the last-generated log-likelihood ratio. The log-likelihood ratio according to an embodiment may be considered a general term including a channel log-likelihood ratio (channel LLR), a posterior log-likelihood ratio (posterior LLR), a prior log-likelihood ratio (prior LLR), and an extrinsic log-likelihood ratio (extrinsic LLR). More details regarding the turbo decoder 230 and the log-likelihood ratio are described below.

[0025] The receiver 200 according to one or more embodiments may generate an extrinsic count value by counting the number of bits among the plurality of bits included in a symbol, for which the sign of the first extrinsic LLR generated in the Nth (hereinafter, N is an integer greater than or equal to 1 and is independent of the number of antennas in the receiver 200) iterative loop is different from the sign of the second extrinsic LLR generated in the N+1th iterative loop, and may determine whether to stop decoding early based on the extrinsic count value. Thus, when decoding failure is expected based on the extrinsic count value, the receiver 200 may reduce the power consumed in decoding by stopping decoding early. Here, the count value includes the extrinsic count value and an input / output (I / O) count value which will be described below. Details in this regard are described below.

[0026] The receiver 200 according to one or more embodiments may generate an input / output count value by counting the number of bits among the plurality of bits included in a symbol, for which the sign of the corresponding channel LLR is different from the sign of the corresponding posterior LLR, and may determine whether to stop decoding early based on the input / output count value. Thus, when decoding failure is expected based on the input / output count value, the receiver 200 may reduce the power consumed in decoding by stopping decoding early.

[0027] The receiver 200 according to another embodiment may determine whether to stop decoding early based on the foregoing extrinsic count value and input / output count value. Thus, when decoding failure is expected based on the extrinsic count value and the input / output count value, the receiver 200 may reduce the power consumed in decoding by stopping decoding early.

[0028] Figure 2 is a block diagram of a transmitter according to one or more embodiments of the present disclosure.

[0029] Figure 2 may show, for example, components included in Figure 1 transmitter 100.

[0030] Referring to Figure 2 , transmitter 100 may include a serial-to-parallel (S / P) converter 110, a plurality of cyclic redundancy check (CRC) units 120_1 to 120_M (CRC_1 to CRC_M), a plurality of forward error correction (FEC) encoders 130_1 to 130_M (FEC encoder_1 to FEC encoder_M), a plurality of rate matching units 140_1 to 140_M (rate matching_1 to rate matching_M), a plurality of modulators 150_1 to 150_M (modulator_1 to modulator_M), a plurality of layer mapping units 160_1 to 160_M (layer mapping_1 to layer mapping_M), a precoding unit 170, a plurality of inverse fast Fourier transform (IFFT) units 180_1 to 180_M (IFFT_1 to IFFT_M), and a plurality of transmit antennas 102-1 to 102-M.

[0031] First, an information bit stream BS to be transmitted may be input to the S / P converter 110. The S / P converter 110 may generate a plurality of information bit streams by performing parallel conversion on the input information bit stream BS, and may output the plurality of information bit streams to the CRC units 120_1 to 120_M, respectively. For example, the S / P converter 110 may perform parallel conversion on the information bit stream BS and output it as a codeword (or transport block) that is an input unit for channel decoding.

[0032] Each of the plurality of CRC units 120_1 to 120_M may perform a CRC operation on the parallel-converted information bit stream, and may output a signal on which the CRC operation has been performed to each of the FEC encoders 130_1 to 130_M. For example, the plurality of CRC units 120_1 to 120_M may perform a CRC operation to detect errors that occur during transmission.

[0033] The plurality of FEC encoders 130_1 to 130_M may use FEC techniques to correct errors caused by noise in the signals received from the plurality of CRC units 120_1 to 120_M using error correction codes. For example, in a wireless communication system, FEC methods (such as convolutional codes, turbo codes, low-density parity-check (LDPC) codes, and polar codes) may be used. A wireless communication system according to one or more embodiments will be described below assuming the use of turbo codes.

[0034] Multiple rate matching units 140_1 to 140_M can perform rate matching operations on the signals output from multiple FEC encoders 130_1 to 130_M based on a preset rate matching method, and can output the signals on which the rate matching operations have been performed to multiple modulators 150_1 to 150_M. Through the rate matching operations, multiple rate matching units 140_1 to 140_M can match the encoded bits with the number of modulation symbols assigned to the user.

[0035] Multiple modulators 150_1 to 150_M can perform modulation operations on the rate-matched signals based on a preset modulation method, and can output the signals on which the modulation operations have been performed to multiple layer mapping units 160_1 to 160_M. For example, multiple modulators 150_1 to 150_M can map the rate-matched signals to constellation points. Multiple layer mapping units 160_1 to 160_M can allocate the modulated signals to match the number of input layers of the precoding unit 170.

[0036] The precoding unit 170 can perform precoding operations on the signals output from the layer mapping units 160_1 to 160_M respectively based on a preset precoding method, and can output them to IFFT units 180_1 to 180_M. For example, the precoding method can be generated based on the feedback information received by the transmitter 100. Multiple IFFT units 180_1 to 180_M can convert the signals transmitted for each transmit antenna in the frequency domain output from the precoding unit 170 to the time domain through IFFT, and can transmit the converted transmitted signals s1 to sM to transmit antennas 102-1 to 102-M.

[0037] Figure 3 is a block diagram of a receiver according to one or more embodiments.

[0038] Figure 3 may show, for example, components included in Figure 1 the receiver 200.

[0039] Referring to Figure 3 FIG. [FIGURE NUMBER], the receiver 200 may include multiple receive antennas 202-1 to 202-N, multiple fast Fourier transform (FFT) units 270_1 to 270_N (FFT_1 to FFT_N), an effective channel generation unit 260, a MIMO demodulator 250, multiple rate dematching units 240_1 to 240_N (rate dematching_1 to rate dematching_N), a turbo decoder 230, multiple CRC units 220_1 to 220_N (CRC_1 to CRC_N), a parallel-to-serial (P / S) converter 210, and a processor 280.

[0040] The signals rs1 to rsN received through the multiple receiving antennas 202-1 to 202-N can be respectively input into the multiple FFT units 270_1 to 270_N. The multiple FFT units 270_1 to 270_N can perform FFT operations on the signals rs1 to rsN. That is, the multiple FFT units 270_1 to 270_N can convert the time-domain signals received by each antenna to the frequency domain through FFT, and can send the converted signals in the frequency domain to the effective channel generation unit 260.

[0041] The effective channel generation unit 260 can reflect the influence of the precoding method applied by the transmitter 100 on the received signals rs1 to rsM converted to the frequency domain, and can output it to the MIMO demodulator 250.

[0042] The MIMO demodulator 250 can perform a demodulation operation on the signal output from the effective channel generation unit 260 based on a demodulation method corresponding to the modulation method used in the transmitter 100. The MIMO demodulator 250 can use the effective channel generated from the effective channel generation unit 260 and the received signals rs1 to rsN to generate the channel LLR LLR_CH. The MIMO demodulator 250 can generate multiple channel LLRs LLR_CH corresponding to multiple bits respectively, and can provide the multiple channel LLRs LLR_CH to the turbo decoder 230.

[0043] The multiple rate dematching units 240_1 to 240_N can perform rate dematching operations on the signal output from the MIMO demodulator 250 based on a rate dematching method corresponding to the rate matching method used in the transmitter 100.

[0044] The turbo decoder 230 can perform a decoding operation on the signal output from the multiple rate dematching units 240_1 to 240_N based on a FEC decoding method corresponding to the FEC coding method used in the transmitter 100 described with reference to Figure 2 The turbo decoder 230 can perform a decoding operation on the signal output from the multiple rate dematching units 240_1 to 240_N based on a FEC decoding method corresponding to the FEC coding method used in the transmitter 100 described with reference to

[0045] The multiple CRC units 220_1 to 220_N can perform CRC operations on the signal output from the turbo decoder 230, and can output the signal on which the CRC operation has been performed to the P / S converter 210. The P / S converter 210 can convert the signals output in parallel from the multiple CRC units 220_1 to 220_N into a serial signal, and then continue to output the serial signal.

[0046] The turbo decoder 230 can decode the received signal in units of code blocks including multiple bits. The turbo decoder 230 can perform decoding based on multiple external LLRs corresponding to the multiple bits included in the code block respectively.

[0047] According to one or more embodiments, the turbo decoder 230 may receive a plurality of channel LLRs LLR_CH corresponding to a plurality of bits, respectively, from the MIMO demodulator 250, and may generate a plurality of posterior LLRs corresponding to the plurality of bits, respectively, based on the plurality of channel LLRs LLR_CH. The turbo decoder 230 may generate an extrinsic LLR based on the difference between the posterior LLR and the prior LLR. Hereinafter, the turbo decoder 230 may adjust the extrinsic LLR. The adjusted extrinsic LLR as the prior LLR may be used to generate the posterior LLR. The turbo decoder 230 may generate the extrinsic LLR as a soft value. The turbo decoder 230 may generate a plurality of extrinsic LLRs as soft values for the plurality of bits included in the code block, respectively. Specifically, the extrinsic LLRs generated for each of the plurality of bits in the previous iteration loop may affect the generation of the extrinsic LLR corresponding to the current iteration loop. More details are described below with reference to Figure 4A for more details.

[0048] When the signs of the extrinsic LLRs generated in the Nth iteration loop are the same as the signs of the extrinsic LLRs generated in the N+1th iteration loop, the receiver 200 may determine that the decoding for the corresponding bit is successful. In this case, the receiver 200 may generate the extrinsic LLR by repeating the loop a predetermined number of times, and may decode the corresponding bit based on the final extrinsic LLR.

[0049] On the other hand, when the signs of the extrinsic LLRs generated in the Nth iteration loop are different from the signs of the extrinsic LLRs generated in the N+1th iteration loop, the receiver 200 may determine that the decoding for the corresponding bit is inappropriate. In this case, although the receiver 200 generates the extrinsic LLR by repeating the loop a predetermined number of times, the probability of decoding failure is relatively high. In other words, when the signs of the extrinsic LLRs change as the loop is repeated (i.e., when the sign transitions), it is difficult to trust the decoding result.

[0050] When the signal-to-noise ratio (SNR) of the received signal is low, the signs of the extrinsic LLRs for each of the plurality of bits included in the corresponding code block may transition, so that the probability of decoding failure of the code block may be high. The receiver 200 according to one or more embodiments may generate a count value CV by counting the number of bits corresponding to the extrinsic LLRs with sign transitions. When the count value CV is greater than a predetermined threshold, the receiver 200 may determine that the decoding for the code block will fail, and may stop decoding the plurality of bits included in the code block in advance.

[0051] The turbo decoder 230 was described above as generating a count value CV based on a symbol conversion of external LLRs. However, according to one or more embodiments, the turbo decoder 230 may generate the count value CV based on a symbol conversion of posterior LLRs. Additionally, according to another embodiment, the turbo decoder 230 may generate the count value CV based on both a symbol conversion of external LLRs and a symbol conversion of posterior LLRs.

[0052] According to one or more embodiments, the turbo decoder 230 may provide the count value CV to the processor 280. According to one or more embodiments, the processor 280 may generate an early stop signal SC for prematurely stopping the decoding of the turbo decoder 230 based on the count value CV. The processor 280 may generate the early stop signal SC by comparing the count value CV with a predetermined threshold. The threshold may be determined based on the number of bits or the count value CV generated in a previous iteration loop. For example, the threshold may be less than the number of bits. Additionally, the threshold may be less than the count value CV generated in a previous iteration loop. When the count value CV is greater than the threshold, the processor 280 may generate the early stop signal SC and output the early stop signal to the turbo decoder 230. The turbo decoder 230 may prematurely stop the decoding operation based on the early stop signal SC. As described above, when the number of bits of the symbol conversion of the corresponding log-likelihood ratio is greater than or equal to the threshold, the receiver 200 may determine that the decoding of the corresponding code block has a high probability of failure. Therefore, the receiver 200 may reduce power by prematurely stopping the decoding based on the early stop signal CS without repeating the loop a predetermined number of times for the corresponding code block.

[0053] In Figure 3 for ease of explanation, the processor 280 is shown as being located external to the turbo decoder 230, but is not limited thereto. The processor 280 may be included in the turbo decoder 230. For example, the turbo decoder 230 may include a decoding control circuit capable of performing the operations of the processor 280 described above with reference to Figure 3

[0054] When the decoding of the turbo decoder 230 for a code block is prematurely stopped, according to one or more embodiments, the receiver 200 may request the transmitter ( Figure 2 100 in

[0055] to retransmit the corresponding code block. The receiver 200 may perform decoding on the retransmitted code block as described above. Figure 3 With reference to Figure 3The turbo decoding circuit for the operation of the described turbo decoder 230 and the decoding control circuit for the operation of the processor 280 described above. As referred to Figure 3 The decoding control circuit for the operation of the described processor 280. As referred to Figure 3 As described, the turbo decoder 230 and the processor 280 are described below assuming that the turbo decoder 230 and the processor 280 are independent components. However, as described above, the circuits performing each operation can be designed on one chip.

[0056] Figures 4A to 4C is a block diagram of a turbo decoder according to one or more embodiments.

[0057] Figures 4A to 4C The turbo decoder 230a can be the turbo decoder 230 described above with reference to Figure 3 and the overlapping description in this regard can be omitted.

[0058] With reference to Figures 4A to 4C , the turbo decoder 230a can include a first decoder 231, a second decoder 235, a first adder 232, a second adder 236, a first interleaver 233, a second interleaver 239, a first external symbol comparator 2300, a second external symbol comparator 2310, and a deinterleaver 237.

[0059] The turbo decoder 230a according to one or more embodiments can generate an external LLR by repeatedly iterating through the operations of the components, which is described below with reference to Figures 4A to 4C the description. Figure 4A is a diagram explaining the Nth iteration cycle of the turbo decoder 230a according to one or more embodiments, Figure 4B is a diagram explaining the (N + 1)th iteration cycle of the turbo decoder 230a according to one or more embodiments, and Figure 4C is a diagram explaining the (N + 2)th iteration cycle of the turbo decoder 230a according to one or more embodiments. Since Figures 4A to 4C are diagrams of consecutive cycles, the overlapping description given with reference to Figures 4A to 4C can be omitted.

[0060] With reference to Figures 4A to 4C, the turbo decoder 230a may include a first decoder 231 and a second decoder 235. The first decoder 231 and the second decoder 235 may receive the channel LLR LLR_CH. The first decoder 231 and the second decoder 235 may generate posterior LLRs (e.g., LLR_POS1 and LLR_POS2) corresponding to a plurality of bits respectively based on the channel LLR LLR_CH. The posterior LLRs (e.g., LLR_POS1 and LLR_POS2) output from each of the first decoder 231 and the second decoder 235 may be values representing the error probabilities of each decoded bit. As Figures 4A to 4C shown, when the loop is repeated, the extrinsic LLRs (e.g., LLR_EX1 and LLR_EX2) respectively generated from the first decoder 231 and the second decoder 235 may be exchanged. Since the posterior LLRs (e.g., LLR_POS1 and LLR_POS2) and the extrinsic LLRs (e.g., LLR_EX1 and LLR_EX2) respectively generated from two different decoders (i.e., the first decoder 231 and the second decoder 235) are exchanged with each other, the error correction performance can be improved.

[0061] The first decoder 231 and the second decoder 235 may be soft input soft output (SISO) decoders. For example, referring to Figure 4A and Figure 4B , the first decoder 231 may receive a third prior LLR LLR_PRI3 generated based on a second posterior LLR LLR_POS2 which is a soft value generated from the second decoder 235. In addition, the first decoder 231 may receive the channel LLR LLR_CH corresponding to each of the plurality of bits. The first decoder 231 may generate a third posterior LLR LLR_POS3 as a soft value based on the received third prior LLR LLR_PRI3 and the channel LLR LLR_CH.

[0062] Referring to Figure 4A , the first adder 232 may receive the first posterior LLR LLR_POS1 from the first decoder 231, and may receive the first prior LLR LLR_PRI1 from the second extrinsic symbol comparator 2310. The first adder 232 may generate a first extrinsic LLR LLR_EX1 corresponding to the difference between the first posterior LLR LLR_POS1 and the first prior LLR LLR_PRI1. Figure 4A illustrates the operation of the turbo decoder 230a in the first iteration loop. Therefore, when N is 1, since there is no first prior LLR LLR_PRI1 generated in the previous iteration loop, the first prior LLR LLR_PRI1 may be 0.

[0063] The first interleaver 233 may receive the first extrinsic LLR LLR_EX1 from the first adder 232. The first interleaver 233 may interleave the first extrinsic LLR LLR_EX1 to generate the interleaved first extrinsic LLR LLR_EX1. Interleaving may refer to an operation of rearranging bits to enhance noise resistance. For ease of explanation, the log-likelihood ratios before and after interleaving are equivalently referred to as the first extrinsic LLR LLR_EX1. However, hereinafter, "extrinsic LLR" is described assuming that the extrinsic LLR is the interleaved first extrinsic LLR LLR_EX1.

[0064] The first extrinsic symbol comparator 2300 may receive the first extrinsic LLR LLR_EX1. The first extrinsic symbol comparator 2300 may adjust the magnitude of the first extrinsic LLR LLR_EX1 to generate a second prior LLR LLR_PRI2. The magnitude of the second prior LLR LLR_PRI2 may be smaller than the magnitude of the first extrinsic LLR LLR_EX1. The first extrinsic symbol comparator 2300 may provide the second prior LLR LLR_PRI2 to the second decoder 235. The second decoder 235 may generate a second posterior LLR LLR_POS2 based on the second prior LLR LLR_PRI2, and the second prior LLR LLR_PRI2 is generated based on the first posterior LLR LLR_POS1 generated from the first decoder 231. Thus, as described above, since the posterior LLRs (or extrinsic LLRs) generated by two different decoders (i.e., the first decoder 231 and the second decoder 235) are exchanged with each other, the error correction performance may be improved.

[0065] The deinterleaver 237 may perform a deinterleaving operation corresponding to the operation of the first interleaver 233 described above. The deinterleaver 237 may generate the extrinsic LLR LLR_EX by performing a deinterleaving operation on the extrinsic LLR LLR_EX.

[0066] According to one or more embodiments, the first extrinsic symbol comparator 2300 may store the sign of the first extrinsic LLR LLR_EX1 in addition to adjusting the first extrinsic LLR LLR_EX1. Specifically, the first extrinsic symbol comparator 2300 may store the sign of each of the plurality of first extrinsic LLRs LLR_EX1 corresponding to the plurality of bits included in the code block. The first extrinsic symbol comparator 2300 may refer to the following Figure 4BIn the (N + 1)-th iteration loop (i.e., the next iteration loop) of the description, the sign of the third extrinsic LLR LLR_EX3 generated is compared with the sign of the stored first extrinsic LLR LLR_EX1. The first extrinsic symbol comparator 2300 can generate a first extrinsic count value ECV_1 by counting the number of bits among a plurality of bits for which the sign of the first extrinsic LLR LLR_EX1 is different from the sign of the third extrinsic LLR LLR_EX3. According to one or more embodiments, a receiver (e.g., Figure 3 the processor 280 shown in

[0067] can determine whether to stop decoding early based on a comparison between the first extrinsic count value ECV_1 and a predetermined first threshold (or referred to as a first predetermined threshold). The first threshold can be determined based on the number of bits or an extrinsic count value generated in a previous iteration loop.

[0068] Referring to the descriptions above and below, the operations of each of the second decoder 235, the second adder 236, the second interleaver 239, and the second extrinsic symbol comparator 2310 can be understood from the foregoing operations of each of the first decoder 231, the first adder 232, the first interleaver 233, and the first extrinsic symbol comparator 2300. For example, the second extrinsic symbol comparator 2310 can store the sign of each of a plurality of second extrinsic LLRs LLR_EX2.

[0068] Referring to Figure 4B , the first decoder 231 can generate a plurality of third posterior LLRs LLR_POS3 based on a plurality of channel LLRs LLR_CH corresponding respectively to a plurality of bits included in a code block and a third prior LLR LLR_PRI3 corresponding respectively to the plurality of bits included in the code block. The first adder 232 can generate a plurality of third extrinsic LLRs LLR_EX3 based on the difference between the plurality of third posterior LLRs LLR_POS3 and the plurality of third prior LLRs LLR_PRI3.

[0069] A first external symbol comparator 2300 according to one or more embodiments may receive third external LLRs LLR_EX3 corresponding to a plurality of bits respectively. As described above, the first external symbol comparator 2300 may generate a first external count value ECV_1 by counting the number of bits among the plurality of bits for which the sign of the first external LLR LLR_EX1 is different from the sign of the third external LLR LLR_EX3. A receiver according to one or more embodiments may determine whether to stop decoding early based on the first external count value ECV_1 and a predetermined first threshold. The first threshold may be determined based on the external count value generated by the first external symbol comparator 2300 in a previous iteration loop. For example, the first threshold may be equal to or less than the external count value generated in the previous iteration loop. Additionally, the first threshold may be determined based on the number of bits included in the code block. For example, the first threshold may be less than the number of bits.

[0070] Figure 4B Illustrates the operation of the turbo decoder 230a in the second iteration loop. Thus, when N is 1, there is no external count value generated in the previous iteration loop. Thus, the first threshold may be determined based on the number of bits. For example, the first threshold may be determined to be a value equal to or less than half of the number of bits.

[0071] The first external symbol comparator 2300 may store the signs of the plurality of third external LLRs LLR_EX3. Additionally, the first external symbol comparator 2300 may adjust the third external LLRs LLR_EX3 to generate fourth prior LLRs LLR_PRI4 that are less than the third external LLRs LLR_EX3.

[0072] Refer to Figure 4B Similar to the operation of the first external symbol comparator 2300 described above, a second external symbol comparator 2310 according to one or more embodiments may generate a second external count value ECV_2. Specifically, the second external symbol comparator 2310 may generate the second external count value ECV_2 by counting the number of bits among the plurality of bits for which the sign of the second external LLR LLR_EX2 is different from the sign of the fourth external LLR LLR_EX4. A receiver according to one or more embodiments may determine whether to stop decoding the turbo decoder 230a early based on the second external count value ECV_2 and a predetermined second threshold. The second threshold may be determined based on the external count value generated by the second external symbol comparator 2310 in a previous iteration loop. For example, the second threshold may be less than or equal to the external count value generated in the previous iteration loop. Additionally, the second threshold may be determined based on the number of bits included in the code block. For example, the second threshold may be less than the number of bits.

[0073] Figure 4BShows the operation of the turbo decoder 230a in the second iteration loop. Similar to above, when N is 1, there is no extrinsic count value generated in the previous iteration loop. Therefore, the second threshold can be determined based on the number of bits.

[0074] Referring to Figure 4C , the first decoder 231 can generate a plurality of fifth posterior LLRs LLR_POS5 based on a plurality of channel LLRs LLR_CH corresponding to a plurality of bits included in the code block and a fifth prior LLR LLR_PRI5 corresponding to the plurality of bits included in the code block (see Figure 4B ). In one example embodiment, the first decoder 231 can receive a seventh prior LLR LLR_PRI7 generated based on a sixth posterior LLR LLR_POS6 that is a soft value generated from the second decoder 235. The first adder 232 can generate a plurality of fifth extrinsic LLRs LLR_EX5 based on the difference between the plurality of fifth posterior LLRs LLR_POS5 and the plurality of fifth prior LLRs LLR_PRI5.

[0075] The first extrinsic symbol comparator 2300 according to one or more embodiments can receive the fifth extrinsic LLRs LLR_EX5 corresponding to the plurality of bits, respectively. As described above, the first extrinsic symbol comparator 2300 can generate a third extrinsic count value ECV_3 by counting the number of bits among the plurality of bits for which the sign of the corresponding third extrinsic LLR LLR_EX3 is different from the sign of the corresponding fifth extrinsic LLR LLR_EX5. A receiver according to one or more embodiments can determine whether to prematurely stop decoding of the turbo decoder 230a based on the third extrinsic count value ECV_3 and a predetermined third threshold. The third threshold can be determined based on the extrinsic count value (i.e., the first extrinsic count value) generated by the first extrinsic symbol comparator 2300 in the previous iteration loop. For example, the third threshold can be less than or equal to the first extrinsic count value generated in the previous iteration loop. Additionally, the third threshold can be determined based on the number of bits included in the code block.

[0076] The first extrinsic symbol comparator 2300 can store the signs of the plurality of fifth extrinsic LLRs LLR_EX5. Additionally, similar to above, the first extrinsic symbol comparator 2300 can adjust the fifth extrinsic LLRs LLR_EX5 to generate a sixth prior LLR LLR_PRI6 that is less than the fifth extrinsic LLR LLR_EX5.

[0077] Referring to Figure 4C, similar to the operation of the first external symbol comparator 2300 described above, the second external symbol comparator 2310 according to one or more embodiments may generate a fourth external count value ECV_4. Specifically, the second external symbol comparator 2310 may generate the fourth external count value ECV_4 by counting the number of bits among a plurality of bits for which the corresponding fourth external LLR LLR_EX4 symbol is different from the corresponding sixth external LLR LLR_EX6 symbol. A receiver according to one or more embodiments may determine whether to prematurely stop the decoding of the turbo decoder 230a based on a comparison between the fourth external count value ECV_4 and a predetermined fourth threshold. The fourth threshold may be determined based on an external count value (i.e., the second external count value) generated by the second external symbol comparator 2310 in a previous iteration loop. For example, the fourth threshold may be less than or equal to the second external count value generated in the previous iteration loop. Additionally, the fourth threshold may be determined based on the number of bits included in the code block.

[0078] As described above with reference to Figures 4A to 4B the first external symbol comparator 2300 and the second external symbol comparator 2310 have been described as simultaneously storing and comparing the symbols of the external LLRs and adjusting the external LLRs, but this is for ease of explanation and one or more embodiments are not limited thereto. For example, the first external symbol comparator 2300 and the second external symbol comparator 2310 may refer to configurations for storing and comparing the symbols of the external LLRs, and the turbo decoder 230a may further include a separate configuration for adjusting the external LLRs.

[0079] As described above with reference to Figure 3 the components included in the turbo decoder 230a may be configured as a circuit and may be referred to as a turbo decoding circuit. Additionally, as described above, those skilled in the art will understand that although a decoding stop circuit or a processor ( Figures 4A to 4C 280 in Figure 3 ) is not shown, the turbo decoding circuit and the decoding stop circuit may be implemented on a single modem chip.

[0080] Figure 5 is a block diagram of an external symbol comparator according to one or more embodiments.

[0081] Figure 5 The first external symbol comparator 2300 of Figures 4A to 4C may correspond to the first external symbol comparator 2300 of Figure 5 and overlapping descriptions are omitted. Additionally, the operation of the second external symbol comparator 2310 that operates similarly to the first external symbol comparator 2300 of Figure 5 may be understood through the description below with reference to Figures 4A to 4C ​

[0082] Refer to Figure 5 , the first external symbol comparator 2300 may include a buffer 2301 and a symbol mismatch counter 2302.

[0083] As referred to above Figures 4A to 4C described, the first external symbol comparator 2300 may store the symbols of the first external LLR LLR_EX1. Specifically, the buffer 2301 included in the first external symbol comparator 2300 may store the symbols of a plurality of first external LLRs LLR_EX1 corresponding to a plurality of bits included in the code block, respectively.

[0084] As referred to above Figures 4A to 4C described, according to one or more embodiments, the symbol mismatch counter 2302 may generate a first external count value ECV_1 based on the symbols of the first external LLR LLR_EX1 and the symbols of the third external LLR LLR_EX3. Specifically, the symbol mismatch counter 2302 may generate the first external count value ECV_1 by counting the number of bits in which the symbols of the first external LLR LLR_EX1 are different from the symbols of the third external LLR LLR_EX3 among the plurality of bits. The first external symbol comparator 2300 may output the first external count value ECV_1 to Figure 3 processor 280.

[0085] To compare the symbols of the fifth external LLR ( Figure 4C LLR_EX5) generated in the next iteration loop with the symbols of the third external LLR LLR_EX3, the buffer 2301 may store the symbols of each of the plurality of third external LLRs LLR_EX3. For example, the buffer 2301 may store the symbols of each of the plurality of third external LLRs LLR_EX3 instead of the symbols of each of the plurality of previously stored first external LLRs LLR_EX1.

[0086] Figure 6 is a table showing the symbol conversion of the external LLR according to one or more embodiments.

[0087] Refer to the above Figures 4A to 4C description Figure 6 .

[0088] Figure 6 is for explaining the first external count value ( Figure 4B ECV_1) and the third external count value ( Figure 4CDiagram of ECV_3).

[0089] Referring to Figure 6 , a code block may include 10 bits Bit_1 to Bit_10. The receiver may generate multiple first extrinsic LLRs LLR_EX1, multiple third extrinsic LLRs LLR_EX3, and multiple fifth extrinsic LLRs LLR_EX5 through iterative loops to construct a code block including 10 bits.

[0090] According to one or more embodiments, the receiver may count the number of bits among the 10 bits where the sign of the corresponding first extrinsic LLR LLR_EX1 is different from the sign of the corresponding third extrinsic LLR LLR_EX3 in the (N + 1)-th iterative loop. Referring to Figure 6 , the receiver may generate a first extrinsic count value ( Figure 4B of ECV_1) by counting the number of bits (i.e., the third bit Bit_3, the fourth bit Bit_4, the seventh bit Bit_7, and the eighth bit Bit_8) with different signs of the corresponding extrinsic LLRs. Referring to Figure 6 , the first extrinsic count value ( Figure 4B of ECV_1) is 4.

[0091] When the first extrinsic count value ( Figure 4B of ECV_1) is greater than or equal to a first predetermined threshold, the receiver may prematurely stop the turbo decoder from decoding the corresponding code block. As described above, the first threshold may be determined based on the number of bits. For example, the first threshold may be determined to be less than 5 of the number of bits.

[0092] When the first extrinsic count value ( Figure 4B of ECV_1) is less than the predetermined first threshold, the receiver may generate 10 fifth extrinsic LLRs LLR_EX5 by performing decoding on the corresponding code block.

[0093] According to one or more embodiments, the receiver may count the number of bits among the 10 bits where the sign of the corresponding third extrinsic LLR LLR_EX3 is different from the sign of the corresponding fifth extrinsic LLR LLR_EX5. Referring to Figure 6 , the receiver may generate a third extrinsic count value ( Figure 4C of ECV_3) by counting the number of bits (i.e., the third bit Bit_3, the seventh bit Bit_7, the eighth bit Bit_8, and the ninth bit Bit_9) with different signs of the corresponding extrinsic LLRs. Referring to Figure 6 , the third extrinsic count value ( Figure 4C of ECV_3) is 4.

[0094] The receiver may be based on the third extrinsic count value ( Figure 4CA comparison between the ECV_3) and a predetermined second threshold is used to determine whether to stop decoding early. As described above, the second threshold can be determined based on the first external count value ( Figure 4B of the ECV_1), the first threshold, or the number of bits. For example, the second threshold can be determined to be equal to or less than the value of the first external count value ( Figure 4B of the ECV_1). Additionally, the second threshold can be determined to be less than the number of bits (e.g., 10). The determined second threshold can be less than the first threshold corresponding to the previous iteration loop.

[0095] Refer to Figure 6 , when the second threshold is determined to be less than the first external count value (e.g., the second threshold is 3), since the first external count value ( Figure 4B of the ECV_1) is the same as the third external count value ( Figure 4C of the ECV_3) (that is, the third external count value ( Figure 4C of the ECV_3) is greater than the second threshold), the receiver according to one or more embodiments can stop decoding the code block early. Therefore, the power consumed in decoding can be reduced by stopping the decoding of the code block expected to fail in decoding.

[0096] Figure 7A and Figure 7B are block diagrams of a turbo decoder according to one or more embodiments.

[0097] Figure 7A and Figure 7B The turbo decoder 230b can correspond to the turbo decoder 230 described above with reference to Figure 3 and can be understood with reference to Figures 4A to 4C . Therefore, overlapping descriptions can be omitted.

[0098] Refer to Figure 7A and Figure 7B , the turbo decoder 230b can include a first decoder 231, a second decoder 235, a first adder 232, a second adder 236, a first interleaver 233, a second interleaver 239, a first scaling value applicator 234, a second scaling value applicator 238, a deinterleaver 237, a first input / output symbol comparator 2320, and a second input / output symbol comparator 2330.

[0099] The same as Figures 4A to4C the first decoder 231, the second decoder 235, the first adder 232, the second adder 236, the first interleaver 233, the second interleaver 239, and the deinterleaver 237 of Figure 7A and Figure 7BThe first decoder 231, the second decoder 235, the first adder 232, the second adder 236, the first interleaver 233, the second interleaver 239, and the deinterleaver 237.

[0100] Each of the first scaling value applicator 234 and the second scaling value applicator 238 may receive an external LLR and may generate a priori LLR by applying a scaling value to the external LLR. The scaling value may be a positive real number less than 1 and may be the same value in each of a plurality of iterative loops. However, one or more embodiments are not limited thereto.

[0101] Figure 7A is a diagram depicting the Nth iterative loop of the turbo decoder 230b according to one or more embodiments, and Figure 7B is a diagram depicting the (N + 1)th iterative loop of the turbo decoder 230b according to one or more embodiments.

[0102] Referring to Figure 7A , according to one or more embodiments, the first input / output symbol comparator 2320 may receive, in the Nth iterative loop, a plurality of channel LLRs LLR_CH as inputs to the first decoder 231 and a plurality of first a posteriori LLRs LLR_POS1 as outputs of the first decoder 231. The first input / output symbol comparator 2320 may generate a first input / output count value IOC_1 by counting the number of bits among the plurality of bits for which the sign of the first a posteriori LLR LLR_POS1 is different from the sign of the channel LLR LLR_CH.

[0103] According to one or more embodiments, the receiver may determine whether to stop decoding early based on a comparison between the first input / output count value IOC_1 and a predetermined fifth threshold. For example, when the first input / output count value IOC_1 is greater than or equal to the fifth threshold, the receiver may stop decoding early to reduce power consumption. The fifth threshold may be determined based on the input / output count value generated by the first input / output symbol comparator 2320 in a previous iterative loop. For example, the fifth threshold may be less than or equal to the input / output count value generated in the previous iterative loop. Additionally, the fifth threshold may be determined based on the number of bits included in the code block. For example, the fifth threshold may be less than the number of bits.

[0104] Figure 7A illustrates the operation of the turbo decoder 230b in the first iterative loop. Thus, when N is 1, there is no input / output count value generated in a previous iterative loop. Thus, the fifth threshold may be determined based on the number of bits.

[0105] Similar to the above-described first input / output symbol comparator 2320, the second input / output symbol comparator 2330 may receive, in the Nth iteration loop, a plurality of channel LLRs LLR_CH that are inputs to the second decoder 235 and a plurality of second posterior LLRs LLR_POS2 that are outputs of the second decoder 235. The second input / output symbol comparator 2330 may generate a second input / output count value IOC_2 by counting the number of bits among the plurality of bits for which the sign of the second posterior LLR LLR_POS2 is different from the sign of the channel LLR LLR_CH.

[0106] A receiver according to one or more embodiments may determine whether to stop decoding early based on a comparison between the second input / output count value IOC_2 and a predetermined sixth threshold. For example, when the second input / output count value IOC_2 is greater than or equal to the sixth threshold, the receiver may stop decoding early to reduce power consumption. The sixth threshold may be determined based on the input / output count value generated by the second input / output symbol comparator 2330 in a previous iteration loop. For example, the sixth threshold may be equal to or less than the input / output count value generated in the previous iteration loop. Additionally, the sixth threshold may be determined based on the number of bits included in the code block. For example, the sixth threshold may be less than the number of bits.

[0107] Figure 7A Illustrates the operation of the turbo decoder 230b in the first iteration loop. Thus, when N is 1, there is no input / output count value generated in a previous iteration loop. Therefore, the sixth threshold may be determined based on the number of bits. The sixth threshold may be the same as the fifth threshold, but this is merely an example, and one or more embodiments are not limited thereto.

[0108] Refer to Figure 7B According to one or more embodiments, the first input / output symbol comparator 2320 may receive, in the (N + 1)th iteration loop, a plurality of channel LLRs LLR_CH that are inputs to the first decoder 231 and a plurality of third posterior LLRs LLR_POS3 that are outputs of the first decoder 231. The first input / output symbol comparator 2320 may generate a third input / output count value IOC_3 by counting the number of bits among the plurality of bits for which the sign of the third posterior LLR LLR_POS3 is different from the sign of the channel LLR LLR_CH.

[0109] A receiver according to one or more embodiments may determine whether to stop decoding early based on a third input / output count value IOC_3 and a predetermined seventh threshold. For example, when the third input / output count value IOC_3 is greater than or equal to the seventh threshold, the receiver may stop decoding early to reduce power consumption. The seventh threshold may be determined based on the first input / output count value IOC_1 generated by the first input / output symbol comparator 2320 in a previous iteration loop and / or the fifth threshold. For example, the seventh threshold may be equal to or less than the fifth threshold and / or the first input / output count value IOC_1. Additionally, the seventh threshold may be determined based on the number of bits included in the code block. For example, the seventh threshold may be less than the number of bits.

[0110] A second input / output symbol comparator 2330 according to one or more embodiments may receive, in an N+1-th iteration loop, a plurality of channel LLRs LLR_CH as inputs to a second decoder 235 and a plurality of fourth posterior LLRs LLR_POS4 as outputs of the second decoder 235. The second input / output symbol comparator 2330 may generate a fourth input / output count value IOC_4 by counting the number of bits among the plurality of bits for which the sign of the corresponding channel LLR LLR_CH is different from the sign of the corresponding fourth posterior LLR LLR_POS4.

[0111] The operation of a receiver according to one or more embodiments to determine whether to stop decoding early based on the fourth input / output count value IOC_4 and a predetermined eighth threshold may be readily understood from the above description and thus may be omitted. For example, the eighth threshold may be equal to or less than the sixth threshold and / or the second input / output count value IOC_2. Additionally, the eighth threshold may be determined based on the number of bits included in the code block.

[0112] A code block according to one or more embodiments may include a plurality of bits as described above. The plurality of bits may include a plurality of information bits and a plurality of parity bits. As described above, a receiver according to one or more embodiments may determine whether to stop decoding early based on the log-likelihood ratio of the information bits or the parity bits.

[0113] Although not shown in Figure 7A and Figure 7B a first input / output symbol comparator 2320 and a second input / output symbol comparator 2330 according to one or more embodiments may include a buffer and a symbol mismatch counter that operate similarly to the first external symbol comparator 2300 described above with reference to Figure 5 For example, the buffer may store the sign of each of the channel LLRs corresponding to the plurality of bits. Additionally, the symbol mismatch counter may generate an input / output count value by counting the number of bits among the plurality of bits for which the sign of the corresponding posterior LLR is different from the sign of the corresponding channel LLR.

[0114] As described above Figure 3 components included in the turbo decoder 230b can be integrated into a single circuit called a turbo decoding circuit. Additionally, as described above, although Figure 7A and Figure 7B do not show a decoding stop circuit or a processor ( Figure 3 the processor 280 in

[0115] Figure 8 ), those skilled in the art will understand that the turbo decoding circuit and the decoding stop circuit can be implemented on a single modem chip.

[0116] Referring below to the above Figure 7A and Figure 7B describe Figure 8 .

[0117] Figure 8 is a table showing symbol conversions of posterior LLRs with respect to symbols of channel LLRs according to one or more embodiments. Figure 7A The first input / output count value IOC_1 of Figure 7B and

[0118] Referring to Figure 8 , a code block may include 10 bits Bit_1 to Bit_10. A receiver according to one or more embodiments may count the number of bits among the 10 bits for which the symbol of the corresponding first posterior LLR LLR_POS1 is different from the symbol of the corresponding channel LLR LLR_CH. Referring to Figure 8 , the receiver may generate a first input / output count value ( Figure 7A the IOC_1 of Figure 8 ) by counting the number of bits (i.e., the fourth bit Bit_4, the sixth bit Bit_6, and the seventh bit Bit_7) for which the symbol of the corresponding first posterior LLR LLR_POS1 is different from the symbol of the corresponding channel LLR LLR_CH. Referring to Figure 7A , the first input / output count value (

[0119] When Figure 7AWhen the first input / output count value IOC_1 is greater than or equal to a predetermined fifth threshold, the receiver may stop decoding the corresponding code block in advance. As described above, the fifth threshold may be determined based on the number of bits. For example, the fifth threshold may be determined to be the number of a plurality of bits (e.g., 10) or less than the number of a plurality of bits.

[0120] When the first input / output count value IOC_1 is less than a predetermined fifth threshold (e.g., the fifth threshold is 4), the receiver may perform decoding on the corresponding code block to generate ten third posterior LLRs LLR_POS3 corresponding to ten bits respectively.

[0121] The receiver according to one or more embodiments may count the number of bits among the ten bits for which the signs of the corresponding third posterior LLRs LLR_POS3 are different from the signs of the corresponding channel LLRs LLR_CH. Refer to Figure 8 , the receiver may generate a third input / output count value ( Figure 7B IOC_3) by counting the number of bits (i.e., the third bit Bit_3, the fourth bit Bit_4, and the eighth bit Bit_8) for which the signs of the corresponding third posterior LLRs LLR_POS3 are different from the signs of the corresponding channel LLRs LLR_CH. Refer to Figure 8 , the third input / output count value ( Figure 7B IOC_3) is 3.

[0122] The receiver may determine whether to stop decoding in advance based on the third input / output count value ( Figure 7B IOC_3) and a predetermined seventh threshold. As described above, the seventh threshold may be determined based on the first input / output count value ( Figure 7A IOC_1), the fifth threshold, or the number of bits. For example, the seventh threshold may be determined to be a value equal to or less than the first input / output count value ( Figure 7A IOC_1). Additionally, the seventh threshold may be determined to be a value less than the number of a plurality of bits (e.g., 10). The determined seventh threshold may be less than the fifth threshold corresponding to the previous iteration loop. That is, the threshold corresponding to the current iteration loop may be less than the threshold corresponding to the previous iteration loop.

[0123] Refer to Figure 6 , when the seventh threshold is determined to be less than the first input / output count value (e.g., the seventh threshold is 2), the first input / output count value ( Figure 7A IOC_1) and the third input / output count value ( Figure 7A IOC_3) are the same (that is, the third input / output count value ( Figure 7AThe IOC_3) is greater than the seventh threshold), so the receiver according to one or more embodiments can stop decoding the code block in advance. Therefore, the power consumed in decoding can be reduced by stopping the decoding of the code block expected to fail in decoding.

[0124] Figure 9 is a block diagram of a turbo decoder according to one or more embodiments.

[0125] Figure 9 The turbo decoder 230c can correspond to the turbo decoder 230 described above with reference to Figure 3 and can be understood with reference to Figures 4A to 4C , Figure 7A and Figure 7B Thus, overlapping descriptions can be omitted.

[0126] Figure 9 The turbo decoder 230c can generate an external count value ECV_1 and / or ECV_2 (e.g., a first external count value ECV_1 and / or a second external count value ECV_2), and an input / output count value IOC_3 and / or IOC_4 (e.g., a third input / output count value IOC_3 and / or a fourth input / output count value IOC_4). Since the operations of the turbo decoder 230c for generating the external count value ECV_1 and / or ECV_2 and the input / output count value IOC_3 and / or IOC_4 can be understood from the above description, they can be omitted.

[0127] It can be understood that the turbo decoder 230c according to one or more embodiments is a combination of the turbo decoder 230a and the turbo decoder 230b described above with reference to Figures 4A to 4C , Figure 7A and Figure 7B Thus, the receiver including the turbo decoder 230c can compare each of the input / output count values (e.g., IOC_3 and IOC_4) and the external count values (e.g., ECV_1 and ECV_2) with a predetermined threshold to determine whether to stop decoding in advance. The thresholds for comparing with each of the input / output count values (e.g., IOC_3 and IOC_4) and the external count values (e.g., ECV_1 and ECV_2) can be understood from the above description.

[0128] In addition, as described above, the components included in the turbo decoder 230c can be configured as a circuit and can be referred to as a turbo decoding circuit. In addition, as described above, although Figure 9 the decoding stop circuit or the processor is not shown in Figure 3in the processor 280), but those skilled in the art can understand that the turbo decoding circuit and the decoding stop circuit can be implemented on a single modem chip.

[0129] Figure 10 is a flowchart of an operation method of a turbo decoder according to one or more embodiments.

[0130] Referring to Figure 10 , in operation S100, the turbo decoder may receive a plurality of bits included in a symbol.

[0131] In operation S200, the turbo decoder may generate a plurality of channel LLRs corresponding to the plurality of bits respectively.

[0132] In operation S300, the turbo decoder may generate at least one log-likelihood ratio corresponding to the plurality of bits respectively based on the plurality of channel LLRs.

[0133] According to one or more embodiments, the turbo decoder may generate a plurality of first extrinsic LLRs corresponding to the plurality of bits respectively in the Nth iteration loop (N is an integer greater than or equal to 1). Additionally, a plurality of second extrinsic LLRs corresponding to the plurality of bits respectively may be generated in the (N + 1)th iteration loop, and a plurality of third extrinsic LLRs corresponding to the plurality of bits respectively may be further generated in the (N + 2)th iteration loop.

[0134] According to another embodiment, the turbo decoder may generate a plurality of first posterior LLRs corresponding to the plurality of bits respectively in the Nth iteration loop (N is an integer greater than or equal to 1). Additionally, a plurality of second posterior LLRs corresponding to the plurality of bits respectively may be generated in the (N + 1)th iteration loop.

[0135] In operation S400, the turbo decoder may generate a count value by counting the number of bits of different symbols having two different log-likelihood ratios among the plurality of bits. The two different log-likelihood ratios may include at least one log-likelihood ratio.

[0136] According to one or more embodiments, the turbo decoder may generate a first extrinsic count value by counting the number of second extrinsic LLRs having a different sign from the corresponding first extrinsic LLR among the plurality of second extrinsic LLRs. Additionally, the turbo decoder may also generate a second extrinsic count value by counting the number of third extrinsic LLRs having a different sign from the corresponding second extrinsic LLR among the plurality of third extrinsic LLRs.

[0137] A turbo decoder according to another embodiment may generate a first input / output count value by counting the number of first posterior LLRs among a plurality of first posterior LLRs having symbols different from corresponding channel LLRs. Additionally, the turbo decoder may also generate a second input / output count value by counting the number of second posterior LLRs among a plurality of second posterior LLRs having symbols different from corresponding channel LLRs.

[0138] In operation S500, when the count value (e.g., the external count value and / or the input / output count value) is greater than or equal to a predetermined threshold, the turbo decoder may stop decoding a plurality of bits.

[0139] When the first external count value is greater than or equal to a first threshold, a turbo decoder according to one or more embodiments may stop decoding a plurality of bits, the first threshold being less than the number of bits. Additionally, when the second external count value is greater than or equal to a second threshold, decoding of the plurality of bits may be stopped, the second threshold being less than the first threshold and / or the first external count value.

[0140] When the first input / output count value is greater than or equal to a third threshold, a turbo decoder according to another embodiment may stop decoding a plurality of bits, the third threshold being less than the number of bits. Additionally, when the second input / output count value is greater than or equal to a fourth threshold, decoding of the plurality of bits may be stopped, the fourth threshold being less than the third threshold and / or the first input / output count value. In one embodiment, the ratio of the first threshold to the second threshold based on the external count value may be equal to the ratio of the third threshold to the fourth threshold based on the input / output count value.

[0141] Figure 11 is a block diagram of a wireless communication device according to one or more embodiments.

[0142] Referring to Figure 11 , the wireless communication device 1000 corresponding to the aforementioned receiver may include an application specific integrated circuit (ASIC) 1100, an application specific instruction set processor (ASIP) 1300, a memory 1500, a main processor 1700, and a main memory 1900. Two or more of the ASIC 1100, the ASIP 1300, and the main processor 1700 may communicate with each other. Additionally, at least two or more of the ASIC 1100, the ASIP 1300, the memory 1500, the main processor 1700, and the main memory 1900 may be embedded in one chip.

[0143] The ASIP 1300 can be a customized integrated circuit for a specific purpose. The ASIP 1300 can support an instruction set for a specific application and can execute instructions included in the instruction set. The memory 1500 can communicate with the ASIP 1300 and can store, as a non-transitory storage device, multiple instructions executed by the ASIP 1300. For example, the memory 1500 can include, but is not limited to, any type of memory accessible by the ASIP 1300 (such as random access memory (RAM), read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof).

[0144] The main processor 1700 can control the wireless communication device 1000 by executing multiple instructions. For example, the main processor 1700 can control the ASIC 1100 and the ASIP 1300, process received data, or process a user's input to the wireless communication device 1000. The main memory 1900 can communicate with the main processor 1700 and can store, as a non-transitory storage device, multiple instructions executed by the main processor 1700. For example, the main memory 1900 can include, but is not limited to, any type of memory accessible by the main processor 1700 (such as RAM, ROM, magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof).

[0145] The main processor 1700 can include the processor 280 described above with reference to Figure 3 However, one or more embodiments are not limited thereto. A processor according to one or more embodiments (e.g., Figure 3 the processor 280) refers to a configuration for determining whether to stop decoding early based on a count value.

[0146] According to one or more embodiments described above with reference to Figures 1 to 10 The wireless communication device and the operation method of the wireless communication device can be executed by at least one component among the components included in Figure 10 the wireless communication device 1000. In some embodiments, at least one operation of the operation method of the above wireless communication device can be implemented as multiple instructions stored in the memory 1500. In some embodiments, the ASIP 1300 can execute at least one of the operations of the above method by executing multiple instructions stored in the memory 1500.

[0147] The foregoing exemplary embodiments are merely exemplary and should not be construed as restrictive. The present teachings can be easily applied to other types of devices. Additionally, the description of the exemplary embodiments is intended to be illustrative and does not limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A modem chip comprising: The turbo decoding circuit is configured as follows: receiving a plurality of channel log-likelihood ratios respectively corresponding to a plurality of bits included in the symbol; Based on the plurality of channel log-likelihood ratios, generating a plurality of first a posteriori log-likelihood ratios corresponding to the plurality of bits, respectively, in an Nth iteration loop, where N is greater than or equal to 1; and generating a first input / output count value by counting the number of first a posteriori log-likelihood ratios that differ in sign from the corresponding channel log-likelihood ratio among the plurality of first a posteriori log-likelihood ratios; as well as The decoding control circuit is configured to stop decoding the plurality of bits in the turbo decoding circuit based on the first input / output count value being greater than or equal to a first threshold.

2. The modem chip according to claim 1, wherein When N is 1, the first threshold is determined based on the number of the plurality of bits and is set to be smaller than the number of the plurality of bits.

3. The modem chip according to claim 1, wherein, The turbo decoding circuit is further configured to: generate a plurality of second a posteriori log-likelihood ratios respectively corresponding to the plurality of bits in an N+1th iteration loop, and generate a second input / output count value by counting the number of second a posteriori log-likelihood ratios that differ in sign from the corresponding channel log-likelihood ratio among the plurality of second a posteriori log-likelihood ratios; The decoding control circuit is further configured to stop decoding in the turbo decoding circuit based on the second input / output count being greater than or equal to a second threshold, where the second threshold is determined based on the first input / output count.

4. The modem chip according to claim 3, wherein, The second threshold is smaller than the first input / output count value.

5. The modem chip according to claim 3, wherein: The second threshold is smaller than the first threshold.

6. The modem chip according to claim 3, wherein, The turbo decoding circuit is further configured to generate a plurality of first extrinsic log-likelihood ratios respectively corresponding to the plurality of bits based on the plurality of first a posteriori log-likelihood ratios, generate a plurality of second extrinsic log-likelihood ratios respectively corresponding to the plurality of bits based on the plurality of second a posteriori log-likelihood ratios, and generate a first extrinsic count value by counting the number of second extrinsic log-likelihood ratios that differ in sign from the corresponding first extrinsic log-likelihood ratios among the plurality of second extrinsic log-likelihood ratios. The decoding control circuit is further configured to: stop decoding in the turbo decoding circuit based on the first external count value being greater than or equal to a third threshold.

7. The modem chip according to claim 6, wherein, The turbo decoding circuit is further configured to: generate a plurality of third external log-likelihood ratios respectively corresponding to the plurality of bits in an N+2th iteration loop, and generate a second external count value by counting the number of third external log-likelihood ratios among the plurality of third external log-likelihood ratios that are different in sign from the corresponding second external log-likelihood ratio. The decoding control circuit is further configured to stop decoding in the turbo decoding circuit based on the second external count value being greater than or equal to a fourth threshold, where the fourth threshold is determined based on the first external count value.

8. The modem chip according to claim 7, wherein: The fourth threshold is smaller than the first external count value.

9. The modem chip according to claim 7, wherein, The fourth threshold is smaller than the third threshold.

10. The modem chip according to claim 7, wherein: The ratio of the first threshold to the second threshold is equal to the ratio of the third threshold to the fourth threshold.

11. A modem chip, comprising: The turbo decoding circuit is configured as follows: Receiving a plurality of channel log-likelihood ratios corresponding to a plurality of bits included in a symbol; Based on the plurality of channel log-likelihood ratios, generating, in an Nth iteration loop, a plurality of first extrinsic log-likelihood ratios corresponding to the plurality of bits, where N is greater than or equal to 1; Generating, in an (N + 1)th iteration loop, a plurality of second extrinsic log-likelihood ratios corresponding to the plurality of bits; and Generating a first extrinsic count value by counting the number of second extrinsic log-likelihood ratios among the plurality of second extrinsic log-likelihood ratios that are different in sign from the corresponding first extrinsic log-likelihood ratio; and A decoding control circuit configured to: based on the first extrinsic count value being greater than or equal to a first threshold, stop decoding the plurality of bits in a turbo decoding circuit.

12. The modem chip of claim 11, wherein: When N is 1, the first threshold is determined based on the number of the plurality of bits and is set to be less than the number of the plurality of bits.

13. The modem chip of claim 11, wherein: The turbo decoding circuit is further configured to: generate, in an (N + 2)th iteration loop, a plurality of third extrinsic log-likelihood ratios corresponding to the plurality of bits, and generate a second extrinsic count value by counting the number of third extrinsic log-likelihood ratios among the plurality of third extrinsic log-likelihood ratios that are different in sign from the corresponding second extrinsic log-likelihood ratio, wherein the decoding control circuit is further configured to: based on the second extrinsic count value being greater than or equal to a second threshold, stop decoding in the turbo decoding circuit, and the second threshold is less than the first threshold.

14. The modem chip according to claim 13, wherein, The second threshold is determined based on the first extrinsic count value.

15. The modem chip according to claim 14, wherein, The second threshold is less than the first extrinsic count value.

16. An operation method of a turbo decoder, the operation method comprising: Receiving a plurality of bits included in a symbol; Generating a plurality of channel log-likelihood ratios corresponding to the plurality of bits; Generating at least one log-likelihood ratio corresponding to the plurality of bits based on the plurality of channel log-likelihood ratios; Generating a count value by counting the number of bits among the plurality of bits for which two different corresponding log-likelihood ratios have different signs; and Based on the count value being greater than or equal to a preset threshold, stopping decoding of the plurality of bits, wherein the two different log-likelihood ratios include the at least one log-likelihood ratio.

17. The operating method according to claim 16, wherein, The step of generating the at least one log-likelihood ratio includes: generating, in an Nth iteration loop, a plurality of first extrinsic log-likelihood ratios corresponding to the plurality of bits, and generating, in an (N + 1)th iteration loop, a plurality of second extrinsic log-likelihood ratios corresponding to the plurality of bits, N is greater than or equal to 1, and The step of generating the count value includes: generating a first extrinsic count value by counting the number of second extrinsic log-likelihood ratios among the plurality of second extrinsic log-likelihood ratios that are different in sign from the corresponding first extrinsic log-likelihood ratio, The step of stopping decoding includes: based on the first extrinsic count value being greater than or equal to a first threshold, stopping decoding of the plurality of bits, and the first threshold is less than the number of the plurality of bits.

18. The operating method according to claim 17, wherein, The step of generating the at least one log-likelihood ratio further includes: generating a plurality of third extrinsic log-likelihood ratios respectively corresponding to the plurality of bits in the (N + 2)-th iteration loop, The step of generating the count value further includes: generating a second extrinsic count value by counting the number of the third extrinsic log-likelihood ratios among the plurality of third extrinsic log-likelihood ratios that are different from the corresponding second extrinsic log-likelihood ratio in terms of sign, and The step of stopping decoding further includes: stopping decoding of the plurality of bits based on the second extrinsic count value being greater than or equal to a second threshold, where the second threshold is less than the first threshold and the first extrinsic count value.

19. The operating method according to claim 16, wherein, The step of generating the at least one log-likelihood ratio includes: generating a plurality of first posterior log-likelihood ratios respectively corresponding to the plurality of bits in the N-th iteration loop, where N is greater than or equal to 1, and The method of generating the count value includes: generating a first input / output count value by counting the number of the first posterior log-likelihood ratios among the plurality of first posterior log-likelihood ratios that are different from the corresponding channel log-likelihood ratio in terms of sign, The step of stopping decoding further includes: stopping decoding of the plurality of bits based on the first input / output count value being greater than or equal to a third threshold, where the third threshold is less than the number of the plurality of bits.

20. The operating method according to claim 19, wherein, The step of generating the at least one log-likelihood ratio further includes: generating a plurality of second posterior log-likelihood ratios respectively corresponding to the plurality of bits in the (N + 1)-th iteration loop, The step of generating the count value further includes: generating a second input / output count value by counting the number of the second posterior log-likelihood ratios among the plurality of second posterior log-likelihood ratios that are different from the corresponding channel log-likelihood ratio in terms of sign, and The step of stopping decoding further includes: stopping decoding of the plurality of bits based on the second input / output count value being greater than or equal to a fourth threshold, where the fourth threshold is less than the third threshold and the first input / output count.

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