Device structure of N-type PERT double-sided solar cell and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a device structure of an N-type PERT double-sided solar cell and a preparation method thereof, the device structure of the N-type PERT double-sided solar cell comprises a front electrode, a front antireflection layer, a passivation layer, a p + emitter, an N-type monocrystalline silicon wafer, an n + back surface field, a back antireflection layer and a back electrode; the n + back surface field is an amorphous silicon-microcrystalline silicon-polycrystalline silicon composite thin film layer and is composed of an amorphous silicon layer, a microcrystalline silicon layer and a polycrystalline silicon layer; the doped microcrystalline silicon thin film layer and the polycrystalline silicon thin film layer are used for replacing device design improvement of a traditional thermal diffusion back surface field, silicon wafer body defects (such as dislocation, lattice distortion and the like) caused by introduction of phosphorus impurities are effectively avoided, a gradually-changed back surface field and a refractive index gradually-changed optical composite thin film are formed, dual optimization of electrical performance and optical performance is achieved, and the manufacturing cost is reduced. Therefore, the open-circuit voltage and the short-circuit current are improved, and the conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to a device structure and a preparation method of an N-type PERT double-sided solar cell. Background Art

[0002] In recent years, with the increasing urgency of the demand for high-efficiency and low-cost solar cells in the photovoltaic industry, N-type double-sided PERT (Passivated Emitter and Rear Totally-diffused Cell) solar cells have attracted much attention due to their low light attenuation characteristics. Attached Figure 1 is a schematic diagram of the device structure of a traditional PERT cell.

[0003] However, traditional PERT cells face double dilemmas in large-scale production: Firstly, the mass production conversion efficiency has been stagnant at the ~24% level for a long time, reaching the limit of the existing structure, and only increasing by 0.5 percentage points compared to PERC (Passivated Emitter and Rear Cell) cells; Secondly, the non-silicon cost is as high as more than 0.2 yuan / W, increasing by more than 30% compared to PERC cells, with a significant economic disadvantage. Due to the low open-circuit voltage and cell conversion efficiency, and the prominent cost disadvantage, it has directly led to the marginalization of PERT cells in the mainstream photovoltaic market.

[0004] Therefore, it is necessary to propose an improved device structure and corresponding preparation method for a new type of high-efficiency and low-cost PERT solar cell. Summary of the Invention

[0005] The purpose of the present invention is to provide a device structure and a preparation method of an N-type PERT double-sided solar cell to solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solution: A device structure of an N-type PERT double-sided solar cell, comprising a front electrode, a front anti-reflection layer, a passivation layer, a p+ emitter, an N-type monocrystalline silicon wafer, an n+ back surface field, a back anti-reflection layer, and a back electrode; The n+ back surface field is an amorphous silicon - microcrystalline silicon - polycrystalline silicon composite thin film layer, composed of an amorphous silicon layer, a microcrystalline silicon layer, and a polycrystalline silicon layer.

[0007] A method for preparing the N-type PERT double-sided solar cell described in claim 1, comprising the following steps: Step 1: Texturing: Making both the front and back surfaces have pyramid structures; Step 2: Boron diffusion; Step 3: Cleaning and alkaline polishing; Step 4: Sequentially grow an intrinsic amorphous silicon thin film, a microcrystalline silicon thin film, and a polycrystalline silicon thin film by PECVD to form an n+ back surface field; Step 5: Deposit a passivation layer on the front surface by ALD; Step 6: Deposit a front film by PECVD; Step 7: Deposit a back film by PECVD; Step 8: Print and sinter; Step 9: Perform laser scanning treatment on the front and back electrodes.

[0008] Preferably, in Step 2, a p+ emitter is formed on the front surface by boron diffusion to form a PN junction with the N-type monocrystalline silicon wafer; a back surface field is realized on the back surface by doping a silicon thin film composite layer.

[0009] Preferably, in Step 4, by using the PECVD process, deposit an amorphous silicon layer of 2 - 5 nm, a microcrystalline silicon layer of 5 - 15 nm, and a polycrystalline silicon layer of 15 - 50 nm in sequence to form an amorphous silicon - microcrystalline silicon - polycrystalline silicon gradient structure thin film, and construct a composite back surface field structure with gradient crystallinity and doping concentration.

[0010] Preferably, the amorphous silicon layer is an intrinsic hydrogenated amorphous silicon thin film, and the concentration of the microcrystalline silicon layer is 1 - 5×10 19 / cm 3 , and the concentration of the polycrystalline silicon layer is 1 - 5×10 20 / cm 3 .

[0011] Preferably, the PECVD process parameters are as follows: temperature 100 - 350 °C, radio frequency 13.56 - 60 MHz, radio frequency power density greater than 0.1 W / cm², deposition pressure 0.1 - 3 Torr, H2 / SiH4 flow ratio 2 - 90, PH3 volume ratio 1 - 4 vol%, deposition rate 0.1 - 8 nm / min.

[0012] Preferably, the PECVD process parameters for depositing the amorphous silicon layer are: temperature 100 - 180 °C, radio frequency 13.56 MHz, radio frequency power density 0.1 - 0.3 W / cm², deposition pressure 0.1 - 1 Torr, H2 / SiH4 flow ratio 2 - 5, deposition rate 0.1 - 0.5 nm / min; The PECVD process parameters for depositing the microcrystalline silicon layer are: temperature 180 - 250 °C, radio frequency 13.56 - 27.12 MHz, radio frequency power density 0.5 - 1 W / cm², deposition pressure 1 - 3 Torr, H2 / SiH4 flow ratio 20 - 30, PH3 volume ratio 1 - 2 vol%, deposition rate 0.5 - 4 nm / min; The PECVD process parameters for depositing the polysilicon layer are as follows: temperature 250 - 350 °C, radio frequency frequency 40 - 60 MHz, radio frequency power density greater than 2 W / cm², deposition pressure 0.5 - 1.5 Torr, H2 / SiH4 flow ratio 50 - 90, PH3 volume ratio 3 - 4 vol%, deposition rate 1 - 8 nm / min.

[0013] Preferably, in step 6, the PECVD deposited front film is the front anti-reflection layer; in step 7, the PECVD deposited back film is the back anti-reflection layer.

[0014] Preferably, in step 8, the printing process specifically involves printing silver paste on the front and back of the battery to form the front electrode and the back electrode; the sintering process specifically involves sintering to form an ohmic contact between the front silver paste or silver-aluminum paste and the front surface of the silicon wafer, and an ohmic contact between the back silver paste and the silicon thin film composite layer, and removing the organic binder.

[0015] Preferably, in the step, both the front electrode and the back electrode are processed by laser scanning to improve the silver-silicon metal-semiconductor contact, and a reverse bias voltage is applied during laser irradiation; the back electrode is in direct ohmic contact with the microcrystalline silicon layer or the polysilicon layer, avoiding contact with the body of the N-type monocrystalline silicon wafer.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. In the present invention, the device design improvement of replacing the traditional thermal diffusion back field by doping the microcrystalline silicon thin film layer and the polysilicon thin film layer effectively avoids the defects of the silicon wafer body (such as dislocations, lattice distortion, etc.) caused by the introduction of phosphorus impurities. By depositing the thin film through PECVD, first deposit an intrinsic hydrogenated amorphous silicon ultra-thin layer with a thickness of 2 - 5 nanometers by adjusting the PECVD process parameters, then deposit and grow a microcrystalline silicon layer with a relatively low impurity concentration of 5 - 15 nanometers, and then deposit and grow a polysilicon layer with a higher impurity concentration of 15 - 50 nanometers, finally forming an intrinsic amorphous silicon - low-doped microcrystalline silicon - high-doped polysilicon composite thin film layer. On the one hand, different impurity concentrations are formed to improve the back surface field effect, and on the other hand, a refractive index gradient layer is formed to reduce the back surface optical loss, forming a gradient back surface field and a refractive index gradient optical composite thin film, achieving the dual optimization of electrical and optical properties. Thus, both the open circuit voltage and the fill factor are increased, and the short circuit current is also increased, so the photoelectric conversion efficiency of the battery is promoted to be greatly improved.

[0017] 2. The back surface uses an alkali polishing process to flatten the pyramid texture on the back surface of the silicon wafer, serving as an infrared light emitter, and at the same time improving the compactness and continuity of the amorphous silicon - microcrystalline silicon - polysilicon composite thin film, improving the passivation effect, thereby increasing the open circuit voltage.

[0018] 3. The back surface electrode is in direct ohmic contact with the microcrystalline silicon or polycrystalline silicon layer after burning through the back surface antireflection layer, avoiding contact between the electrode and the silicon wafer body, reducing the accumulation of locally high-concentration carriers, and minimizing non-radiative recombination such as Auger recombination, thereby increasing the open-circuit voltage and the cell conversion efficiency.

[0019] 4. A laser process is used to treat the front and back electrodes, which are scanned under a certain bias voltage to improve the silver-silicon metal-semiconductor contact, thereby reducing the series resistance and increasing the fill factor.

[0020] 5. After the device structure is optimized, the manufacturing process flow of the device is reduced by 2 steps compared with that of the traditional N-type PERT bifacial cell. While improving the cell conversion efficiency, the non-silicon cost of cell production is also reduced, enabling large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of a traditional N-type PERT bifacial solar cell; Figure 2 is a schematic structural diagram of the device of the N-type PERT bifacial solar cell provided by the present invention; Figure 3 is the manufacturing process flow of the N-type PERT bifacial solar cell in the present invention; Among them, 1 - front electrode, 2 - front surface antireflection layer, 3 - passivation layer, 4 - p+ emitter, 5 - N-type monocrystalline silicon wafer, 6 - n+ back surface field, 61 - amorphous silicon layer, 62 - microcrystalline silicon layer, 63 - polycrystalline silicon layer; 7 - back surface antireflection layer, 8 - back electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] The present invention provides a technical solution: a device structure of an N-type PERT bifacial solar cell, including a front electrode 1, a front surface antireflection layer 2, a passivation layer 3, a p+ emitter 4, an N-type monocrystalline silicon wafer 5, an n+ back surface field 6, a back surface antireflection layer 7, and a back electrode 8, wherein the n+ back surface field 6 is an amorphous silicon-microcrystalline silicon-polycrystalline silicon composite thin film layer, composed of an amorphous silicon layer 61, a microcrystalline silicon layer 62, and a polycrystalline silicon layer 63.

[0024] The front electrode 1 is an Ag front electrode or an Ag / Al front electrode, the front antireflection layer 2 is a Si3N4 antireflection layer, the passivation layer 3 is an Al2O3 passivation layer, the back antireflection layer 7 is a Si3N4 antireflection layer, and the back electrode 8 is an Ag back electrode.

[0025] The present invention also provides a technical solution: a preparation method of an N-type PERT double-sided solar cell, comprising the following steps: Step 1: Texturing: Make the front and back surfaces have pyramid structures, reduce the light reflectivity and enhance the light trapping ability, thereby improving the photoelectric conversion efficiency.

[0026] Step 2: Boron diffusion: Form a p+ emitter 4 (inversion layer) on the front surface through boron diffusion, form a PN junction with the N-type monocrystalline silicon wafer 5, and realize the separation of photo-generated carriers; on the back surface, realize the back surface field by doping a silicon thin film composite layer, and use the built-in electric field to suppress the recombination of minority carriers (holes) on the back surface.

[0027] Step 3: Cleaning and alkaline polishing: Remove impurities through cleaning, then remove the excess doping on the edges, and at the same time polish the back surface flat through alkaline polishing to improve the passivation effect.

[0028] Step 4: Sequentially grow an intrinsic hydrogenated amorphous silicon thin film, a low-doped microcrystalline silicon thin film, and a highly doped polycrystalline silicon thin film by PECVD to form an n+ back surface field 6: Adopt the PECVD (plasma-enhanced chemical vapor deposition) process, and by adjusting the process parameters, sequentially deposit a 2-5 nm amorphous silicon layer 61, a 5-15 nm microcrystalline silicon layer 62 with a relatively low impurity concentration (concentration of 1~5×10 19 / cm 3 ), and a 15-50 nm polycrystalline silicon layer 63 with a higher impurity concentration (concentration of 1~5×10 20 / cm 3 ). The amorphous silicon layer 61 is an intrinsic hydrogenated amorphous silicon layer, forming an amorphous silicon-microcrystalline silicon-polysilicon gradient structure thin film, constructing a composite back surface field structure with gradient crystallinity and doping concentration. On the one hand, different impurity concentrations are formed to improve the back surface field effect, and on the other hand, a refractive index gradient layer is formed to reduce the back surface optical loss, forming a gradient back surface field and a refractive index gradient optical composite thin film, realizing the dual optimization of electrical and optical properties.

[0029] The specific PECVD process parameters are shown in Table 1:

[0030] Step 5: Deposit a passivation layer on the front surface by ALD: Deposit a passivation layer 3 (Al2O3 passivation layer) on the front surface by ALD (atomic layer deposition).

[0031] Step 6: PECVD front film: PECVD deposits the front anti-reflection layer 2 (Si3N4 anti-reflection layer).

[0032] Step 7: PECVD back film: PECVD deposits the back anti-reflection layer 7 (Si3N4 anti-reflection layer).

[0033] Step 8: Printing and sintering: Silver paste is printed on the front and back of the cell to form the front electrode 1 (Ag front electrode or Ag / Al front electrode) and the back electrode 8 (Ag back electrode); through high-temperature (750 - 950 °C) sintering, the front silver paste or silver-aluminum paste forms an ohmic contact with the front surface of the silicon wafer, and the back silver paste forms an ohmic contact with the silicon thin film composite layer, and the organic binder is removed.

[0034] Step 9: Front and back electrode laser scanning treatment: Both the front electrode 1 and the back electrode 8 are processed by laser scanning to improve the silver-silicon metal-semiconductor contact. When the laser irradiates, a reverse bias voltage of more than 20 V is applied to the positive and negative electrodes of the cell to enhance the carrier mobility, promote the diffusion of silver ions into the silicon wafer or silicon thin film, enable better contact between silver and silicon, further optimize the contact quality, thereby reducing the series resistance and increasing the fill factor; Among them, the back electrode 8 is in direct ohmic contact with the microcrystalline silicon or polycrystalline silicon layer, avoiding contact with the body of the N-type monocrystalline silicon wafer 5, reducing the accumulation of locally high-concentration carriers, and minimizing non-radiative recombination such as Auger recombination to the greatest extent, thereby increasing the open-circuit voltage and the cell conversion efficiency.

[0035] The laser scanning uses a nanosecond or picosecond laser, with a wavelength of 500 - 1400 nm, a laser power of 8 - 24 W, an energy density of 0.5 - 2.5 J / cm², a pulse frequency of 50 - 200 kHz, a scanning speed of 5 - 20 m / s, a spot diameter of 20 - 50 μm, and a reverse voltage of 12 - 16 V.

[0036] Step 10: Testing, sorting, and packaging: The testing includes electrical performance testing and optical detection. Among them, the electrical performance testing includes IV (current-voltage) characteristic testing and EL (electroluminescence) detection; the optical detection includes appearance inspection and reflectance / transmittance testing; after sorting and grading, packaging is carried out.

[0037] The preparation steps of the traditional N-type PERT double-sided solar cell are 12 steps, which are respectively: S1: Silicon wafer cleaning and double-sided texturing, S2: Boron diffusion (formation of P+ emitter), S3: Removal of boron-silicon glass (BSG), S4: Phosphorus diffusion (formation of N+ back field), S5: Removal of phosphorus-silicon glass (PSG), S6: Edge isolation etching, S7: Front passivation and anti-reflection layer deposition, S8: Back passivation and structure optimization, S9: Back laser drilling, S10: Double-sided electrode printing and metallization, S11: High-temperature sintering, S12: Performance testing and sorting packaging.

[0038] The total preparation steps of the novel N-type PERT bifacial solar cell provided by the present invention are 10 steps, two steps less than those of the traditional N-type PERT bifacial solar cell preparation, which can reduce the non-silicon cost. Example 1:

[0039] Step 1: Texturing.

[0040] Step 2: Boron diffusion.

[0041] Step 3: Cleaning and alkaline polishing.

[0042] Step 4: PECVD deposit a 5-nm amorphous silicon layer 61; PECVD deposit a 15-nm microcrystalline silicon layer 62 (concentration of 1×10 19 / cm 3 ); PECVD deposit a 50-nm polycrystalline silicon layer 63 (concentration of 5×10 20 / cm 3 ).

[0043] The PECVD process parameters of Example 1 are shown in Table 2:

[0044] Step 5: Deposit a passivation layer on the front surface by ALD.

[0045] Step 6: PECVD front film.

[0046] Step 7: PECVD back film.

[0047] Step 8: Printing and sintering.

[0048] Step 9: Laser scanning treatment for the front and back electrodes; The specific laser scanning treatment parameters are as follows: Wavelength 1064 nm, laser power 20 W, energy density 2.3 J / cm², pulse frequency 100 kHz, scanning speed 15 m / s, spot diameter 40 μm, reverse voltage 14 V.

[0049] Step 10: Testing, sorting, and packaging.

[0050] The performance parameters of the N-type PERT bifacial solar cell obtained from the above manufacturing process are: open-circuit voltage (Voc): 718 mV, short-circuit current density (Jsc): 41.2 mA / cm 2 , fill factor (FF): 82.5%, solar cell conversion efficiency ( ): 24.4%.

[0051] Example 1 uses a high deposition rate, which can meet the mass production requirements. Its performance is slightly lower, but the cost is controllable. Example 2:

[0052] The difference between Example 2 and Example 1 lies in that the thickness of each structural layer deposited by PECVD and the PECVD process parameters in Step 4 are different.

[0053] Specifically, Step 4: Deposit a 3-nm amorphous silicon layer 61 by PECVD; Deposit a 12-nm microcrystalline silicon layer 62 by PECVD (concentration is 3×10 19 / cm 3 ); Deposit a 40-nm polycrystalline silicon layer 63 by PECVD (concentration is 2×10 20 / cm 3 ).

[0054] The PECVD process parameters of Example 2 are shown in Table 3:

[0055] The performance parameters of the N-type PERT double-sided solar cell obtained from the above manufacturing process are: open circuit voltage (Voc): 722 mV, short circuit current density (Jsc): 41.7 mA / cm 2 , fill factor (FF): 84.1%, solar cell conversion efficiency ( ): 25.3%.

[0056] Example 2 is a balanced parameter design and is suitable for a stable and efficient production line. Example 3:

[0057] The difference between Example 3 and Example 1 lies in that the thickness of each structural layer deposited by PECVD and the PECVD process parameters in Step 4 are different.

[0058] Specifically, Step 4: Deposit a 2-nm amorphous silicon layer 61 by PECVD; Deposit an 8-nm microcrystalline silicon layer 62 by PECVD (concentration is 5×10 19 / cm 3 ); Deposit a 30-nm polycrystalline silicon layer 63 by PECVD (concentration is 4×10 20 / cm 3 ).

[0059] The PECVD process parameters of Example 3 are shown in Table 4:

[0060] The performance parameters of the N-type PERT bifacial solar cell obtained by the above manufacturing process are: open-circuit voltage (Voc): 728 mV, short-circuit current density (Jsc): 42.0 mA / cm 2 , fill factor (FF): 83.6%, solar cell conversion efficiency ( ): 25.6%.

[0061] Example 3 improves the crystallization rate through high H2 dilution, which is the near-limit efficiency in the laboratory scenario.

[0062] The performance tests of the above three examples were all carried out by a cell I-V tester to obtain the performance parameters.

[0063] Comparative example: The comparative example uses the n-PERT bifacial cell jointly developed by IMEC and Zhonglai Co., Ltd. The following are its publicly disclosed electrical performance parameters: Open-circuit voltage (Voc): 690 mV, Short-circuit current density (Jsc): 40.5 mA / cm², Fill factor (FF): 83%, Conversion efficiency ( ): 23.2%.

[0064] The following table shows the comparison of the performance parameters of each N-type PERT cell:

[0065] According to the above test data, compared with the comparative example, in Example 1, the open-circuit voltage increased by 28 mV, the short-circuit current density increased by 0.7 mA / cm², the fill factor decreased by 0.5%, and the solar cell conversion efficiency increased by 1.2%.

[0066] Compared with the comparative example, in Example 2, the open-circuit voltage increased by 32 mV, the short-circuit current density increased by 1.2 mA / cm², the fill factor increased by 1.1%, and the solar cell conversion efficiency increased by 2.1%.

[0067] Compared with the comparative example, in Example 3, the open-circuit voltage increased by 38 mV, the short-circuit current density increased by 1.5 mA / cm², the fill factor increased by 0.6%, and the solar cell conversion efficiency increased by 2.4%.

[0068] In summary, the N-type PERT bifacial solar cell prepared by using the preparation method of the present invention is an upgraded version of the traditional N-PERT cell, which can realize the dual optimization of the electrical and optical properties of the cell. The open-circuit voltage Voc≥718 mV, and the short-circuit current density Jsc≥41.2 mA / cm 2, fill factor FF ≥ 82.5%, the conversion efficiency of the solar cell ≥ 24.4%, effectively improving the conversion efficiency by at least 1.2%, increasing the open-circuit voltage and fill factor, reducing the non-silicon cost by at least 0.04 yuan / W, and ultimately reducing the cost per kilowatt-hour of the photovoltaic power generation system.

[0069] For those skilled in the art, it is obvious that the invention is not limited to the details of the above exemplary embodiments, and the invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the invention. Any reference signs in the claims should not be construed as limiting the claimed invention.

[0070] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. The device structure of an N-type PERT double-sided solar cell, characterized in that: It includes a front electrode (1), a front antireflection layer (2), a passivation layer (3), a p+ emitter (4), an N-type monocrystalline silicon wafer (5), an n+ back surface field (6), a back antireflection layer (7), and a back electrode (8); The n+ back surface field (6) is an amorphous silicon - microcrystalline silicon - polycrystalline silicon composite thin film layer, which is composed of an amorphous silicon layer (61), a microcrystalline silicon layer (62), and a polycrystalline silicon layer (63).

2. A method for fabricating the N-type PERT double-sided solar cell described in claim 1, comprising the following steps: Step 1: Texturing: Making the front and back surfaces both have pyramid structures; Step 2: Boron diffusion; Step 3: Cleaning and alkaline polishing; Step 4: Sequentially growing an intrinsic amorphous silicon thin film, a microcrystalline silicon thin film, and a polycrystalline silicon thin film by PECVD to form the n+ back surface field (6); Step 5: Depositing the passivation layer (3) on the front surface by ALD; Step 6: Depositing a front film by PECVD; Step 7: Depositing a back film by PECVD; Step 8: Printing and sintering; Step 9: Laser scanning treatment of the front and back electrodes.

3. The manufacturing method of the N-type PERT double-sided solar cell according to claim 2, characterized in that: In step 2, a p+ emitter (4) is formed on the front surface through boron diffusion, constituting a PN junction with the N-type monocrystalline silicon wafer (5); on the back surface, a back surface field is realized by doping a silicon thin film composite layer.

4. The manufacturing method of the N-type PERT double-sided solar cell according to claim 2, characterized in that: In step 4, using the PECVD process, an amorphous silicon layer (61) with a thickness of 2 - 5 nm, a microcrystalline silicon layer (62) with a thickness of 5 - 15 nm, and a polycrystalline silicon layer (63) with a thickness of 15 - 50 nm are sequentially deposited to form an amorphous silicon - microcrystalline silicon - polycrystalline silicon gradient structure thin film, constructing a composite back surface field structure with gradient crystallinity and doping concentration.

5. The manufacturing method of the N-type PERT double-sided solar cell according to claim 4, characterized in that: The amorphous silicon layer (61) is an intrinsic hydrogenated amorphous silicon thin film, and the concentration of the microcrystalline silicon layer (62) is 1 to 5×10 19 / cm 3 , and the concentration of the polycrystalline silicon layer (63) is 1 to 5×10 20 / cm 3 .

6. The manufacturing method of the N-type PERT double-sided solar cell according to claim 5, wherein: The PECVD process parameters are as follows: temperature 100 - 350 °C, radio frequency 13.56 - 60 MHz, radio frequency power density greater than 0.1 W / cm², deposition pressure 0.1 - 3 Torr, H2 / SiH4 flow ratio 2 - 90, PH3 volume ratio 1 - 4 vol%, deposition rate 0.1 - 8 nm / min.

7. The preparation method of the N-type PERT double-sided solar cell according to claim 6, characterized in that: The PECVD process parameters for depositing the amorphous silicon layer (61) are: temperature 100 - 180 °C, radio frequency 13.56 MHz, radio frequency power density 0.1 - 0.3 W / cm², deposition pressure 0.1 - 1 Torr, H2 / SiH4 flow ratio 2 - 5, deposition rate 0.1 - 0.5 nm / min; The PECVD process parameters for depositing the microcrystalline silicon layer (62) are: temperature 180 - 250 °C, radio frequency 13.56 - 27.12 MHz, radio frequency power density 0.5 - 1 W / cm², deposition pressure 1 - 3 Torr, H2 / SiH4 flow ratio 20 - 30, PH3 volume ratio 1 - 2 vol%, deposition rate 0.5 - 4 nm / min; The PECVD process parameters for depositing the polycrystalline silicon layer (63) are: temperature 250 - 350 °C, radio frequency 40 - 60 MHz, radio frequency power density greater than 2 W / cm², deposition pressure 0.5 - 1.5 Torr, H2 / SiH4 flow ratio 50 - 90, PH3 volume ratio 3 - 4 vol%, deposition rate 1 - 8 nm / min.

8. The manufacturing method of the N-type PERT double-sided solar cell according to claim 2, characterized in that: In step 6, the front film is deposited by PECVD to form the front anti-reflection layer (2); in step 7, the back film is deposited by PECVD to form the back anti-reflection layer (7).

9. The manufacturing method of the N-type PERT double-sided solar cell according to claim 2, characterized in that: In step 8, the printing process specifically involves printing silver paste on the front and back of the cell to form the front electrode (1) and the back electrode (8); the sintering process specifically involves sintering to form an ohmic contact between the front silver paste or silver-aluminum paste and the front surface of the silicon wafer, and an ohmic contact between the back silver paste and the back silver film composite layer, and removing the organic binder.

10. The preparation method of the N-type PERT double-sided solar cell according to claim 2, characterized in that: In step 9, both the front electrode (1) and the back electrode (8) are processed by laser scanning to improve the silver-silicon metal-semiconductor contact, and a reverse bias is applied during laser irradiation; the back electrode (8) is in direct ohmic contact with the microcrystalline silicon layer (62) or the polycrystalline silicon layer (63), and avoids contacting the body of the N-type monocrystalline silicon wafer (5).

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