Solar cell and photovoltaic module

Abstract

The present application provides a solar cell and a photovoltaic module. The solar cell comprises: a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, the first surface comprises an electrode collection region, the electrode collection region comprises majority carrier regions and minority carrier regions alternately arranged at intervals in a first direction, and in the first direction, collection regions located at two opposite edges of a silicon wafer are both majority carrier regions; first doped semiconductor portions arranged in the majority carrier regions; and second doped semiconductor portions arranged in the minority carrier regions, wherein the second doped semiconductor portions have a conductivity type opposite to that of the first doped semiconductor portions. By means of the majority carrier regions arranged at the edge of the first surface, i.e., back surface field regions, which have the same conductivity type as the semiconductor substrate, there is no need to remove wrap-around plating of a passivated contact conductive structure or perform additional insulation processes, and a resistance-limiting effect caused by an emitter is avoided.

Description

Solar cell and photovoltaic module

[0001] Cross-reference to related applications

[0002] This application claims priority to and the benefit of Chinese Patent Application No. 202422360761.X, filed September 27, 2024, the contents of which are incorporated herein in their entirety by this reference. TECHNICAL FIELD

[0003] The present application relates to the field of photovoltaic technology, in particular to a solar cell and a photovoltaic module. BACKGROUND

[0004] In existing solar cells, the positive electrode and the negative electrode can be arranged on the back surface of the cell piece. When the light-receiving surface of the solar cell is irradiated by sunlight, the base of the solar cell generates hole-electron pairs. Under the action of the electric field in the P-N junction, the photo-generated holes flow to the P region, and the photo-generated electrons flow to the N region to form an electric current when the circuit is connected. The semiconductor base can be N-type doped or P-type doped. The carrier collection region with the same doping type as the semiconductor base is the majority carrier collection region, i.e., the back surface field; and the carrier collection region with the opposite doping type to the semiconductor base is the minority carrier collection region, i.e., the emitter. In the manufacturing process of the cell, there are often some defects in the edge region of the silicon wafer, such as not conducive to the collection of edge carriers, which will adversely affect the performance of the cell.

[0005] SUMMARY

[0006] Compared with traditional bifacial solar cells, if the emitter and the back surface field of the solar cell are arranged at intervals on the back surface of the cell, the staggered distribution of the emitter and the back surface field affects the collection of carriers. It is necessary to insulate and isolate the emitter and the back surface field, especially at the edge of the semiconductor base, and the influence of the edge plating on the carrier collection also needs to be considered. If the edge of the semiconductor base is set as the emitter, i.e., opposite to the doping type of the semiconductor base, a complex process such as de-plating needs to be introduced to form an insulating structure to prevent edge leakage and cause a decrease in conversion efficiency, and it will also be affected by the emitter resistance limitation effect. If a transparent conductive oxide or the like is needed to form a transparent conductive layer to collect carriers, the edge plating of the transparent conductive layer will also cause short circuit and leakage, and a hybrid process is also needed to form an insulating structure to prevent edge leakage and cause a decrease in conversion efficiency.

[0007] Therefore, how to improve the carrier collection efficiency of the edge part of the back surface of the solar cell has become a technical problem to be solved.

[0008] To solve the above and other aspects of the prior art, at least one technical problem, the present application provides a solar cell and a photovoltaic module, the electrode collection area arranged adjacent to the edge of the semiconductor substrate of the first surface is a multi-sub area, and the structure is arranged to simplify the manufacturing process and cost of the cell.

[0009] Embodiments of the present application provide a solar cell, comprising a semiconductor substrate, the semiconductor substrate having opposite first and second surfaces, the first surface comprising an electrode collection area; the electrode collection area comprising multi-sub areas and few-sub areas alternately and spacedly distributed along a first direction; along the first direction, the electrode collection area near the two opposite edges of the silicon wafer is a multi-sub area; a first doped semiconductor part is arranged in the multi-sub area; a second doped semiconductor part is arranged in the few-sub area, and the second doped semiconductor part is opposite in conductive type to the first doped semiconductor part.

[0010] According to embodiments of the present application, the conductive type of the first doped semiconductor part is N-type, and the conductive type of the second doped semiconductor part is P-type.

[0011] According to embodiments of the present application, the first doped semiconductor part comprises a doped polysilicon layer. The second doped semiconductor part comprises one or more of doped polysilicon, doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0012] According to embodiments of the present application, in the first surface, the region between the multi-sub area and the few-sub area along the first direction is a spacing area; the first doped semiconductor part is also arranged on the spacing area; the second doped semiconductor part also extends to cover the part of the first doped semiconductor part corresponding to the spacing area; in the spacing area, the second doped semiconductor part and the first doped semiconductor part are spaced along the thickness direction of the semiconductor substrate.

[0013] According to embodiments of the present application, the first doped semiconductor part is covered with a first transparent conductive layer, and the second doped semiconductor part is covered with a second transparent conductive layer, and the first transparent conductive layer and the second transparent conductive layer are insulated and disconnected in the spacing area. That is, the insulation of the multi-sub area and the few-sub area is formed by the disconnection of the transparent conductive layer to prevent electric leakage.

[0014] According to the embodiments of the present application, the first transparent conductive layer also extends to cover at least part of the edge side of the semiconductor substrate. When the electrode collection region of the first surface adjacent to the edge of the semiconductor substrate is a multi-carrier region, there is no need to consider that the first transparent conductive layer will connect the semiconductor substrate of the opposite doping type and the electrode collection region adjacent to the edge of the semiconductor substrate to form a leakage channel, resulting in a decrease in conversion efficiency. In the prior art, it is usually necessary to remove the wrap plating of the transparent conductive layer on the edge side of the semiconductor substrate, or insert an insulating layer between the transparent conductive layer and the edge side of the semiconductor substrate, or use a precision template to prevent wrap plating. The prior art will complicate the process and increase the manufacturing cost. However, the embodiments of the present application can simplify the process and reduce the process cost, and at the same time, under the coverage of the transparent conductive layer, the first doped semiconductor part under the transparent conductive layer in the edge region can be prevented from being excessively etched, thereby reducing the carrier collection capability of the edge region.

[0015] According to the embodiments of the present application, the first surface further includes a non-electrode collection region at the edge of the silicon wafer, and the electrode collection region is located inside the non-electrode collection region. Preferably, in the first direction, the width of the non-electrode collection region is less than 1000 μm, and the width of the non-electrode collection region is less than the width of the minority carrier region.

[0016] According to the embodiments of the present application, in the first surface, the non-electrode collection region is further located outside the electrode collection region along a second direction; and the second direction is different from the first direction.

[0017] According to the embodiments of the present application, the second direction is perpendicular to the first direction; and / or the width of the non-electrode collection region along the second direction is less than or equal to the width of the non-electrode collection region along the first direction.

[0018] According to the embodiments of the present application, a passivation layer is provided on the non-electrode collection region, and the passivation layer can be a single layer or a stack of two or more layers of different materials. The passivation layer is one or more of intrinsic amorphous silicon, silicon oxide, aluminum oxide or silicon nitride.

[0019] According to the embodiments of the present application, a third doped semiconductor part is further formed on the passivation layer, the third doped semiconductor part has the same conductivity type as the first doped semiconductor part, and the material of the third doped semiconductor part is the same as the material of the first doped semiconductor part.

[0020] According to the embodiments of the present application, the surface of the non-electrode collection region is a polished surface or a textured surface.

[0021] According to the embodiments of the present application, the surface of the minority carrier region is a textured surface.

[0022] The embodiments of the present application also provide a photovoltaic module comprising the above-mentioned solar cell.

[0023] According to the solar cell and photovoltaic module provided in the present application, the multi-carrier region, i.e. the back surface field region, provided at the edge of the first surface has the same conductive type as the semiconductor substrate, and no additional process is needed to remove the passivation contact conductive structure. In particular, when a transparent conductive layer is used, the risk of leakage caused by the transparent conductive layer wrapping around the semiconductor substrate edge and the emitter to form a conductive path is eliminated, thereby improving the photoelectric conversion efficiency. In addition, the back surface field can reduce the contact resistance and the difficulty of multi-carrier collection in the edge region, thereby improving the fill factor and the photoelectric conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1 is a longitudinal sectional view of a solar cell according to an illustrative embodiment of the present application, showing a hybrid solar cell;

[0025] FIG. 2 is a longitudinal sectional view of a solar cell according to another illustrative embodiment of the present application, showing a tunnel oxide passivation contact cell;

[0026] FIG. 3 is a schematic diagram showing the distribution of non-electrode collection regions and electrode collection regions on the first surface according to an illustrative embodiment of the present application;

[0027] FIG. 4 is a schematic diagram showing the distribution of non-electrode collection regions and electrode collection regions on the first surface according to another illustrative embodiment of the present application.

[0028] In the drawings, the following reference signs have the following meanings: 10, semiconductor substrate; 12, first interface passivation layer; 12-1, second interface passivation layer; 13, first transparent conductive layer; 14, first electrode; 15, first doped semiconductor portion; 16, second doped semiconductor portion; 17, insulating layer; 18, second electrode; 19, second transparent conductive layer; 20, electrode collection region; 21, non-electrode collection region; 22, spacing region; 23, multi-carrier region; 24, minority carrier region; 30, semiconductor substrate edge. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0030] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The terms "comprise", "contain", and the like as used herein indicate the presence of the stated features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0031] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the use of any terms herein should not be interpreted to imply any limitation on the scope of the disclosure unless otherwise defined. It should also be noted that the use of "a" or "an" or "the" or "at least one" preceding an element or intervention is intended to be equivalent to inclusion of the element or intervention by "at least one" preceding the element in a claim or specification, unless otherwise restricted or limited by context.

[0032] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should be generally interpreted that the meaning of the expression is at least one of A, B, and C, etc. For example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc. In the case of using expressions similar to "at least one of A, B, or C, etc.", it should be generally interpreted that the meaning of the expression is at least one of A, B, and C, etc. For example, "a system having at least one of A, B, or C" should include but not be limited to a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.

[0033] The positive electrode and the negative electrode of the solar cell provided by the present application are arranged on the back surface of the cell sheet, so as to reduce the coverage area of the metal electrode on the light-receiving surface of the cell sheet, and have a higher energy conversion efficiency. The minority carrier region and the majority carrier region of the solar cell provided by the present application are formed on the back surface of the cell sheet in a spaced manner, and a hole-electron pair is formed on the absorption layer of the cell sheet when sunlight is incident on the light-receiving surface of the cell sheet.

[0034] Taking a cell sheet with an N-type silicon wafer as a semiconductor substrate as an example, electrons are majority carriers and holes are minority carriers. Correspondingly, the P region is used as a minority carrier region for collecting minority carriers, i.e. holes; and the N region is used as a majority carrier region for collecting majority carriers, i.e. electrons, so as to generate an electric current after the circuit is turned on.

[0035] Based on the above characteristics, the solar cell provided by the present application has more complex drift motion and diffusion motion compared with a conventional double-sided cell. The electron-hole pair not only transmits in the longitudinal direction (i.e. the thickness direction of the solar cell), but also undergoes a lateral transmission process (i.e. the width direction of the solar cell). Therefore, the holes located in the edge portion on the back surface side are prone to carrier recombination in the majority carrier region, which leads to a low minority carrier collection efficiency of the edge portion on the back surface side, and is not conducive to improving the working efficiency of the solar cell.

[0036] Therefore, how to improve the carrier region collection efficiency of the edge portion on the back surface side of the solar cell has become a technical problem to be solved.

[0037] Figure 1 is a longitudinal sectional view of a solar cell according to an illustrative embodiment of the present application, showing a hybrid solar cell.

[0038] According to the solar cell provided by the present application, as shown in Figure 1, it comprises a semiconductor substrate 10, a first doped semiconductor portion 15, and a second doped semiconductor portion 16. The semiconductor substrate 10 has opposite first and second faces, and the first face comprises an electrode collection region 20. The electrode collection region 20 comprises a plurality of majority carrier regions 23 and minority carrier regions 24 alternately and spacedly arranged along a first direction. Along the first direction, the majority carrier region 23 located at the most edge is closer to the semiconductor substrate edge 30 than the minority carrier region 24 located at the most edge. The first doped semiconductor portion 15 is arranged in the majority carrier regions 23. The second doped semiconductor portion 16 is arranged in the minority carrier regions 24, and the second doped semiconductor portion 16 has a conductive type opposite to that of the first doped semiconductor portion 15.

[0039] The electrode collection region 20 refers to the structure of the first doped semiconductor portion 15 and the second doped semiconductor portion 16 arranged on the electrode collection region 20 and having conductive properties, which needs to be electrically connected with an interconnection structure such as a conductive electrode, electrode mesh, or solder strip, etc. to lead out the majority carriers (may be referred to as majority carriers) or minority carriers (may be referred to as minority carriers) collected by itself, and is beneficial to form a photoelectric current. The first doped semiconductor portion 15 arranged in the majority carrier regions 23 is used as a back surface field (BSF) of the solar cell, and the second doped semiconductor portion 16 arranged in the minority carrier regions 24 is used as an emitter of the solar cell.

[0040] In such an embodiment, the majority carrier regions 23 are located at the edge of the semiconductor substrate 10, and the first doped semiconductor portion 15 arranged in the majority carrier regions has the same conductive type as the semiconductor substrate, and thus it is not necessary to remove the passivation contact conductive structure by plating or additional processes for insulation. The first transparent conductive layer 13 covering the edge of the semiconductor substrate also does not need to be additionally broken and insulated in the edge region, which reduces the complexity of the process. At the same time, the first transparent conductive layer 13 can effectively protect the first doped semiconductor portion 15, and increase light absorption by using the difference in refractive index between the first transparent conductive layer 13, the first doped semiconductor portion 15, and the semiconductor substrate 10.

[0041] In an illustrative embodiment, the first doped semiconductor portion 15 is N-type doped, and the second doped semiconductor portion 16 is P-type doped.

[0042] In another illustrative embodiment, the first doped semiconductor portion 15 is P-type doped, and the second doped semiconductor portion 16 is N-type doped.

[0043] In such an embodiment, the semiconductor substrate 10 is, for example, a silicon substrate, the first doped semiconductor portion 15 is an N-type doped polysilicon layer (i.e. n-poly), and the second doped semiconductor portion 16 is a P-type doped amorphous silicon. The preparation process is as follows: a first interface passivation layer 12 and a first doped semiconductor portion composed of a polysilicon material are formed on the first surface (back surface) of the silicon substrate; the silicon substrate is exposed by removing part of the polysilicon and the first interface passivation layer 12 through wet etching to form a minority carrier region; the edge of the silicon substrate is covered by the first doped semiconductor portion 15 of the N-type doped polysilicon layer, which can better protect the underlying first interface passivation layer 12 and achieve good passivation effect at the edge of the silicon substrate; a second interface passivation layer 12-1 is formed on the exposed silicon substrate, which is intrinsic amorphous silicon; and a P-type doped amorphous silicon layer, a P-type doped microcrystalline silicon layer, or a P-type doped nanocrystalline silicon layer is formed on the intrinsic amorphous silicon. The exposed silicon substrate is a textured surface or a polished surface.

[0044] According to an embodiment of the present application, as shown in FIG. 1, in the first surface, the region between the majority carrier region 23 and the minority carrier region 24 in the first direction is a spacing region 22. The first doped semiconductor portion 15 is also disposed on the spacing region 22. The second doped semiconductor portion 16 further extends to cover the portion of the first doped semiconductor portion 15 corresponding to the spacing region 22; in the spacing region 22, the second doped semiconductor portion 16 and the first doped semiconductor portion 15 are spaced apart along the thickness direction of the semiconductor substrate 10.

[0045] In an illustrative embodiment, as shown in FIG. 1, an insulating layer 17 is further disposed between the first doped semiconductor portion 15 and the second doped semiconductor portion 16, which extends in a direction parallel to the first surface to space apart the first doped semiconductor portion 15 and the second doped semiconductor portion 16 along the thickness direction of the semiconductor substrate 10 (i.e. the up-down direction as shown in FIG. 1).

[0046] In an illustrative embodiment, as shown in FIG. 1, the first doped semiconductor portion 15 is further disposed on the spacing region 22. Further, the second doped semiconductor portion 16 further extends to cover the portion of the first doped semiconductor portion 15 corresponding to the spacing region 22 to form a PN overlapping spacing region 22.

[0047] Such a configuration can improve the insulation performance between the first doped semiconductor portion 15 and the second doped semiconductor portion 16, prevent electric leakage, and improve the photoelectric conversion efficiency.

[0048] In one illustrative embodiment, as shown in FIG. 1, the first and second transparent conductive layers 13 and 19 are respectively disposed over the first and second doped semiconductor portions 15 and 16, and are insulated from each other at the spacing region 22. The first and second electrodes 14 and 18 are respectively formed on the first and second transparent conductive layers 13 and 19. The first transparent conductive layer 13 on the first doped semiconductor portion 15 near the edge of the semiconductor substrate only needs to be insulated from the second transparent conductive layer 19 at the spacing region 22 between the first doped semiconductor portion 15 and the adjacent second doped semiconductor portion 16. The process difficulty required for insulating the transparent conductive layer at the edge of the semiconductor substrate is reduced. In addition, the first doped semiconductor portion 15 is of the same doping type as the semiconductor substrate, and no additional process is required to remove the transparent conductive layer from around the edge of the semiconductor substrate or to break the transparent conductive layer at the edge of the semiconductor substrate to prevent current leakage. Under the coverage of the transparent conductive layer, the first doped semiconductor portion under the transparent conductive layer at the edge region can be prevented from being over-etched, which can otherwise cause a decrease in the edge carrier collection capability.

[0049] FIG. 2 is a longitudinal sectional view of a solar cell of another illustrative embodiment of the present application, showing a tunnel oxide passivated contact (TOPCon) solar cell. The first doped semiconductor portion 15 is an N-type doped polysilicon layer (i.e., n-poly), and the second doped semiconductor portion 16 is a P-type doped polysilicon layer (i.e., p-poly). The first electrode 14 is formed on the first doped semiconductor portion 15, and the second electrode 18 is formed on the second doped semiconductor portion 16. The spacing region 22 is formed between the first and second doped semiconductor portions 15 and 16. The first doped semiconductor portion 15 at the edge of the semiconductor substrate forms a majority carrier region, and no additional process is required to remove the doped semiconductor layer of the opposite doping type that can cause a risk of current leakage. The first transparent conductive layer 13 also extends to cover at least part of the edge 30 of the semiconductor substrate.

[0050] For the embodiments of FIGS. 1 and 2, as shown in FIG. 3, a certain width of the first doped semiconductor portion 15 is removed in the first direction to form a non-electrode collection region 21. The electrode collection region 20 is disposed between the non-electrode collection regions 21 on both sides of the semiconductor substrate. The width of the non-electrode collection region 21 is less than 1000 μm, and the width of the non-electrode collection region 21 is less than the width of the minority carrier region 24. Removing a certain width of the first doped semiconductor portion prevents the edge region from being over-etched, which can otherwise cause uneven thickness and doping concentration distribution of the first doped semiconductor portion.

[0051] In one illustrative embodiment, the width of the non-electrode collection region 21 is configured to be less than the width of the minority carrier region 24. Further, the width of the majority carrier region 23 can also be configured to be less than the width of the minority carrier region 24.

[0052] In such an embodiment, the width of the non-electrode collection region 21 is configured to be smaller than the width of the minority carrier region 24, which is advantageous to reduce the proportion of the non-electrode collection region on the side of the first surface (e.g. the upper side in FIG. 3) where the majority carriers cannot be extracted, so that the proportion of the electrode collection region 20 in the first surface is larger, and the collection efficiency of the solar cell is improved.

[0053] FIG. 3 is a schematic diagram of the distribution of the non-electrode collection region and the electrode collection region in the first surface according to an embodiment of the present application.

[0054] According to an embodiment of the present application, as shown in FIG. 3, the first surface further includes a non-electrode collection region 21 at the edge of the silicon wafer, and the electrode collection region 20 is located inside the non-electrode collection region 21.

[0055] In an illustrative embodiment, as shown in FIG. 3, in the first surface, the non-electrode collection region 21 is arranged on the outside of the electrode collection region 20 only along a first direction (e.g. the up-down direction in FIG. 3). In detail, the electrode collection region 20 is continuously distributed between two non-electrode collection regions 21. In this way, the first doped semiconductor part 15 and the second doped semiconductor part 16 on both sides of the first surface along the extension direction of the non-electrode collection region 21 do not need to be selectively etched in the manufacturing process, which is advantageous to reduce the etching amount. It should be understood that embodiments of the present application are not limited thereto.

[0056] For example, the first direction described above can be any direction parallel to the first surface. Preferably, in the case where the shape of the first surface of the semiconductor substrate 10 is a rectangle or a rectangle with chamfered corners, the first direction can be parallel to the extension direction of any side length of the non-chamfered corner of the rectangle.

[0057] FIG. 4 is a schematic diagram of the distribution of the non-electrode collection region and the electrode collection region in the first surface according to another illustrative embodiment of the present application.

[0058] According to an embodiment of the present application, as shown in FIG. 4, in the first surface, the non-electrode collection region 21 is further arranged on the outside of the electrode collection region 20 along a second direction; and the second direction is different from the first direction.

[0059] According to an embodiment of the present application, as shown in FIG. 4, the second direction is perpendicular to the first direction. And / or, the width of the non-electrode collection region 21 along the second direction is less than or equal to the width of the non-electrode collection region 21 along the first direction.

[0060] In an exemplary embodiment, as shown in FIG. 4, in the first surface, the non-electrode collecting region 21 is further disposed outside the electrode collecting region 20 along a second direction (e.g., the left-right direction shown in FIG. 4). The second direction is different from the first direction. In detail, the edge passivation layer is further disposed outside the electrode collecting region 20 along the second direction, which can reduce the unevenness of the thickness and the doping concentration distribution of the alternately arranged first doped semiconductor part and the second doped semiconductor part caused by over-etching of the edge region along the second direction. The width of the non-electrode collecting region 21 along the first direction and along the second direction is not specifically limited here.

[0061] In the first surface, the non-electrode collecting region 21 is further disposed outside the electrode collecting region 20 along a second direction (e.g., the left-right direction shown in FIG. 4). The second direction is different from the first direction. In detail, the edge passivation layer is further disposed outside the electrode collecting region 20 along the second direction, which is conducive to improving the collection efficiency of the minority carriers of the edge part of the semiconductor substrate 10 along the second direction, and further inhibiting the carrier recombination of the edge part of the semiconductor substrate 10. Moreover, since the edge passivation layer has a higher field passivation effect on the non-electrode collecting region 21, when the non-electrode collecting region 21 is further disposed outside the electrode collecting region 20 along the second direction, the passivation effect of the edge part along the second direction in the first surface can also be improved, the number of defects of the non-electrode collecting region 21 located at the edge of the first surface can be reduced, and the working efficiency of the solar cell can be further improved. The above-mentioned second direction can be any direction parallel to the first surface and different from the first direction.

[0062] According to the embodiments of the present application, the edge passivation layer disposed on the non-electrode collecting region 21 can be one layer or a stack of two or more layers composed of different materials. The passivation layer can be one or more of intrinsic amorphous silicon, silicon oxide, aluminum oxide, or silicon nitride.

[0063] According to the embodiments of the present application, the surface of the non-electrode collecting region 21 is a polished surface or a textured surface, as shown in FIG. 1 and FIG. 2.

[0064] According to the embodiments of the present application, the surface of the non-electrode collecting region 21 is a polished surface or a textured surface, as shown in FIG. 1 and FIG. 2.

[0065] In an exemplary embodiment, the surface of the non-electrode collecting region 21 is a polished surface, and the surface of the minority carrier region 24 is a textured surface, as shown in FIG. 1 and FIG. 2.

[0066] In such an embodiment, compared with the textured surface, the surface of the non-electrode collecting region 21 is relatively flat when the surface of the non-electrode collecting region 21 is set to be a polished surface. Compared with the textured surface, the number of defect recombination centers of the polished surface is smaller, and the carrier recombination rate of the edge part of the first surface can be further reduced.

[0067] Further, the minority carrier region 24 is provided with a rough surface, and the deposition film thickness of the second doped semiconductor portion 16 on the rough surface is relatively small compared with the polished surface, so that the thickness of the edge passivation layer provided in the non-electrode collecting region 21 can be greater than the thickness of the second doped semiconductor portion 16 provided in the minority carrier region, so as to ensure that the non-electrode collecting region 21 has a higher passivation effect. In addition, the minority carrier region 24 provided with a rough surface has a larger specific surface area, which is conducive to making the side of the second doped semiconductor portion 16 formed on the minority carrier region 24 away from the semiconductor substrate 10 also have a larger specific surface area, which is conducive to increasing the contact area between the second doped semiconductor portion 16 and the corresponding conductive electrode, and improving the contact performance therebetween.

[0068] Based on the similar concept as the above-mentioned solar cell, the application further provides a photovoltaic module, not shown in the drawings, which comprises the above-mentioned solar cell.

[0069] It should be further noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only with reference to the drawings, and are not intended to limit the protection scope of the application. Throughout the drawings, the same elements are represented by the same or similar reference numerals. When it is possible to cause confusion in the understanding of the application, the conventional structures or configurations will be omitted.

[0070] The above describes the embodiments of the application. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the application is defined by the appended claims and their equivalents. Without departing from the scope of the application, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the application.

Claims

1. A solar cell, characterized by, Comprising: a semiconductor substrate (10) having opposite first and second faces, the first face comprising an electrode collection region (20); the electrode collection region (20) comprising a plurality of majority regions (23) and minority regions (24) alternately and spacedly distributed along a first direction; along the first direction, the electrode collection region near both opposite semiconductor substrate edges (30) is a majority region; a first doped semiconductor portion (15) disposed on the majority regions (23); a second doped semiconductor portion (16) disposed on the minority regions (24), the second doped semiconductor portion (16) being opposite in conductivity type to the first doped semiconductor portion (15).

2. The solar cell according to claim 1, characterized in that, The first doped semiconductor portion (15) is N-type, and the second doped semiconductor portion (16) is P-type.

3. The solar cell according to claim 2, characterized in that, The first doped semiconductor portion (15) comprises a doped polysilicon layer; the second doped semiconductor portion (16) comprises at least one of a doped polysilicon, a doped amorphous silicon, a doped microcrystalline silicon, and a doped nanocrystalline silicon.

4. The solar cell of claim 1, wherein In the first face, a region between the majority regions (23) and the minority regions (24) along the first direction is a spacing region (22); The first doped semiconductor portion (15) is further disposed on the spacing region (22); The second doped semiconductor portion (16) further extends to cover a portion of the first doped semiconductor portion (15) corresponding to the spacing region (22); in the spacing region (22), the second doped semiconductor portion (16) and the first doped semiconductor portion (15) are spaced apart along the thickness direction of the semiconductor substrate (10).

5. The solar cell according to claim 4, characterized in that, The first doped semiconductor portion (15) is covered with a first transparent conductive layer (13), and the second doped semiconductor portion (16) is covered with a second transparent conductive layer (19); the first transparent conductive layer (13) and the second transparent conductive layer (19) are insulated and disconnected in the spacing region (22).

6. The solar cell according to claim 5, characterized in that, The first transparent conductive layer (13) further extends to cover at least part of the semiconductor substrate edge (30) side.

7. The solar cell of claim 1, wherein The first face further comprises a non-electrode collection region (21) at the semiconductor substrate edge (30), and the electrode collection region (20) is located inside the non-electrode collection region (21).

8. The solar cell of claim 7, wherein, Along the first direction, the width of the non-electrode collection region (21) is less than 1000 μm, and the width of the non-electrode collection region (21) is less than the width of the minority region (24).

9. The solar cell of claim 7, wherein, In the first face, the non-electrode collection region (21) is further disposed outside the electrode collection region (20) along a second direction; the second direction is different from the first direction.

10. The solar cell of claim 9, wherein, The second direction is perpendicular to the first direction. And / or, the width of the non-electrode collection region (21) along the second direction is less than or equal to the width of the non-electrode collection region (21) along the first direction.

11. The solar cell of claim 7, wherein, A passivation layer is disposed on the non-electrode collection region (21), the passivation layer being at least one of intrinsic amorphous silicon, silicon oxide, aluminum oxide, or silicon nitride.

12. A photovoltaic module, characterized by A solar cell comprising any one of claims 1 to 11.

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