Display module, driving method thereof and display device

Abstract

The invention discloses a display module, a driving method thereof and a display device. The display module comprises an initial signal line, a first control signal line and a gate driving circuit, the initial signal line is used for providing an initial signal; the first control signal line is used for providing a stage transmission stop signal; the gate drive circuit comprises a plurality of shift register circuits in cascade connection, the shift register circuits are connected with a first control signal line, and the first shift register circuit of the plurality of shift register circuits is connected with an initial signal line; the shift register circuit is used for generating a scanning signal under the condition that the initial signal is received or the scanning signal output by the previous shift register circuit is received; and the shift register circuit is also used for stopping generating the scanning signal under the condition that the cascade transmission stop signal is received. According to the invention, the display panel can adopt different refresh rates in different display areas, so that the power consumption of the display panel is reduced.

Description

Technical Field

[0001] The present invention relates to the field of displays, and in particular to a display module, a driving method thereof, and a display device. Background Art

[0002] In some application scenarios, the display panel needs to display different pictures in different zones. For example, when a user watches a video, only a part of the upper area of the display panel is used to display the video picture, while other areas are used to display function icons or display buttons. Since the video picture requires a relatively high refresh rate during display, the function icons and buttons generally do not require a high refresh rate. If the entire display panel maintains a high refresh rate according to the refresh rate requirement of the video picture, it will cause an increase in the power consumption of the display panel. Summary of the Invention

[0003] The present invention provides a display module, a driving method thereof, and a display device, which can achieve different refresh rates in different display areas of the display panel, thereby reducing the power consumption of the display panel.

[0004] In a first aspect, the present invention provides a display module, including: a start signal line for providing a start signal; a first control signal line for providing a cascade stop signal; a gate driving circuit including a plurality of cascaded shift register circuits, the shift register circuit being connected to the first control signal line, and the first shift register circuit of the plurality of shift register circuits being connected to the start signal line; the shift register circuit is configured to generate a scan signal when receiving the start signal or the scan signal output by the previous shift register circuit; the shift register circuit is further configured to stop generating the scan signal when receiving the cascade stop signal.

[0005] In a second aspect, the present invention further provides a display device including the display module of the present invention.

[0006] In a third aspect, the present invention further provides a driving method for a display module, which is applied to the display module of the present invention. The display module includes a first display area and a second display area, and a plurality of shift register circuits corresponding to the first display area and the second display area are cascaded in sequence. The method includes: in a first display mode, in a first display frame and a second display frame, providing a start signal to a start signal line to enable each shift register circuit in the first display area and the second display area to sequentially generate a scan signal through cascading transmission; in a second display mode, in the first display frame and the second display frame, providing a start signal to the start signal line, and when the first shift register circuit in the second display area receives the scan signal output by the previous shift register circuit in the second display frame, providing a cascading stop signal to a first control signal line; wherein, the first display mode is a mode in which the display module displays at a first display frequency; the second display mode is a mode in which the display module displays at a second display frequency. In a fourth aspect, the present invention further provides a driving method for a display module, which is applied to the display module of the present invention. The display module includes a first display area and a second display area, and a plurality of shift register circuits corresponding to the first display area and the second display area are cascaded in sequence. In a third display mode, in the first display frame and the second display frame, providing a start signal to the start signal line to enable each shift register circuit in the first display area and the second display area to sequentially generate a scan signal through cascading transmission; in a fourth display mode, in the first display frame and the second display frame, providing a start signal to the start signal line, and when the first shift register circuit in the second display area receives the scan signal output by the previous shift register circuit in the second display frame, providing a fixed level signal to a clock signal line; wherein, the third display mode is a mode in which the display module displays at a first display frequency; the fourth display mode is a mode in which the display module displays at a second display frequency.

[0007] Compared with the prior art, the display module, its driving method, and the display device provided by the present invention at least achieve the following beneficial effects:

[0008] The display module provided by the present invention includes: a start signal line for providing a start signal; a first control signal line for providing a cascade stop signal; a gate driving circuit including a plurality of cascaded shift register circuits, the shift register circuits being connected to the first control signal line, and the first shift register circuit of the plurality of shift register circuits being connected to the start signal line; the shift register circuit is configured to generate a scan signal when receiving the start signal or the scan signal output by the previous shift register circuit; the shift register circuit is further configured to stop generating the scan signal when receiving the cascade stop signal. According to an embodiment of the present invention, the shift register circuit is connected to the first control signal line, and the first control signal line is used to provide the cascade stop signal to the shift register circuit, so that the first shift register circuit of a certain display area stops generating the scan signal, thereby enabling this display area to stop refreshing within one display frame. Therefore, in the present invention, in some display frames, the entire display panel can be normally refreshed, while in other display frames, a partial display area of the display panel is normally refreshed, and another partial display area of the display panel stops refreshing according to the cascade stop signal provided by the first control signal line, so that the refresh rate of this partial display area is reduced in multiple display frames. Thus, the present invention realizes different refresh rates for different display areas with different display requirements during the entire display process of the display module, enabling the display area with a higher refresh rate requirement to be normally refreshed in all display frames, while the display area with a lower refresh rate requirement stops refreshing in some display frames, thereby reducing the signal output of this area and further reducing the power consumption of the display panel. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0010] Figure 1 Showing a schematic structural diagram of a display module provided by the present invention;

[0011] Figure 2 Showing a schematic structural diagram of another display module provided by the present invention;

[0012] Figure 3 Showing a schematic diagram of the display situation of a display module provided by the present invention;

[0013] Figure 4 Showing a circuit diagram of a shift register circuit provided by the present invention;

[0014] Figure 5Shows the control timing diagram of a display module provided by the present invention;

[0015] Figure 6 Shows the control timing diagram of another display module provided by the present invention;

[0016] Figure 7 Shows the structural schematic diagram of another display module provided by the present invention;

[0017] Figure 8 Shows the schematic diagram of the display situation of another display module provided by the present invention;

[0018] Figure 9 Shows the structural schematic diagram of another display module provided by the present invention;

[0019] Figure 10 Shows the structural schematic diagram of another display module provided by the present invention;

[0020] Figure 11 Shows the structural schematic diagram of another display module provided by the present invention;

[0021] Figure 12 Shows the structural schematic diagram of a display device provided by the present invention;

[0022] Figure 13 Shows the flow schematic diagram of a driving method of a display module provided by the present invention;

[0023] Figure 14 Shows the flow schematic diagram of another driving method of a display module provided by the present invention. Detailed Description of the Invention

[0024] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present invention.

[0025] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0026] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or this region will be "below" or "beneath" the other layer or another region.

[0027] It should be understood that the term "and / or" used in this article is only a relational term describing the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0028] In the embodiments of the present invention, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components.

[0029] In the embodiments of the present invention, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not an actual circuit unit.

[0030] Without departing from the spirit or scope of the present invention, various modifications and variations can be made to the present invention, which are obvious to those skilled in the art. Therefore, the present invention is intended to cover the modifications and variations of the present invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention can be combined with each other without contradiction.

[0031] In some application scenarios, there are multiple display situations for a display panel. For example, when a user watches a video, only a partial area above the display panel is used to display the video picture, while other areas are used to display the video comment area, function icons, or buttons. Generally speaking, users have a relatively high refresh rate requirement for the video picture, while the display areas such as the video comment area, function icons, and buttons often do not require a high refresh rate. Therefore, if the entire display panel maintains a high refresh frequency according to the refresh rate requirement of the video picture, it will cause the display areas with low refresh rate requirements to also adopt a high refresh rate, resulting in an increase in the power consumption of the display panel.

[0032] Based on the above technical problems, embodiments of the present invention provide a display module, a driving method thereof, and a display device. The following will describe each embodiment of the present invention with reference to the accompanying drawings.

[0033] Figure 1 A schematic structural diagram of a display module provided by the present invention is shown in Figure 1 As shown, the display module includes: a start signal line 10, a first control signal line 20, and a gate driving circuit 30.

[0034] The start signal line 10 is used to provide a start signal; the first control signal line 20 is used to provide a stage transfer stop signal;

[0035] The gate driving circuit 30 includes m cascaded shift register circuits 31. The m shift register circuits 31 are respectively labeled as 31_1, 31_2…31_i-1, 31_i, 31_i+1…31_m, where i and m are positive integers greater than 1.

[0036] The shift register circuit 31 is connected to the first control signal line 20, and the first shift register circuit 31_1 of the m shift register circuits 31 is connected to the start signal line 10.

[0037] The shift register circuit 31_i is used to generate a scan signal when receiving the start signal or the scan signal output by the previous shift register circuit 31_i-1; the shift register circuit 31 is also used to stop generating the scan signal when receiving the stage transfer stop signal.

[0038] Exemplarily, the gate driving circuit 30 includes a plurality of cascaded shift register circuits 31. The display module can be arbitrarily divided into a plurality of display regions, and each display region correspondingly includes a part of the shift register circuits 31. When the first shift register circuit 31_1 of the display module receives a start signal, it generates a scan signal and outputs the scan signal to the corresponding scan signal line and the next shift register circuit 31_2. The next shift register circuit 31_2 continues to generate a scan signal to be transmitted downward according to the received scan signal until all the shift register circuits 31 complete the transmission of the scan signal, then a display frame is completed. The shift register circuit 31 is connected to the first control signal line 20, and the first control signal line 20 is used to provide a transmission stop signal to the i-th stage shift register circuit 31_i, so that the i-th stage shift register circuit 31_i stops generating the scan signal, thereby enabling the display regions corresponding to the i-th stage shift register circuit 31_i and the subsequent shift register circuits 31 to stop refreshing within a display frame. In the present invention, the number of shift register circuits 31 included in the second display region corresponding to each display frame may be the same or different. Therefore, the first shift register circuit 31_1 corresponding to the second display region in different display frames may be the same or different, so that there are a plurality of display regions during the multi-frame display process of the display panel, and the refresh rate of each display region is different. In the present invention, in some display frames, the entire display panel can be normally refreshed, while in another part of the display frames, part of the display regions of the display panel are normally refreshed, and another part of the display regions of the display panel stop refreshing according to the transmission stop signal provided by the first control signal line, so that the refresh rate of this part of the display regions is reduced in multiple display frames. Thus, the present invention realizes different refresh rates for different display regions with different display requirements during the entire display process of the display module, enables the display regions with higher refresh rate requirements to be normally refreshed in all display frames, while the display regions with lower refresh rate requirements stop refreshing in some display frames, thereby reducing the signal output of this region and further reducing the power consumption of the display panel.

[0039] In some embodiments, Figure 2 A schematic structural diagram of another display module provided by the present invention is shown, as Figure 2 shown, the display module includes a first display region 41 and a second display region 42; a plurality of shift register circuits 31 corresponding to the first display region 41 and the second display region 42 are cascaded in sequence.

[0040] Exemplarily, the shift register circuit 31 is connected to the first control signal line 20. Therefore, the shift register circuit 31 can receive the stage transmission stop signal provided by the first control signal line 20, thereby stopping generating the scan signal. The first display area 41 and the second display area 42 respectively correspond to a part of the shift register circuits 31 in the display module. The first display area 41 is the area that is fixedly displayed by the display module during multiple-frame display. The second display area 42 is the area range corresponding to the shift register circuits 31 from the shift register circuit 31 that receives the stage transmission stop signal provided by the first control signal line 20 to the last shift register circuit 31_m during multiple-frame display. The second display area 42 alternately refreshes and stops refreshing during multiple-frame display, so that the refresh rate of the second display area 42 during display is different from that of the first display area 41. Therefore, the signal output provided by the display module to the second display area 42 is reduced, thereby reducing the power consumption of the display panel.

[0041] In the first display frame, for the shift register circuits 31_i corresponding to the first display area 41 and the second display area 42, when receiving the start signal or the scan signal of the previous shift register circuit 31_i-1, the scan signal is generated.

[0042] Specifically, the first shift register circuit 31_1 in the first display area 41 is electrically connected to the start signal line 10. The start signal line 10 provides a start signal to the first shift register circuit 31_1 in the first display area 41, enabling it to generate a scan signal according to the received start signal and provide the scan signal to the second shift register circuit 31_2. The second shift register circuit 31_2 will generate a scan signal according to the scan signal provided by the first shift register circuit 31_1 and provide the scan signal to the third shift register circuit 31_3, thereby enabling the first display area 41 to complete the stage transmission of the scan signal. The last shift register circuit 31_i corresponding to the first display area 41 is connected to the first shift register circuit 31_i+1 corresponding to the second display area 42. Therefore, in the first display frame, after the first display area 41 completes the stage transmission of the scan signal, it will transmit the scan signal to the first shift register circuit 31_i+1 corresponding to the second display area 42, enabling the multiple shift register circuits 31 corresponding to the second display area 42 to stage-transmit the scan signal, thereby realizing normal refreshing of both the first display area 41 and the second display area 42 within the first display frame.

[0043] In the second display frame, the first shift register circuit 31_i+1 corresponding to the second display area 42 stops generating the scan signal according to the received stage transmission stop signal when receiving the scan signal of the previous shift register circuit 31_i.

[0044] As an example, the last shift register circuit 31_i corresponding to the first display area 41 is connected to the first shift register circuit 31_i+1 corresponding to the second display area 42. Therefore, the last shift register circuit 31_i corresponding to the first display area 41 can provide a scan signal to the first shift register circuit 31_i+1 corresponding to the second display area 42. In the second display frame, the first control signal line 20 provides a stage transfer stop signal to the first shift register circuit 31_i+1 corresponding to the second display area 42. When the first shift register circuit 31_i+1 corresponding to the second display area 42 receives the scan signal, it stops generating the scan signal according to the received stage transfer stop signal, so that the multiple shift register circuits 31 corresponding to the second display area 42 stop generating the scan signal, thereby realizing normal refreshing of the first display area 41 in the second display frame and stopping refreshing of the second display area 42 in the second display frame. Thus, during the entire display process of the display module, the first display area 41 is normally refreshed in both display frames, while the second display area 42 is only normally refreshed in the first display frame and stops refreshing in the second display frame. Therefore, the refresh rate corresponding to the second display area 42 is half of the refresh rate of the first display area 41.

[0045] As another example, the first display area and the second display area are the same display area, that is, both the first display area and the second display area correspond to all the shift register circuits in the display module. Therefore, in the second display frame, the first shift register circuit of the second display area receives the start signal provided by the start signal line and also receives the stage transfer stop signal provided by the first control signal line. Thus, when the first shift register circuit corresponding to the second display area receives the start signal, it stops generating the scan signal according to the received stage transfer stop signal. Therefore, the second display area stops refreshing in the second display frame. For example, when the first display area is normally refreshed in the first display frame and the second display area is normally refreshed in the second display frame, the refresh rate of the display module during the entire display process is 120 Hz. If the second display area does not refresh in the second display frame, the refresh rate of the display module during the entire display process is adjusted to 60 Hz. Therefore, in some cases where a low refresh rate display is required, the present invention can reduce the refresh rate of the display module by controlling all the shift register circuits of the display module to stop transmitting signals in the second display frame, and the signal output provided by the display module is reduced in the second display frame, thereby reducing the power consumption of the display panel.

[0046] Figure 3 The figure shows a schematic diagram of the display situation of a display module provided by the present invention, as Figure 3As shown, for example, the display module includes a first display area 41 and a second display area 42 arranged in sequence. In the first display frame, the shift register circuits 31 corresponding to the first display area 41 and the second display area 42 both normally transmit scan signals, so that the first display area 41 and the second display area 42 are both normally refreshed. In the second display frame, the first display area 41 is normally refreshed. The first shift register circuit 31_i+1 corresponding to the second display area 42 receives the stage transmission stop signal provided by the first control signal line 20 and stops providing the scan signal to the next shift register circuit 31_i+2, so that no scan signal is transmitted to all the shift register circuits 31 in the second display area 42, and thus the second display area 42 stops refreshing. Therefore, the refresh rate of the second display area 42 is half of the refresh rate of the first display area 41. For example, the refresh rate of the first display area 41 is 120 Hz and the refresh rate of the second display area 42 is 60 Hz. The first display area 41 can be used to display navigation content or movies, and the second display area 42 can be used to display vehicle function icons. Thus, it is possible to implement display areas with two refresh rates in the display device.

[0047] In some embodiments, continue to refer to Figure 2 , the display module further includes a first clock signal line 51 and a second clock signal line 52. The first clock signal line 51 is connected to the first ends of the shift register circuits 31 of odd rows and to the second ends of the shift register circuits 31 of even rows. The second clock signal line 52 is connected to the second ends of the shift register circuits 31 of odd rows and to the first ends of the shift register circuits 31 of even rows. The first input terminal Gn-1 of the shift register circuit 31_i is connected to the start signal line 10 or the output terminal OUT of the previous shift register circuit 31_i-1. The signal reset terminal Gn+1 of the shift register circuit 31 is connected to the output terminal OUT of the next shift register circuit 31_i+1. The first clock signal line 51 is used to provide a first clock signal, and the second clock signal line 52 is used to provide a second clock signal. The first clock signal and the second clock signal are opposite in signal and have a phase difference of 180° at the same moment, that is, when the first clock signal is a high-level signal, the second clock signal is a low-level signal; when the first clock signal is a low-level signal, the second clock signal is a high-level signal.

[0048] Exemplarily, Figure 4 shows a circuit diagram of a shift register circuit provided by the present invention. As Figure 4 shown, the shift register circuit includes a first switching transistor Q1, a second switching transistor Q2, a third switching transistor Q3, a fourth switching transistor Q4, a fifth switching transistor Q5, a sixth switching transistor Q6, a seventh switching transistor Q7, an eighth switching transistor Q8, a ninth switching transistor Q9, a first capacitor C1, and a second capacitor C2.

[0049] The first end of the first switching transistor Q1 is electrically connected to the fourth clock signal line DIR1. The control end of the first switching transistor Q1 is electrically connected to the first input end Gn-1 of the shift register circuit. The second end of the first switching transistor Q1 is connected to the first node A.

[0050] The first end of the second switching transistor Q2 is connected to the first node A. The control end of the second switching transistor Q2 is electrically connected to the signal reset end Gn+1 of the shift register circuit. The second end of the second switching transistor Q2 is electrically connected to the fifth clock signal line DIR2.

[0051] The first end of the third switching transistor Q3 is connected to the first node A. The control end of the third switching transistor Q3 is electrically connected to the second node B. The second end of the third switching transistor Q3 is connected to the first voltage line.

[0052] The first end of the fourth switching transistor Q4 is connected to the second node B. The control end of the fourth switching transistor Q4 is connected to the first node A. The second end of the fourth switching transistor Q4 is connected to the first voltage line.

[0053] The first end of the fifth switching transistor Q5 is electrically connected to the first end of the shift register circuit. The control end of the fifth switching transistor Q5 is connected to the first node A. The second end of the fifth switching transistor Q5 is electrically connected to the output end OUT of the shift register circuit.

[0054] The first end of the sixth switching transistor Q6 is electrically connected to the output end OUT of the shift register circuit. The control end of the sixth switching transistor Q6 is connected to the second node B. The second end of the sixth switching transistor Q6 is connected to the first voltage line.

[0055] The first end of the seventh switching transistor Q7 is electrically connected to the output end OUT of the shift register circuit. The control end of the seventh switching transistor Q7 is electrically connected to the second end of the shift register circuit. The second end of the seventh switching transistor Q7 is connected to the first voltage line.

[0056] The first end of the eighth switching transistor Q8 is electrically connected to the output end OUT of the shift register circuit. The control end of the eighth switching transistor Q8 is electrically connected to the first control signal line 20. The second end of the eighth switching transistor Q8 is connected to the first voltage line.

[0057] The first end of the ninth switching transistor Q9 is connected to the first node A. The control end of the ninth switching transistor Q9 is electrically connected to the first control signal line 20. The second end of the ninth switching transistor Q9 is connected to the first voltage line.

[0058] The first end of the first capacitor C1 is connected to the first node A. The second end of the first capacitor C1 is electrically connected to the output end OUT of the shift register circuit. The first end of the second capacitor C2 is electrically connected to the first end of the shift register circuit. The second end of the second capacitor C2 is connected to the second node B.

[0059] The first voltage line is used to provide the VGL signal.

[0060] It should be noted that the first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4, the fifth switching transistor Q5, the sixth switching transistor Q6, the seventh switching transistor Q7, the eighth switching transistor Q8, and the ninth switching transistor Q9 provided in the embodiments of the present invention are all introduced by taking N-type switching transistors as examples. The first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4, the fifth switching transistor Q5, the sixth switching transistor Q6, the seventh switching transistor Q7, the eighth switching transistor Q8, and the ninth switching transistor Q9 may also be P-type switching transistors, and no specific limitation is made here.

[0061] In some embodiments, Figure 5 A control timing diagram of a display module provided by the present invention is shown. Figure 6 Another control timing diagram of a display module provided by the present invention is shown, as Figure 5 and Figure 6 shown, the working stages of the shift register circuit include a first working stage t1, a second working stage t2, and a third working stage t3.

[0062] According to Figure 4 and Figure 5 , taking the shift register circuit 31 of odd rows as an example for introduction:

[0063] In the first working stage t1, the shift register circuit 31_i is used to generate a first scan sub-signal according to the received first clock signal when receiving a start signal or a scan signal output by the previous shift register circuit 31_i-1; wherein, the first scan sub-signal is an invalid scan signal.

[0064] In the second working stage t2, the shift register circuit 31_i is used to generate a second scan sub-signal according to the received second clock signal, or, in the second working stage t2, the shift register circuit 31_i is used to stop generating the second scan sub-signal according to the received stage transfer stop signal.

[0065] In the third working stage t3, the shift register circuit 31_i is used to reset the internal potential of the shift register circuit 31_i according to the third scan sub-signal received at the signal reset terminal; wherein, the third scan sub-signal is the scan signal generated by the subsequent shift register circuit in its corresponding second working stage.

[0066] Exemplarily, the invalid scan signal can be determined according to the type of the switching transistor in the shift register circuit 31_i. For example, if the switching transistor in the shift register circuit 31_i is N-type, then the invalid scan signal is a low-level signal. The fourth clock signal line DIR1 provides the VGH signal, and the fifth clock signal line DIR2 provides the VGL signal.

[0067] In the first working stage t1 corresponding to the first display frame, when the first input terminal Gn-1 of the shift register circuit 31_i receives the high-level start signal provided by the start signal line 10 or receives the high-level second scan sub-signal output by the previous shift register circuit 31_i-1, the first switching transistor Q1 is turned on, and the first node A is connected to the fourth clock signal line DIR1 through the turned-on first switching transistor Q1, and the first node A receives a high-level signal. At this time, the fifth switching transistor Q5 is turned on. According to the high-level first clock signal provided by the received first clock signal line 51, the seventh switching transistor Q7 is turned on, and the output terminal OUT of the shift register circuit 31_i outputs a low-level first scan sub-signal. At this time, the signal reset terminal Gn+1 of the shift register circuit 31_i receives a low-level signal, and the second clock signal line 52 provides a low-level second clock signal. And the first node A is at a high level, and the first capacitor C1 stores energy in the first working stage t1, and the shift register circuit 31_i completes the preparation work for generating the second scan sub-signal.

[0068] In the second working stage t2 corresponding to the first display frame, since the first capacitor C1 stores energy in the first working stage t1 and there is no discharge path for the first node A, the first node A continues to maintain a high level, so that the fifth switching transistor Q5 is turned on. The shift register circuit 31_i outputs a high-level second scan sub-signal to the output terminal OUT of the shift register circuit 31_i through the turned-on fifth switching transistor Q5 according to the high-level second clock signal provided by the second clock signal line 52, and outputs it to the signal reset terminal Gn+1 of the previous shift register circuit 31_i-1 and the first input terminal Gn-1 of the next shift register circuit 31_i+1 through the output terminal OUT of the shift register circuit 31_i. At this time, the previous shift register circuit 31_i-1 is in the third working stage t3, and the next shift register circuit 31_i+1 is in the first working stage t1. And at this time, both the first input terminal Gn-1 and the signal reset terminal Gn+1 of the shift register circuit 31_i receive low-level signals, and the first clock signal line 51 provides a low-level signal.

[0069] In the third working stage t3 corresponding to the first display frame, the signal reset terminal Gn+1 of the shift register circuit 31_i receives a high-level third scan sub-signal provided by the subsequent shift register circuit 31_i+1. The third scan sub-signal is the second scan sub-signal generated by the subsequent shift register circuit 31_i+1 when it is in the second working stage t2. The second switch transistor Q2 is turned on, and the fifth clock signal line DIR2 provides the VGL signal, enabling a discharge path for the first node A, thereby causing the fifth switch transistor Q5 to turn off. And at this time, the first clock signal line 51 provides a high-level first clock signal, causing the seventh switch transistor Q7 to turn on, and the output terminal OUT of the shift register circuit 31_i provides a low-level signal, and the second clock signal line 52 correspondingly provides a low-level second clock signal. In the third working stage t3, the first node A changes from a high level to a low level, thus completing the signal reset within the shift register circuit 31_i.

[0070] In the first working stage t1 corresponding to the second display frame, when the first input terminal Gn-1 of the shift register circuit 31_i receives a high-level start signal provided by the start signal line 10 or a high-level second scan sub-signal output by the previous shift register circuit 31_i-1, the first switch transistor Q1 is turned on, and the first node A is connected to the fourth clock signal line DIR1 through the turned-on first switch transistor Q1, and the first node A receives a high-level signal. At this time, the fifth switch transistor Q5 is turned on. According to the high-level first clock signal provided by the received first clock signal line 51, the seventh switch transistor Q7 is turned on, and the output terminal OUT of the shift register circuit 31_i outputs a low-level first scan sub-signal. At this time, the signal reset terminal Gn+1 of the shift register circuit 31_i receives a low-level signal, and the second clock signal line 52 provides a low-level second clock signal.

[0071] In the second working stage t2 corresponding to the second display frame, the first control signal line 20 provides a high-level stage transfer stop signal, turning on the eighth switch transistor Q8 and the ninth switch transistor Q9, enabling a discharge path for the first node A, causing the fifth switch transistor Q5 to turn off. Therefore, the output terminal OUT of the shift register circuit 31_i cannot receive the high-level second clock signal provided by the second clock signal line 52, thereby stopping the generation of the second scan sub-signal. The output terminal OUT of the shift register circuit 31_i provides a low-level signal, causing the subsequent shift register circuit 31_i+1 not to receive a high-level second scan sub-signal in the first working stage t1. Therefore, the first node A of the subsequent shift register circuit 31_i+1 remains at a low level, and the first capacitor C1 cannot store energy in the first working stage t1. Therefore, the subsequent shift register circuit 31_i+1 cannot generate a second scan sub-signal in the second working stage t2 either, thereby preventing the subsequent shift register circuits 31 from stage-transferring the second scan sub-signal and causing the corresponding display area not to be displayed.

[0072] In the third working stage t3 corresponding to the second display frame, the first clock signal line 51 provides a high-level first clock signal to turn on the seventh switching transistor Q7, and the second clock signal line 52 provides a low-level second clock signal. At this time, since the fifth switching transistor Q5 is in the off state, the output terminal OUT of the shift register circuit 31_i is connected to the first voltage line through the turned-on seventh switching transistor Q7, and the output terminal OUT of the shift register circuit 31_i provides a low-level VGL signal at this time.

[0073] According to Figure 4 and Figure 6 , taking the shift register circuit 31 of even rows as an example for introduction:

[0074] In the first working stage t1, the shift register circuit 31_i is used to generate a first scan sub-signal according to the received second clock signal when receiving a start signal or a scan signal output by the previous shift register circuit 31_i - 1; wherein, the first scan sub-signal is an invalid scan signal.

[0075] In the second working stage t2, the shift register circuit 31_i is used to generate a second scan sub-signal according to the received first clock signal, or, in the second working stage t2, the shift register circuit 31_i is used to stop generating the second scan sub-signal according to the received stage transfer stop signal.

[0076] In the third working stage t3, the shift register circuit 31_i is used to reset the internal potential of the shift register circuit 31_i according to the third scan sub-signal received at the signal reset terminal; wherein, the third scan sub-signal is a scan signal generated by the subsequent shift register circuit in the second working stage.

[0077] Exemplarily, the invalid scan signal can be determined according to the type of the switching transistor in the shift register circuit 31_i. For example, if the switching transistor in the shift register circuit 31_i is an N-type, then the invalid scan signal is a low-level signal. The fourth clock signal line DIR1 provides a VGH signal, and the fifth clock signal line DIR2 provides a VGL signal.

[0078] In the first working stage t1 corresponding to the first display frame, when the first input terminal Gn-1 of the shift register circuit 31_i receives a high-level start signal provided by the start signal line 10 or receives a high-level second scan sub-signal output by the previous shift register circuit 31_i-1, the first switching transistor Q1 is turned on. The first node A is connected to the fourth clock signal line DIR1 through the turned-on first switching transistor Q1, and the first node A receives a high-level signal. At this time, the fifth switching transistor Q5 is turned on. According to the high-level second clock signal provided by the received second clock signal line 52, the seventh switching transistor Q7 is turned on, and the output terminal OUT of the shift register circuit 31_i outputs a low-level first scan sub-signal. At this time, the signal reset terminal Gn+1 of the shift register circuit 31_i receives a low-level signal, and the first clock signal line 51 provides a low-level first clock signal. Moreover, the first node A is at a high level, and the first capacitor C1 stores energy in the first working stage t1, and the shift register circuit 31_i completes the preparation work for generating the second scan sub-signal.

[0079] In the second working stage t2 corresponding to the first display frame, since the first capacitor C1 completes energy storage in the first working stage t1 and there is no discharge path for the first node A, the first node A continues to maintain a high level, making the fifth switching transistor Q5 turned on. According to the high-level first clock signal provided by the first clock signal line 51, the shift register circuit 31_i outputs a high-level second scan sub-signal to the output terminal OUT of the shift register circuit 31_i through the turned-on fifth switching transistor Q5, and outputs it to the signal reset terminal Gn+1 of the previous shift register circuit 31_i-1 and the first input terminal Gn-1 of the next shift register circuit 31_i+1 through the output terminal OUT of the shift register circuit 31_i. At this time, the previous shift register circuit 31_i-1 is in the third working stage t3, and the next shift register circuit 31_i+1 is in the first working stage t1. Moreover, at this time, both the first input terminal Gn-1 and the signal reset terminal Gn+1 of the shift register circuit 31_i receive low-level signals, and the second clock signal line 52 provides a low-level signal.

[0080] In the third working stage t3 corresponding to the first display frame, the signal reset terminal Gn+1 of the shift register circuit 31_i receives the high-level second scan sub-signal provided by the subsequent shift register circuit 31_i+1. The second switching transistor Q2 is turned on, and the fifth clock signal line DIR2 provides the VGL signal, enabling a discharge path for the first node A, and thus causing the fifth switching transistor Q5 to turn off. At this time, the second clock signal line 52 provides a high-level second clock signal, causing the seventh switching transistor Q7 to turn on. The output terminal OUT of the shift register circuit 31_i provides a low-level signal, and the first clock signal line 51 correspondingly provides a low-level first clock signal. In the third working stage t3, the first node A changes from high level to low level, thus completing the signal reset within the shift register circuit 31_i.

[0081] In the first working stage t1 corresponding to the second display frame, when the first input terminal Gn-1 of the shift register circuit 31_i receives the high-level start signal provided by the start signal line 10 or the high-level second scan sub-signal output by the previous shift register circuit 31_i-1, the first switching transistor Q1 is turned on. The first node A is connected to the fourth clock signal line DIR1 through the turned-on first switching transistor Q1, and the first node A receives a high-level signal. At this time, the fifth switching transistor Q5 is turned on. According to the high-level second clock signal provided by the received second clock signal line 52, the seventh switching transistor Q7 is turned on, and the output terminal OUT of the shift register circuit 31_i outputs a low-level first scan sub-signal. At this time, the signal reset terminal Gn+1 of the shift register circuit 31_i receives a low-level signal, and the first clock signal line 51 provides a low-level first clock signal.

[0082] In the second working stage t2 corresponding to the second display frame, the first control signal line 20 provides a high-level stage transfer stop signal, turning on the eighth switching transistor Q8 and the ninth switching transistor Q9. A discharge path exists for the first node A, causing the fifth switching transistor Q5 to turn off. Therefore, the output terminal OUT of the shift register circuit 31_i cannot receive the high-level first clock signal provided by the first clock signal line 51, thus stopping the generation of the second scan sub-signal. The output terminal OUT of the shift register circuit 31_i provides a low-level signal, causing the subsequent shift register circuit 31_i+1 not to receive the high-level second scan sub-signal in the first working stage t1. Therefore, the first node A of the subsequent shift register circuit 31_i+1 remains at a low level, and the first capacitor C1 cannot store energy in the first working stage t1. Therefore, the subsequent shift register circuit 31_i+1 cannot generate the second scan sub-signal in the second working stage t2 either, thus preventing the subsequent shift register circuits 31 from stage-transferring the second scan sub-signal and causing the corresponding display area not to be displayed.

[0083] In the third working stage t3 corresponding to the second display frame, the second clock signal line 52 provides a high-level second clock signal to turn on the seventh switching transistor Q7, and the first clock signal line 51 provides a low-level first clock signal. At this time, since the fifth switching transistor Q5 is in the off state, the output terminal OUT of the shift register circuit 31_i is connected to the first voltage line through the turned-on seventh switching transistor Q7, and the output terminal OUT of the shift register circuit 31_i provides a low-level VGL signal at this time.

[0084] In the first display frame of the present invention, the first control signal line 20 does not provide a stage transmission stop signal in the second working stage t2, and the shift register circuit 31 correspondingly generates a second scanning sub-signal to realize the stage transmission of the second scanning sub-signal between the shift register circuits, so that all color sub-pixels connected to the shift register circuit in the first display frame emit light normally. In the second display frame, the first control signal line 20 provides a stage transmission stop signal in the second working stage t2 to stop the corresponding shift register circuit 31 from generating the second scanning sub-signal. The first shift register circuit 31_1 to a part of the shift register circuits before the shift register circuit receiving the stage transmission stop signal correspond to the first display area, and the shift register circuit receiving the stage transmission stop signal to the last shift register circuit 31_m correspond to the second display area. Therefore, in the second display frame, the first display area is normally refreshed, and the second display area stops refreshing, so as to reduce the refresh rate of the second display area during the multi-frame display process of the display module, and further reduce the signal output provided by the display module in the second display frame, thereby reducing the power consumption of the display panel.

[0085] It should be noted that Figure 4 The 9T2C circuit provided by the corresponding shift register circuit is only an example, and the shift register circuit can also be other types of circuits. The number of transistors and capacitors in the circuit can be the same as Figure 4 the 9T2C shown, or different, and no specific limitation is made here.

[0086] In some embodiments, Figure 7 shows a schematic structural diagram of another display module provided by the present invention. As Figure 7 shown, the display module further includes a third display area 43; a plurality of shift register circuits 31 corresponding to the first display area 41, the second display area 42, and the third display area 43 are cascaded in sequence.

[0087] Exemplarily, the shift register circuit 31 is connected to the first control signal line 20. The shift register circuit 31 can stop generating the scan signal according to the stage transfer stop signal provided by the first control signal line 20. The first display area 41, the second display area 42, and the third display area 43 respectively correspond to part of the shift register circuit 31 in the display module. The first display area 41 is the area that is fixedly displayed by the display module during multiple-frame display. The second display area 42 and the third display area 43 are the area ranges corresponding to the shift register circuit 31 that receives the stage transfer stop signal provided by the first control signal line 20 to the last shift register circuit 31_i during multiple-frame display of the display module. The second display area 42 and the third display area 43 are alternately refreshed and stopped refreshing during multiple-frame display, so that the refresh rates of the second display area 42 and the third display area 43 during display are different from the refresh rate of the first display area 41, and the refresh rates between the second display area 42 and the third display area 43 during display are also different. Therefore, the signal output provided by the display module to the second display area 42 and the third display area 43 is reduced, thereby reducing the power consumption of the display panel.

[0088] In the first display frame, the shift register circuit 31_i corresponding to the first display area 41, the second display area 42, and the third display area 43 generates a scan signal when receiving the start signal or the scan signal of the previous shift register circuit 31_i-1.

[0089] Specifically, the first shift register circuit 31_1 in the first display area 41 is electrically connected to the start signal line 10. The start signal line 10 provides a start signal to the first shift register circuit 31_1 in the first display area 41, enabling it to generate a scan signal based on the received start signal and provide the scan signal to the second shift register circuit 31_2. The second shift register circuit 31_2 generates a scan signal based on the scan signal provided by the first shift register circuit 31_1 and provides the scan signal to the third shift register circuit 31_3, thereby enabling the first display area 41 to complete the cascade transmission of the scan signal. The last shift register circuit 31_i corresponding to the first display area 41 is connected to the first shift register circuit 31_i+1 corresponding to the second display area 42. Therefore, after the first display area 41 completes the cascade transmission of the scan signal, the scan signal will be transmitted to the first shift register circuit 31_i+1 corresponding to the second display area 42, causing the multiple shift register circuits 31 corresponding to the second display area 42 to cascade transmit the scan signal. The last shift register circuit 31_n corresponding to the second display area 42 is connected to the first shift register circuit 31_n+1 corresponding to the third display area 43. Therefore, after the second display area 42 completes the cascade transmission of the scan signal, the scan signal will be transmitted to the first shift register circuit 31_n+1 corresponding to the third display area 43, causing the multiple shift register circuits 31 corresponding to the third display area 43 to cascade transmit the scan signal. Thus, normal refreshing of the first display area 41, the second display area 42, and the third display area 43 within the first display frame is achieved.

[0090] In the second display frame, the shift register circuit 31 corresponding to the second display area 42 stops generating the scan signal according to the received cascade stop signal.

[0091] Specifically, in the second display frame, the first control signal line 20 provides a cascade stop signal to the first shift register circuit 31_i+1 corresponding to the second display area 42. When the first shift register circuit 31_i+1 corresponding to the second display area 42 receives the scan signal, it stops generating the scan signal according to the received cascade stop signal, thereby causing the multiple shift register circuits 31 corresponding to the second display area 42 to stop generating the scan signal. And since the first shift register circuit 31_n+1 of the third display area 43 is connected to the last shift register circuit 31_n of the second display area 42, the first shift register circuit 31_n+1 of the third display area 43 does not receive the scan signal cascaded from the second display area 42, causing the multiple shift register circuits 31 corresponding to the third display area 43 to also stop generating the scan signal. Thus, normal refreshing of the first display area 41 within the second display frame is achieved, and the second display area 42 and the third display area 43 stop refreshing within the second display frame.

[0092] In the third display frame, the shift register circuit corresponding to the third display area stops generating a scan signal according to the received stage transfer stop signal.

[0093] Specifically, in the third display frame, the first control signal line 20 provides the stage transfer stop signal to the first shift register circuit 31_n+1 corresponding to the third display area 43. When the first shift register circuit 31_n+1 corresponding to the third display area 43 receives the scan signal, it stops generating the scan signal according to the received stage transfer stop signal, so that the multiple shift register circuits 31 corresponding to the third display area 43 stop generating the scan signal. Thus, it is realized that the first display area 41 and the second display area 42 are normally refreshed within the third display frame, and the third display area 43 stops refreshing within the third display frame.

[0094] In the fourth display frame, the shift register circuit corresponding to the second display area stops generating a scan signal according to the received stage transfer stop signal.

[0095] Specifically, in the fourth display frame, the first control signal line 20 provides the stage transfer stop signal to the first shift register circuit 31_i+1 corresponding to the second display area 42, so that the multiple shift register circuits 31 corresponding to the second display area 42 and the third display area 43 stop generating the scan signal. Thus, it is realized that the first display area 41 is normally refreshed within the second display frame, and the second display area 42 and the third display area 43 stop refreshing within the second display frame. Thus, during the entire display process of the display module, the first display area 41 is normally refreshed in all three display frames, the second display area 42 is normally refreshed in the first display frame and the third display frame, and stops refreshing in the second display frame and the fourth display frame. Therefore, the refresh rate corresponding to the second display area 42 is half of the refresh rate of the first display area 41. The third display area 43 is normally refreshed in the first display frame and stops refreshing in the second display frame, the third display frame and the fourth display frame. Therefore, the refresh rate corresponding to the third display area 43 is half of the refresh rate of the second display area 42. Therefore, the signal output provided by the display module to the second display area 42 and the third display area 43 is reduced, thereby reducing the power consumption of the display panel.

[0096] In some embodiments, continue to refer to Figure 2 、 Figure 5 and Figure 6 The display module includes a first display area 41 and a second display area 42; the shift register circuits 31 corresponding to the first display area 41 and the second display area 42 are cascaded in sequence.

[0097] The display module further includes a third clock signal line 53, connected to the shift register circuit 31, for providing a third clock signal.

[0098] Exemplarily, the third clock signal line 53 is the same clock signal line as the first clock signal line 51 or the second clock signal line 52. The third clock signal line 53 corresponds to the second clock signal line 52 connected to the second end of the shift register circuit 31 of odd rows, or corresponds to the first clock signal line 51 connected to the second end of the shift register circuit of even rows.

[0099] In the first display frame, for the shift register circuits 31_i corresponding to the first display area 41 and the second display area 42, when receiving a start signal or a scan signal from the previous shift register circuit 31_i-1, a scan signal is generated based on the third clock signal.

[0100] Exemplarily, in the first working stage t1 of the first display frame, the shift register circuit 31_i of odd rows receives a start signal or a scan signal from the previous shift register circuit 31_i-1, and completes the preparation for generating a scan signal. In the second working stage t2 of the first display frame, according to the high-level second clock signal provided by the second clock signal line 52, a high-level second scan sub-signal is output through the output terminal OUT of the shift register circuit 31_i. The second clock signal line 52 corresponds to the third clock signal line 53, and generating the second scan sub-signal based on the second clock signal corresponds to generating a scan signal based on the third clock signal.

[0101] In the first working stage t1 of the first display frame, the shift register circuit 31_i of even rows receives a start signal or a scan signal from the previous shift register circuit 31_i-1, and completes the preparation for generating a scan signal. In the second working stage t2 of the first display frame, according to the high-level first clock signal provided by the first clock signal line 51, a high-level second scan sub-signal is output through the output terminal OUT of the shift register circuit 31_i. The first clock signal line 51 corresponds to the third clock signal line 53, and generating the second scan sub-signal based on the first clock signal corresponds to generating a scan signal based on the third clock signal.

[0102] Therefore, in the first display frame, when the shift register circuit 31 receives the third clock signal provided by the third clock signal line 53 correspondingly, a cascaded scan signal is generated correspondingly, so that all the color sub-pixels corresponding to the shift register circuits 31 can complete display in the first display frame, and the first display area 41 and the second display area 42 are both normally refreshed in the first display frame.

[0103] In the second display frame, when the third clock signal line 53 stops providing the third clock signal, the shift register circuit 31 corresponding to the second display area 42 stops generating a scan signal.

[0104] Exemplarily, when the first shift register circuit 31_i+1 corresponding to the second display area 42 is the shift register circuit 31 of an odd row, in the second working stage t2 corresponding to the second display frame, due to the second clock signal stopped being provided by the second clock signal line 52, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scan signal is transmitted to the next shift register circuit 31_i+2 stage. When the first shift register circuit 31_i+1 corresponding to the second display area 42 is the shift register circuit 31 of an even row, in the second working stage t2 corresponding to the second display frame, due to the first clock signal stopped being provided by the first clock signal line 51, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scan signal is transmitted to the next shift register circuit 31_i+2 stage. That is, when the third clock signal line 53 stops providing the third clock signal, the shift register circuit 31 corresponding to the second display area 42 has no scan signal output, the second display area 42 stops refreshing, and the first display area 41 remains normally refreshed.

[0105] Therefore, in the second display frame, since the first shift register circuit 31_i+1 corresponding to the second display area 42 cannot receive the third clock signal provided by the third clock signal line 53, it cannot correspondingly generate a scan signal, and thus cannot provide a scan signal to the next shift register circuit 31_i+2, resulting in no scan signal being cascaded among all the shift register circuits 31 corresponding to the second display area 42. Thus, in the multi-frame display process of the display module, in the first display frame, both the first display area 41 and the second display area 42 are normally refreshed, and in the second display frame, the first display area 41 is normally refreshed while the second display area 42 stops refreshing. Therefore, the refresh rate corresponding to the second display area 42 is half of the refresh rate corresponding to the first display area 41. The refresh rate of the second display area 42 is lower than that of the first display area 41, thereby reducing the signal output provided by the display module in the second display frame and reducing the power consumption of the display panel.

[0106] In some embodiments, continue to refer to Figure 5 、 Figure 6 and Figure 7 , the display module further includes a third display area 43; the shift register circuits 31 corresponding to the first display area 41, the second display area 42, and the third display area 43 are cascaded in sequence.

[0107] In the first display frame, the shift register circuits 31_i corresponding to the first display area 41, the second display area 42, and the third display area 43 generate scan signals when receiving a start signal or the scan signal of the previous shift register circuit 31_i-1.

[0108] Exemplarily, in the first working stage t1 corresponding to the first display frame, the shift register circuit 31_i of the odd rows receives the start signal or the scan signal of the previous shift register circuit 31_i-1, and completes the preparation for generating the scan signal. In the second working stage t2 corresponding to the first display frame, according to the high-level second clock signal provided by the second clock signal line 52, a high-level second scan sub-signal is output through the output terminal OUT of the shift register circuit 31_i. The second clock signal line 52 corresponds to the third clock signal line 53, and generating the second scan sub-signal based on the second clock signal corresponds to generating the scan signal based on the third clock signal.

[0109] In the first working stage t1 corresponding to the first display frame, the shift register circuit 31_i of the even rows receives the start signal or the scan signal of the previous shift register circuit 31_i-1, and completes the preparation for generating the scan signal. In the second working stage t2 corresponding to the first display frame, according to the high-level first clock signal provided by the first clock signal line 51, a high-level second scan sub-signal is output through the output terminal OUT of the shift register circuit 31_i. The first clock signal line 51 corresponds to the third clock signal line 53, and generating the second scan sub-signal based on the first clock signal corresponds to generating the scan signal based on the third clock signal.

[0110] Therefore, in the first display frame, when the shift register circuit 31 correspondingly receives the third clock signal provided by the third clock signal line 53, the scan signal for stage transmission is correspondingly generated, so that each color sub-pixel corresponding to all the shift register circuits 31 in the first display frame can complete the display, and the first display frame, the first display area 41, the second display area 42, and the third display area 43 are all normally refreshed in the first display frame.

[0111] In the second display frame, the shift register circuit 31 corresponding to the second display area 42 stops generating the scan signal when the third clock signal line 53 stops providing the third clock signal.

[0112] Exemplarily, when the first shift register circuit 31_i+1 corresponding to the second display area 42 is the shift register circuit 31 of an odd row, in the second working stage t2 corresponding to the second display frame, due to the second clock signal stopped being provided by the second clock signal line 52, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scanning signal is transmitted to the next shift register circuit 31_i+2 stage. When the first shift register circuit 31_i+1 corresponding to the second display area 42 is the shift register circuit 31 of an even row, in the second working stage t2 corresponding to the second display frame, due to the first clock signal stopped being provided by the first clock signal line 51, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scanning signal is transmitted to the next shift register circuit 31_i+2 stage. That is, when the third clock signal line 53 stops providing the third clock signal, there is no scanning signal output from the shift register circuit 31 corresponding to the second display area 42. And the last shift register circuit 31_n corresponding to the second display area 42 is connected to the first shift register circuit 31_n+1 corresponding to the third display area 43. When there is no scanning signal output from all the shift register circuits 31 corresponding to the second display area 42, there is no scanning signal input to the first shift register circuit 31_n+1 corresponding to the third display area 43. Therefore, in the second display frame, the first display area 41 is normally refreshed, while the second display area 42 and the third display area 43 both stop refreshing.

[0113] In the third display frame, when the third clock signal line 53 stops providing the third clock signal, the shift register circuit 31 corresponding to the third display area 43 stops generating the scanning signal.

[0114] Exemplarily, when the first shift register circuit 31_n+1 corresponding to the third display area 43 is the shift register circuit 31 of an odd row, in the second working stage t2 corresponding to the third display frame, due to the second clock signal stopped being provided by the second clock signal line 52, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scanning signal is transmitted to the next shift register circuit 31_n+2 stage. When the first shift register circuit 31_n+1 corresponding to the third display area 43 is the shift register circuit 31 of an even row, in the second working stage t2 corresponding to the third display frame, due to the first clock signal stopped being provided by the first clock signal line 51, there is no signal output at the output terminal OUT of the shift register circuit 31, and thus no scanning signal is transmitted to the next shift register circuit 31_n+2 stage. That is, when the third clock signal line 53 stops providing the third clock signal, there is no scanning signal output from the shift register circuit 31 corresponding to the third display area 43, the third display area 43 stops refreshing, and the first display area 41 and the second display area 42 maintain normal refreshing.

[0115] In the fourth display frame, when the shift register circuit 31 corresponding to the second display area 42 stops generating the scan signal when the third clock signal line 53 stops providing the third clock signal.

[0116] Exemplarily, in the fourth display frame, when the third clock signal line 53 stops providing the third clock signal, the shift register circuit 31 corresponding to the second display area 42 does not output the scan signal, and the last shift register circuit 31_n corresponding to the second display area 42 is connected to the first shift register circuit 31_n+1 corresponding to the third display area 43. Therefore, the first shift register circuit 31_n+1 corresponding to the third display area 43 does not receive the scan signal input, so that in the fourth display frame, the first display area 41 is normally refreshed, and the second display area 42 and the third display area 43 both stop refreshing.

[0117] Therefore, in the second display frame and the fourth display frame, since the first shift register circuit 31_i+1 corresponding to the second display area 42 does not receive the third clock signal provided by the third clock signal line 53, it cannot generate the scan signal correspondingly, and thus cannot provide the scan signal to the next shift register circuit 31_i+2, so that all the shift register circuits 31 corresponding to the second display area 42 and the third display area 43 do not have the scan signal level transmission. In the third display frame, since the first shift register circuit 31_n+1 corresponding to the third display area 43 does not receive the third clock signal provided by the third clock signal line 53, all the shift register circuits 31 corresponding to the third display area 43 do not have the scan signal level transmission. Therefore, during the multi-frame display process of the display module, in the first display frame, the first display area 41, the second display area 42, and the third display area 43 are all normally refreshed. In the second display frame and the fourth display frame, the first display area 41 is normally refreshed, and the second display area 42 and the third display area 43 stop refreshing. In the third display frame, the first display area 41 and the second display area 42 are normally refreshed, and the third display area 43 stops refreshing. Therefore, the refresh rate corresponding to the second display area 42 is half of the refresh rate corresponding to the first display area 41, and the refresh rate corresponding to the third display area 43 is half of the refresh rate corresponding to the second display area 42, so that the signal output provided by the display module is reduced in the second display frame, the third display frame, and the fourth display frame, thereby reducing the power consumption of the display panel.

[0118] Figure 8 The schematic diagram showing the display situation of the display module provided by another embodiment of the present application is as Figure 8As shown, for example, the display device includes a first display area 41, a second display area 42, and a third display area 43 arranged in sequence. In the first display frame, the shift register circuits 31 corresponding to the first display area 41, the second display area 42, and the third display area 43 all transmit the scanning signal in the normal stage, enabling the first display area 41, the second display area 42, and the third display area 43 to be refreshed normally. In the second display frame, the first display area 41 is refreshed normally. The second display area 42 and the third display area 43 can be regarded as the same display area. The first shift register circuit 31_i + 1 corresponding to the second display area 42 receives the stage transmission stop signal provided by the first control signal line 20, and stops providing the scanning signal to the next shift register circuit 31_i + 2. As a result, all the shift register circuits 31 in the second display area 42 have no scanning signal transmission. Since the second display area 42 and the third display area 43 are arranged in sequence, and the last shift register circuit 31_n of the second display area 42 is connected to the first shift register circuit 31_n + 1 of the third display area 43, the first shift register circuit 31_n + 1 of the third display area 43 cannot receive the scanning signal provided by the last shift register circuit 31_n of the second display area 42. Thus, it can be achieved that both the second display area 42 and the third display area 43 stop refreshing. In the third display frame, the first display area 41 and the second display area 42 are refreshed normally. The first shift register circuit 31_n + 1 corresponding to the third display area 43 receives the stage transmission stop signal provided by the first control signal line 20, and stops providing the scanning signal to the next shift register circuit 31_n + 2. As a result, all the shift register circuits 31 in the third display area 43 have no scanning signal transmission, and further, the third display area 43 stops refreshing. In the fourth display frame, the first display area 41 is refreshed normally, and the second display area 42 and the third display area 43 stop refreshing. Therefore, the refresh rate of the second display area 42 is half of the refresh rate of the first display area 41, and the refresh rate of the third display area 43 is half of the refresh rate of the second display area 42, which are, for example, the refresh rate of the first display area 41 is 120 Hz, the refresh rate of the second display area 42 is 60 Hz, and the refresh rate of the third display area 43 is 30 Hz. The first display area 41 can be used to display navigation content or movies, the second display area 42 can be used to display vehicle-mounted function icons, and the third display area 43 can be used to display vehicle-mounted buttons. Thus, it can be achieved that there are display areas with three refresh rates in the display device. In each display frame of the present application, the first shift register circuit 31 corresponding to the second display area is different, so that there are multiple display areas during the multi-frame display process, and the refresh rates of each display area are different.

[0119] In some embodiments, Figure 9The structural schematic diagram of another display module provided by the present invention is shown, as Figure 9 shown, the display module further includes a driving chip 60. The driving chip 60 is connected to the start signal line 10. The start signal line 10 is connected to the first shift register circuit 31_1 far from the driving chip 60, and is also connected to the first shift register circuit 31_1 close to the driving chip 60. The driving chip 60 provides a start signal to the shift register circuit 31 through the start signal line 10.

[0120] The display module further includes a fourth clock signal line DIR1. The fourth clock signal line DIR1 is connected to the shift register circuit 31 and is used to provide a fourth clock signal. In the first scanning mode, the first shift register circuit 31_1 far from the driving chip 60 generates a scanning signal transmitted in the first scanning direction based on the fourth clock signal when receiving the start signal; wherein, the first scanning direction is the direction from the first shift register circuit 31_1 far from the driving chip 60 to the driving chip 60.

[0121] Specifically, in the first scanning mode, the fourth clock signal line DIR1 provides a high-level fourth clock signal, so that when the driving chip 60 provides a start signal through the start signal line 10, although both the first shift register circuit 31_1 far from the driving chip 60 and the first shift register circuit 31_1 close to the driving chip 60 can receive the start signal, only the first shift register circuit 31_1 far from the driving chip 60 transmits the scanning signal in the direction from the first shift register circuit 31_1 far from the driving chip 60 to the driving chip 60 when receiving the start signal. Therefore, the present invention can set the display area corresponding to the high refresh rate at a position far from the driving chip 60 by making the shift register circuit 31 transmit the scanning signal in the first scanning direction, and the display area corresponding to the low refresh rate can be set at a position close to the driving chip 60.

[0122] The display module further includes a fifth clock signal line DIR2. The fifth clock signal line DIR2 is connected to the shift register circuit 31 and is used to provide a fifth clock signal. In the second scanning mode, the first shift register circuit 31_m close to the driving chip 60 generates a scanning signal transmitted in the second scanning direction based on the fifth clock signal when receiving the start signal; wherein, the second scanning direction is the direction from the driving chip 60 to the first shift register circuit 31_m far from the driving chip 60.

[0123] Specifically, in the second scanning mode, the fifth clock signal line DIR2 provides a fifth clock signal with a high level, enabling the driving chip 60 to provide a start signal through the start signal line 10. Although the first shift register circuit 31_m far from the driving chip 60 and the first shift register circuit 31_m close to the driving chip 60 can both receive the start signal, only the first shift register circuit 31_m close to the driving chip 60, when receiving the start signal, cascades and transmits the scanning signal in the direction from the driving chip 60 to the first shift register circuit 31_m far from the driving chip 60. Therefore, the present invention can set the display area corresponding to the high refresh rate at a position close to the driving chip 60 by making the shift register circuit 31 cascade and transmit the scanning signal in the second scanning direction, and the display area corresponding to the low refresh rate can be set at a position far from the driving chip 60.

[0124] In some embodiments, the display module further includes: a touch control circuit including a plurality of cascaded touch control sub - circuits; wherein, the touch control sub - circuits correspond to the shift register circuits one by one; a second control signal line connected to the touch control sub - circuits for providing a touch control stop signal to the corresponding touch control sub - circuit when the first control signal line provides a cascade stop signal to the shift register circuit.

[0125] Specifically, during the multi - frame display process of the display module, in the first data frame, neither the first control signal line nor the second control signal line outputs a signal. Therefore, the entire display area of the display module is normally refreshed, and the touch control circuit can implement the touch control function. In the second data frame, the first control signal line provides a cascade stop signal to the first shift register circuit corresponding to the second display area, causing the second display area to stop refreshing, while the first display area remains normally refreshed. The second control signal line provides a touch control stop signal to the corresponding touch control sub - circuit when the first control signal line provides a cascade stop signal, so that the touch control sub - circuit receiving the control stop signal to the last touch control sub - circuit corresponding to the second touch area stops implementing the touch control function, while the first touch area corresponding to the first touch control sub - circuit to the touch control sub - circuit receiving the control stop signal maintains the touch control function. Therefore, during the multi - frame display process of the display module, the refresh rate of the second display area is half of the refresh rate of the first display area, and the refresh rate of the second touch area is half of the refresh rate of the first touch area. Since the first display area is normally refreshed and the first touch area normally implements the touch control function in each data frame of the display module, the refresh rate of the first display area is the same as the refresh rate of the first touch area, and thus the refresh rate of the second display area is the same as the refresh rate of the second touch area, thereby realizing the synchronization of the refresh rates of the touch area and the display area.

[0126] In some embodiments, Figure 10Schematic diagram showing another display module provided by the present invention, as follows Figure 10 As shown, the gate driving circuit includes: a first sub-driving circuit and a second sub-driving circuit; the first sub-driving circuit includes a plurality of shift register circuits 31 for odd rows connected in cascade, and the second sub-driving circuit includes a plurality of shift register circuits 31 for even rows connected in cascade.

[0127] The start signal line 10 includes a first sub-start signal line 11 and a second sub-start signal line 12.

[0128] The first sub-start signal line 11 is connected to the first shift register circuit 31_a of a plurality of shift register circuits 31 for odd rows, and the first sub-start signal line 11 is used to provide a first sub-start signal. The plurality of shift register circuits 31 for odd rows are used to generate a scan signal when receiving the first sub-start signal or the scan signal output by the previous shift register circuit.

[0129] Specifically, the first shift register circuit 31_a of the plurality of shift register circuits 31 for odd rows generates a scan signal after receiving the first sub-start signal and provides the scan signal to the next shift register circuit 31_a+1 for odd rows. The next shift register circuit 31_a+1 for odd rows will continue to generate a scan signal according to the received scan signal and continue to cascade the scan signal until all the shift register circuits 31 for odd rows complete the cascading of the scan signal.

[0130] The second sub-start signal line 12 is connected to the first shift register circuit 31_b of a plurality of shift register circuits 31 for even rows, and the second sub-start signal line 12 is used to provide a second sub-start signal. The plurality of shift register circuits 31 for even rows are used to generate a scan signal when receiving the second sub-start signal or the scan signal output by the previous shift register circuit.

[0131] Specifically, the first shift register circuit 31_b of the plurality of shift register circuits 31 for even rows generates a scan signal after receiving the second sub-start signal and provides the scan signal to the next shift register circuit 31_b+1 for even rows. The next shift register circuit 31 for even rows will continue to generate a scan signal according to the received scan signal and continue to cascade the scan signal until all the shift register circuits 31 for even rows complete the cascading of the scan signal.

[0132] The first control signal line 20 includes a first sub-control signal line 21 and a second sub-control signal line 22.

[0133] The first sub-control signal line 21 is connected to the shift register circuits 31 of multiple odd-numbered rows, and the first sub-control signal line 21 is used to provide a first sub-stage transfer stop signal. The shift register circuits 31 of multiple odd-numbered rows are further configured to stop generating the scan signal when receiving the first sub-stage transfer stop signal. The second sub-control signal line 22 is connected to the shift register circuits 31 of multiple even-numbered rows, and the second sub-control signal line 22 is used to provide a second sub-stage transfer stop signal. The shift register circuits 31 of multiple even-numbered rows are further configured to stop generating the scan signal when receiving the second sub-stage transfer stop signal.

[0134] Exemplarily, in the first display frame, neither the first sub-control signal line 21 nor the second sub-control signal line 22 outputs a signal. The shift register circuits 31 of odd-numbered rows and the shift register circuits 31 of even-numbered rows respectively transfer the scan signal to achieve normal refreshing of the display module. In the second display frame, the first shift register circuit 31 corresponding to the second display area can be the shift register circuit 31 of odd-numbered rows or the shift register circuit 31 of even-numbered rows. The first sub-control signal line 21 provides a first sub-stage transfer stop signal to the first shift register circuit 31 of odd-numbered rows corresponding to the second display area, so that the shift register circuits 31 of multiple odd-numbered rows corresponding to the second display area stop transferring the scan signal. And the second sub-control signal line 22 provides a second sub-stage transfer stop signal to the first shift register circuit 31 of even-numbered rows corresponding to the second display area, so that the shift register circuits 31 of multiple even-numbered rows corresponding to the second display area stop transferring the scan signal. Thus, all the shift register circuits 31 in the second display area stop transferring the scan signal in the second display frame. Furthermore, the second display area alternately refreshes and stops refreshing during multiple-frame display, so that the refresh rate of the second display area during display is different from that of the first display area. Therefore, the signal output provided by the display module to the second display area is reduced, thereby reducing the power consumption of the display panel.

[0135] In some embodiments, Figure 11 The structural schematic diagram of another display module provided by the present invention is shown, as Figure 11 shown, the display module further includes a display panel 70.

[0136] Specifically, the first sub-driving circuit 301 and the second sub-driving circuit 302 are respectively arranged on both sides of the display panel 70, so that the data traces corresponding to the first sub-driving circuit 301 and the second sub-driving circuit 302 can be respectively arranged on both sides of the display panel 70. Compared with arranging the first sub-driving circuit 301 and the second sub-driving circuit 302 on the same side of the display panel 70, it is beneficial to the narrow-edge design of the display device.

[0137] The present application further provides a display device, including the display module provided by the present invention. Please refer toFigure 12 , Figure 12 The structural schematic diagram of a display device provided by the present invention is shown. Figure 12 The provided display device 1000 includes the display module 100 provided by any of the above embodiments of the present invention. Figure 12 In the embodiment, only a mobile phone is taken as an example to illustrate the display device 1000. It can be understood that the display device provided by the embodiments of the present invention can be other display devices with a display function, such as wearable products, computers, televisions, in-vehicle display devices, etc. The present invention does not make specific limitations thereto. The display device provided by the embodiments of the present invention has the beneficial effects of the display module provided by the embodiments of the present invention. For the specific description of the display module, reference can be made to the above embodiments. Details will not be repeated herein.

[0138] The present application also provides a driving method for a display module. The driving method is applied to the display module of the present invention. The display module includes a first display area and a second display area. A plurality of shift register circuits corresponding to the first display area and the second display area are connected in cascade in sequence.

[0139] Exemplarily, the display module further includes a driving chip, a first control signal line, and a start signal line. The driving chip is respectively connected to the first control signal line and the start signal line. The shift register circuit is connected to the first control signal line. Therefore, the shift register circuit can receive the stage transfer stop signal provided by the driving chip to the first control signal line. The first shift register circuit in the display module is connected to the start signal line. Therefore, the first shift register circuit can receive the start signal provided by the driving chip to the start signal line.

[0140] Figure 13 The flowchart of a driving method for a display module provided by the present invention is shown. As Figure 13 shown, the driving method includes: S810 and S820.

[0141] S810. In the first display mode, in the first display frame and the second display frame, provide a start signal to the start signal line, so that each shift register circuit in the first display area and the second display area generates a scanning signal in sequence by stage transfer.

[0142] Among them, the first display mode is a mode in which the display module only displays at the first display frequency.

[0143] Specifically, in the first display frame and the second display frame of the first display mode, the driving chip provides a start signal to the first shift register circuit in the first display area through the start signal line, enabling it to generate a scan signal based on the received start signal and providing the scan signal to the second shift register circuit. The second shift register circuit generates a scan signal based on the scan signal provided by the first shift register circuit and provides the scan signal to the third shift register circuit, thereby enabling the first display area to complete the cascade transmission of the scan signal. The last shift register circuit corresponding to the first display area is connected to the first shift register circuit corresponding to the second display area. Therefore, after the cascade transmission of the scan signal is completed in the first display area, the scan signal will be transmitted to the first shift register circuit corresponding to the second display area, causing the multiple shift register circuits corresponding to the second display area to cascade-transmit the scan signal, thereby achieving the display of the first display area and the second display area at the same first display frequency in the first display mode of the display module.

[0144] S820. In the second display mode, in the first display frame and the second display frame, provide a start signal to the start signal line, and provide a cascade stop signal to the first control signal line when the first shift register circuit in the second display area receives the scan signal output by the previous shift register circuit in the second display frame.

[0145] Among them, the second display mode is a mode in which the display module displays at the first display frequency and the second display frequency.

[0146] Specifically, in the first display frame of the second display mode, the driving chip provides a start signal to the first shift register circuit in the first display area through the start signal line, enabling the shift register circuits corresponding to the first display area and the second display area to transmit the scan signal in cascade, so that both the first display area and the second display area are normally refreshed in the first display frame. In the second display frame of the second display mode, the driving chip provides a cascade stop signal to the first shift register circuit corresponding to the second display area through the first control signal line. When the first shift register circuit corresponding to the second display area receives the scan signal, it will stop generating the scan signal according to the received cascade stop signal, so that the multiple shift register circuits corresponding to the second display area stop generating the scan signal. Thus, it is realized that the first display area is normally refreshed in the second display frame, and the second display area stops refreshing in the second display frame. Therefore, during the multi-frame display process of the display module in the second mode, the first display area is normally refreshed in both display frames, while the second display area is only normally refreshed in the first display frame and stops refreshing in the second display frame. Therefore, the refresh rate corresponding to the second display area is half of the refresh rate of the first display area. The first display area is displayed at the first display frequency in the second display mode, and the second display area is displayed at the second display frequency in the second display mode. In the second display mode of the present invention, the refresh rate of the second display area during the display process is lower than that of the first display area, that is, the second display area does not display in some display frames, so that the signal output provided by the display module to the second display area is reduced, thereby reducing the power consumption of the display panel.

[0147] The present invention also provides a driving method for a display module. The driving method is applied to the display module corresponding to any of the above embodiments. The display module includes a first display area and a second display area, and multiple shift register circuits corresponding to the first display area and the second display area are connected in cascade in sequence.

[0148] Exemplarily, the display module further includes a driving chip, a first control signal line, and a start signal line. The driving chip is respectively connected to the first control signal line and the start signal line. The shift register circuit is connected to the first control signal line, so the shift register circuit can receive the cascade stop signal provided by the driving chip to the first control signal line. The first shift register circuit in the display module is connected to the start signal line, so the first shift register circuit can receive the start signal provided by the driving chip to the start signal line.

[0149] Figure 14 The flowchart showing another driving method for a display module provided by the present invention is as Figure 14 shown. The driving method includes: S910 and S920.

[0150] S910. In the third display mode, during the first display frame and the second display frame, a start signal is provided to the start signal line so that each shift register circuit in the first display area and the second display area sequentially generates a scan signal through cascading.

[0151] Among them, the third display mode is a mode in which the display module performs display at the first display frequency.

[0152] Specifically, in the first display frame and the second display frame of the third display mode, the driving chip provides a start signal to the first shift register circuit in the first display area through the start signal line, so that it generates a scan signal according to the received start signal and provides the scan signal to the second shift register circuit. The second shift register circuit generates a scan signal according to the scan signal provided by the first shift register circuit and provides the scan signal to the third shift register circuit, thereby completing the cascading of the scan signal in the first display area. The last shift register circuit corresponding to the first display area is connected to the first shift register circuit corresponding to the second display area. Therefore, after the cascading of the scan signal in the first display area is completed, the scan signal will be transmitted to the first shift register circuit corresponding to the second display area, enabling the multiple shift register circuits corresponding to the second display area to cascade the scan signal, thereby realizing that both the first display area and the second display area perform display at the same first display frequency in the first display mode of the display module.

[0153] S920. In the fourth display mode, during the first display frame and the second display frame, a start signal is provided to the start signal line, and when the first shift register circuit in the second display area receives the scan signal output by the previous shift register circuit in the second display frame, a fixed-level signal is provided to the clock signal line.

[0154] Among them, the fourth display mode is a mode in which the display module performs display at the second display frequency.

[0155] Specifically, in the first display frame of the fourth display mode, the driving chip provides a start signal to the first shift register circuit in the first display area through the start signal line. At the same time, the driving chip also provides a square-wave clock signal to each shift register circuit through the clock signal line, so that the shift register circuits corresponding to the first display area and the second display area cascade and transmit scan signals according to the received clock signal, enabling both the first display area and the second display area to be normally refreshed in the first display frame. In the second display frame of the fourth display mode, when the first shift register circuit in the second display area receives the scan signal output by the previous shift register circuit in the second display frame, the driving chip provides a fixed-level signal through the clock signal line, so that the multiple shift register circuits corresponding to the second display area stop generating scan signals, thereby realizing that the first display area is normally refreshed in the second display frame and the second display area stops refreshing in the second display frame. Thus, during the multi-frame display process of the display module in the second mode, the first display area is normally refreshed in both display frames, while the second display area is only normally refreshed in the first display frame and stops refreshing in the second display frame. Therefore, the refresh rate corresponding to the second display area is half of the refresh rate of the first display area. This enables the first display area to be displayed at the first display frequency in the second display mode, and the second display area to be displayed at the second display frequency in the second display mode. In the second display mode of the present invention, the refresh rate of the second display area during the display process is lower than that of the first display area, that is, the second display area does not display in some display frames, thereby reducing the signal output provided by the display module to the second display area and further reducing the power consumption of the display panel.

[0156] As can be seen from the above embodiments, the display module, its driving method, and the display device provided by the present invention at least achieve the following beneficial effects:

[0157] The display module provided by the present invention includes: a start signal line for providing a start signal; a first control signal line for providing a cascading stop signal; a gate driving circuit including a plurality of cascaded shift register circuits, the shift register circuits being connected to the first control signal line, and the first shift register circuit of the plurality of shift register circuits being connected to the start signal line; the shift register circuit is configured to generate a scan signal when receiving the start signal or the scan signal output by the previous shift register circuit; the shift register circuit is further configured to stop generating the scan signal when receiving the cascading stop signal. According to the embodiments of the present invention, the shift register circuit is connected to the first control signal line, and the first control signal line is used to provide the cascading stop signal to the shift register circuit, so that the first shift register circuit of a certain display area stops generating the scan signal, thereby enabling this display area to stop refreshing within a display frame. Therefore, in some display frames, the present invention can make the entire display panel refresh normally, while in other display frames, it makes a partial display area of the display panel refresh normally, and another partial display area of the display panel stops refreshing according to the cascading stop signal provided by the first control signal line, so that the refresh rate of this partial display area is reduced in multiple display frames. Thus, the present invention realizes different refresh rates for different display areas with different display requirements during the entire display process of the display module, enabling the display areas with higher refresh rate requirements to refresh normally in all display frames, while the display areas with lower refresh rate requirements stop refreshing in some display frames, thereby reducing the signal output of this area and further reducing the power consumption of the display panel.

[0158] In accordance with the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A display module, characterized in that, Comprising: A start signal line for providing a start signal; A first control signal line for providing a cascading stop signal; A gate driving circuit including a plurality of cascaded shift register circuits, the shift register circuits being connected to the first control signal line, and the first shift register circuit of the plurality of shift register circuits being connected to the start signal line; The shift register circuit is configured to generate a scan signal when receiving the start signal or the scan signal output from the previous shift register circuit; the shift register circuit is further configured to stop generating the scan signal when receiving the cascading stop signal.

2. The display module according to claim 1, wherein The display module includes a first display area and a second display area; a plurality of shift register circuits corresponding to the first display area and the second display area are cascaded in sequence; In a first display frame, the shift register circuits corresponding to the first display area and the second display area generate the scan signal when receiving the start signal or the scan signal of the previous shift register circuit; In a second display frame, one of the shift register circuits corresponding to the second display area stops generating the scan signal according to the received cascading stop signal when receiving the scan signal of the previous shift register circuit.

3. The display module according to claim 2, wherein The working stages of the shift register circuit include a first working stage and a second working stage; The display module further includes: A first clock signal line connected to the shift register circuit for providing a first clock signal; A second clock signal line connected to the shift register circuit for providing a second clock signal; In the first working stage, the shift register circuit is configured to generate a first scan sub-signal according to the received first clock signal when receiving the start signal or the scan signal output from the previous shift register circuit; In the second working stage, the shift register circuit is configured to generate a second scan sub-signal according to the received second clock signal, Or, In the second working stage, the shift register circuit is configured to stop generating the second scan sub-signal according to the received cascading stop signal; Wherein, the first scan sub-signal is an invalid scan signal, and the second scan sub-signal is a valid scan signal.

4. The display module according to claim 3, characterized in that, The working stages of the shift register circuit include a third working stage; The signal reset terminal of the shift register circuit is electrically connected to the output terminal of the next shift register circuit; In the third working stage, the shift register circuit is configured to reset the internal potential of the shift register circuit according to the third scan sub-signal received by the signal reset terminal; Wherein, the third scan sub-signal is the scan signal generated by the next shift register circuit in the second working stage.

5. The display module according to claim 2, wherein The display module further includes a third display area; a plurality of shift register circuits corresponding to the first display area, the second display area and the third display area are cascaded in sequence; In the first display frame, the shift register circuits corresponding to the first display area, the second display area, and the third display area generate the scan signal when receiving the start signal or the scan signal of the previous shift register circuit. In the second display frame, the shift register circuit corresponding to the second display area stops generating the scan signal according to the received stage transfer stop signal. In the third display frame, the shift register circuit corresponding to the third display area stops generating the scan signal according to the received stage transfer stop signal. In the fourth display frame, the shift register circuit corresponding to the second display area stops generating the scan signal according to the received stage transfer stop signal.

6. The display module according to claim 1, wherein The display module includes a first display area and a second display area; the shift register circuits corresponding to the first display area and the second display area are cascaded in sequence. The display module further includes a third clock signal line, connected to the shift register circuit for providing a third clock signal. In the first display frame, the shift register circuits corresponding to the first display area and the second display area generate the scan signal based on the third clock signal when receiving the start signal or the scan signal of the previous shift register circuit. In the second display frame, the shift register circuit corresponding to the second display area stops generating the scan signal when the third clock signal line stops providing the third clock signal.

7. The display module according to claim 6, wherein The display module further includes a third display area; the shift register circuits corresponding to the first display area, the second display area, and the third display area are cascaded in sequence. In the first display frame, the shift register circuits corresponding to the first display area, the second display area, and the third display area generate the scan signal when receiving the start signal or the scan signal of the previous shift register circuit. In the second display frame, the shift register circuit corresponding to the second display area stops generating the scan signal when the third clock signal line stops providing the third clock signal. In the third display frame, the shift register circuit corresponding to the third display area stops generating the scan signal when the third clock signal line stops providing the third clock signal. In the fourth display frame, the shift register circuit corresponding to the second display area stops generating the scan signal when the third clock signal line stops providing the third clock signal.

8. The display module according to claim 1, wherein The display module further includes: a driving chip; The driving chip is connected to the start signal line, and the start signal line is connected to the first shift register circuit far from the driving chip and the first shift register circuit close to the driving chip.

9. The display module according to claim 8, wherein The display module further includes: A fourth clock signal line, connected to the shift register circuit for providing a fourth clock signal; In the first scanning mode, the first shift register circuit away from the driving chip generates the scanning signal that is cascaded in the first scanning direction based on the fourth clock signal when receiving the start signal; Wherein, the first scanning direction is the direction from the first shift register circuit away from the driving chip to the driving chip.

10. The display module according to claim 8, wherein, The display module further includes: A fifth clock signal line, connected to the shift register circuit, for providing a fifth clock signal; In the second scanning mode, the first shift register circuit close to the driving chip generates the scanning signal that is cascaded in the second scanning direction based on the fifth clock signal when receiving the start signal; Wherein, the second scanning direction is the direction from the driving chip to the first shift register circuit away from the driving chip.

11. The display module according to claim 1, wherein The display module further includes: A touch circuit, including a plurality of cascaded touch sub - circuits; wherein, the touch sub - circuits correspond to the shift register circuits one by one; A second control signal line, connected to the touch sub - circuit, for providing a touch stop signal to the corresponding touch sub - circuit when the first control signal line provides the cascading stop signal to the shift register circuit.

12. The display module according to claim 1, wherein The gate driving circuit includes: a first sub - driving circuit and a second sub - driving circuit; the first sub - driving circuit includes a plurality of shift register circuits of odd rows connected in cascade, and the second sub - driving circuit includes a plurality of shift register circuits of even rows connected in cascade; The start signal line includes: A first sub - start signal line, connected to the first shift register circuit of a plurality of shift register circuits of odd rows, and the first sub - start signal line is used to provide a first sub - start signal; A second sub - start signal line, connected to the first shift register circuit of a plurality of shift register circuits of even rows, and the second sub - start signal line is used to provide a second sub - start signal; The plurality of shift register circuits of odd rows are used to generate a scanning signal when receiving the first sub - start signal or the scanning signal output by the previous shift register circuit; The plurality of shift register circuits of even rows are used to generate a scanning signal when receiving the second sub - start signal or the scanning signal output by the previous shift register circuit.

13. The display module according to claim 12, wherein The display module further includes a display panel; The first sub - driving circuit and the second sub - driving circuit are respectively arranged on two sides of the display panel.

14. A display device, characterized in that, Including the display module according to any one of claims 1 - 13.

15. A driving method for a display module, characterized in that Applied to the display module according to any one of claims 1 - 13, the display module includes a first display area and a second display area, and the plurality of shift register circuits corresponding to the first display area and the second display area are sequentially connected in cascade; The method includes: In the first display mode, in the first display frame and the second display frame, providing the start signal to the start signal line so that each shift register circuit in the first display area and the second display area sequentially cascades to generate a scanning signal; In the second display mode, in the first display frame and the second display frame, the start signal is provided to the start signal line, and when the first shift register circuit in the second display area in the second display frame receives the scan signal output from the previous shift register circuit, the stage transfer stop signal is provided to the first control signal line; Among them, the first display mode is the mode in which the display module displays at the first display frequency; the second display mode is the mode in which the display module displays at the second display frequency.

16. A driving method for a display module, characterized in that, Applied to the display module according to any one of claims 1-13, the display module includes a first display area and a second display area, and a plurality of shift register circuits corresponding to the first display area and the second display area are connected in cascade in sequence; In the third display mode, in the first display frame and the second display frame, the start signal is provided to the start signal line so that each shift register circuit in the first display area and the second display area sequentially generates a scan signal through stage transfer; In the fourth display mode, in the first display frame and the second display frame, the start signal is provided to the start signal line, and when the first shift register circuit in the second display area in the second display frame receives the scan signal output from the previous shift register circuit, a fixed level signal is provided to the clock signal line; Among them, the third display mode is the mode in which the display module displays at the first display frequency; the fourth display mode is the mode in which the display module displays at the second display frequency.

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