Dynamic compensation-based CPU (Central Processing Unit) load monitoring method for satellite-borne network equipment

Abstract

The embodiment of the invention discloses a CPU load monitoring method based on dynamic compensation for satellite-borne network equipment. The method comprises the following steps: acquiring a first baseline and a second baseline when a load calculation cycle is started; respectively executing the following operations in each load calculation period: dynamically determining a baseline observation window according to the current CPU temperature, and extracting a data packet-free time period in the baseline observation window; dynamically updating the first base line of the current period according to the first base line during starting and the DPDK cycle number in the data packet-free time period; preliminarily determining the CPU load rate of the current period according to the first base line of the current period, the second base line and the DPDK cycle number in the current period; and compensating the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current period. The embodiment of the invention has the advantages of small error, high reliability and less resource consumption.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of satellite communication technology, and in particular, to a method for monitoring the CPU load of an on-board network device based on dynamic compensation. Background Art

[0002] Monitoring the actual CPU (Central Processing Unit) load of an on-board network device can provide data support for satellite resource scheduling and fault warning. The current CPU load monitoring technologies are as follows: Technology 1: An interrupt-driven load monitoring method. This method uses a hardware interrupt trigger sampling mechanism to calculate the CPU utilization rate by counting the number of interrupt triggers within a unit time; an interrupt is triggered after the message processing is completed to record the effective processing time segment.

[0003] However, this method has the following defects: 1) Poor radiation environment adaptability: The interrupt register is vulnerable to single-event upsets, resulting in interrupt loss or false triggering; 2) Distortion in high-load scenarios: In high-speed traffic scenarios above 10 Gbps, the interrupt frequency exceeds the hardware processing capacity, resulting in packet loss of sampling data; 3) Incompatibility with the DPDK (Data Plane Development Kit) architecture: DPDK uses a polling mode to bypass the kernel protocol stack, and the interrupt mechanism cannot capture the actual load cycle.

[0004] Technology 2: A polling sampling method in the DPDK environment. This method inserts a timestamp acquisition point in the DPDK packet receiving loop, calculates the CPU occupancy rate by comparing the time differences of adjacent cycles, and uses a fixed threshold to filter out invalid polling cycles.

[0005] However, this method has the following defects: 1) Baseline drift problem: The dynamic change of the CPU frequency affected by temperature in the space environment is not considered; 2) Lack of single-particle protection: The timestamp storage area is not protected by ECC, and continuous flips will cause the cumulative error to amplify; 3) Failure of multi-core cooperation: A cross-core data consistency mechanism is not designed, and there is data competition when aggregating multi-core loads.

[0006] Patent application CN1664789A discloses a method for detecting the CPU occupancy rate of a real-time operating system, and patent application CN117827604A discloses a method, device, and readable storage medium for determining the processor load rate, neither of which can solve the above problems. Summary of the Invention

[0007] The embodiments of the present invention provide a method for monitoring the CPU load of an on-board network device based on dynamic compensation to solve at least one of the above technical problems.

[0008] In a first aspect, an embodiment of the present invention provides a method for monitoring the CPU load of a spaceborne network device based on dynamic compensation, including: Obtain a first baseline and a second baseline when the load calculation cycle of the spaceborne network device starts. Among them, the first baseline is the number of DPDK cycles in which the CPU of the spaceborne network device remains in a state without data packets within a load calculation cycle, and the second baseline is the number of DPDK cycles in which the CPU of the spaceborne network device remains in a state with full data packets within a load calculation cycle; Perform the following operations respectively in each load calculation cycle: S1-1. Dynamically determine a baseline observation window according to the current CPU temperature, and extract the time period without data packets within the baseline observation window; S1-2. Dynamically update the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles within the time period without data packets; S1-3. Preliminarily determine the CPU load rate of the current load calculation cycle according to the first baseline, the second baseline of the current load calculation cycle, and the number of DPDK cycles within the current load calculation cycle; S1-4. Compensate the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation cycle.

[0009] In a second aspect, an embodiment of the present invention provides an electronic device, and the electronic device includes: One or more processors; A memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method for monitoring the CPU load of the spaceborne network device based on dynamic compensation according to any embodiment.

[0010] In summary, this embodiment provides a method for monitoring the CPU load of a spaceborne network device based on dynamic compensation, which can accurately monitor the true load rate of the DPDK exclusive core in a space radiation environment with single-event upsets, solve problems such as error accumulation and insufficient anti-interference ability existing in traditional monitoring methods in extreme environments, and provide reliable data support for satellite resource scheduling and fault warning. The whole method has small errors, high reliability, and low resource consumption. Specifically, the method: 1. Introduce a non-intrusive timing anchor mechanism, implant double anchors in the DPDK packet receiving main loop, directly obtain the cycle start and end timestamps through dedicated clock instructions, and avoid system call overhead. Use a 4KB-aligned core exclusive cache page to isolate and store data, and combine memory barrier instructions to ensure the timing measurement accuracy, with the error controlled at the 10 nanosecond level.

[0011] 2. A dynamic baseline calibration mode is proposed. Before the start of the load calculation cycle, reference values are established through operations in the no-packet state and the full-packet state. During operation, a sliding window algorithm with temperature compensation is used to dynamically update the baseline, improving environmental adaptability.

[0012] 3. A dynamic model for environmental compensation of CPU load data is proposed. A linear compensation model for temperature-clock drift and a sensitivity adjustment model for radiation intensity are established to achieve real-time compensation calculation and further improve environmental adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 It is a flowchart of a method for monitoring CPU load based on dynamic compensation of a spaceborne network device provided by an embodiment of the present invention; Figure 2 It is a flowchart of an anchor point counting provided by an embodiment of the present invention; Figure 3 It is a flowchart of a multi-core load aggregation provided by an embodiment of the present invention; Figure 4 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope protected by the present invention.

[0016] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0017] In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0018] Figure 1 It is a flowchart of a method for monitoring CPU load based on dynamic compensation of an on-board network device provided by an embodiment of the present invention. This method is applicable to on-board network devices with DPDK architecture and can be executed by modules deployed in the on-board network device or by other electronic devices. As Figure 1 shown, the method specifically includes: S110. Insert two counting anchor points in the DPDK loop of the on-board network device.

[0019] In this embodiment, an anchor point implantation mechanism is introduced into the DPDK packet receiving main loop of the on-board network device, and two non-blocking counting anchor points are inserted in each DPDK loop: one is located at the entrance of the polling loop and is used to record the number of DPDK loops; the other is located at the end of the data processing flow of the DPDK loop with data packets and is used to record the number of DPDK loops with data packets. For the convenience of distinction and description, in this embodiment, the counting anchor point located at the entrance of the polling loop is called the first counting anchor point, and the counting anchor point located at the end of the data processing flow is called the second counting anchor point.

[0020] As Figure 2 shown, the working mechanism of the two timing anchor points is as follows: each time the CPU enters the DPDK loop, the count of the first counting anchor point is incremented by 1; then, it is queried whether there are data packets in the current DPDK loop; if there are no data packets in the current DPDK loop, it directly enters the next DPDK loop; if there are data packets in the current DPDK loop, the count of the second counting anchor point is incremented by 1, and it enters the next DPDK loop after the data packet processing is completed.

[0021] Furthermore, in this embodiment, the clock counter is directly read through processor-specific instructions to avoid system call overhead; at the same time, memory barrier instructions are used to ensure the accuracy of timing measurement. In addition, the CPU of the on-board network device may include multiple cores. In this embodiment, a cache isolation design is adopted, and each CPU core is allocated its own first counting anchor point and second counting anchor point, as well as an independent cache page to store the anchor point count data of each core; among them, the memory area is aligned in 4KB, occupies the exclusive first-level cache space, and at the same time, cross-core data contamination is prevented through the memory protection mechanism.

[0022] S120. Before the load calculation period of the spaceborne network device starts, pre-run two time periods equal in length to the load calculation period, and perform the following operations respectively within these two time periods: Simulate a state without data packets within one time period, and use the first counting anchor to record the number of DPDK cycles N1 within this time period as a baseline when the load calculation period starts; simulate a state with full data packets within the other time period, and use the second counting anchor to record the number of DPDK cycles N2 within this time period as another baseline when the load calculation period starts.

[0023] Among them, the state without data packets means that each DPDK cycle within a time period has no data packets to be processed; the state with full data packets means that each DPDK cycle within a time period has data packets to be processed. In this embodiment, before calculating the CPU load rate periodically, first simulate these two typical states, and record the number of DPDK cycles in these two states respectively as the initial baselines when the load calculation period is subsequently started. The difference N1 - N2 between these two initial baselines corresponds to a 100% CPU load rate in the initial state (i.e., when the load calculation period of the spaceborne network device starts). For the convenience of distinction and description, in this embodiment, the baseline in the state without data packets is called the first baseline, and the baseline in the state with full data packets is called the second baseline.

[0024] S130. Start the load calculation period, receive the service traffic data of the spaceborne network device, and perform the following operations respectively within each load calculation period: S1-1. Dynamically determine the baseline observation window according to the current CPU temperature, and extract the time period without data packets within the baseline observation window. Here, the baseline observation window refers to a historical time window with the current moment as the end point, which is used to reflect the characteristics of the time period without data packets in the recent period. Specifically, the length of the baseline observation window is adaptively adjusted according to the running time. Optionally, by introducing a temperature compensation factor, when the chip temperature of the CPU exceeds the threshold by ±5°C, automatically shrink the sliding window to 1 / 3, and extract the time period without data packets within this window. Specifically, during the counting process of the second counting anchor, if the count value of the second counting anchor remains unchanged within a time period, it is considered that this time period is a time period without data packets. The baseline observation window with the current moment as the end point can cover multiple time periods without data packets.

[0025] S1-2. Dynamically update the first baseline of the current load calculation cycle according to the first baseline N1 at startup and the number of DPDK cycles during the no-packet period. Optionally, first convert the number of DPDK cycles in all no-packet periods within the baseline observation window to the number of DPDK cycles current_cycles in the entire load calculation cycle. Exemplarily, sum the number of DPDK cycles in all no-packet periods, divide the sum by the total duration of all no-packet periods, and then multiply by the duration of a load calculation cycle to obtain current_cycles. Then use the following formula to update the first baseline N11 of the current load calculation cycle: where α is a dynamic weight coefficient, which can take values between 0.75 and 0.9, and the specific value is automatically adjusted according to environmental parameters.

[0026] S1-3. Initially determine the CPU load rate of the current load calculation cycle according to the first baseline of the current load calculation cycle, the second baseline, and the number of DPDK cycles in the current load calculation cycle. Optionally, use the first counting anchor point to record the number of DPDK cycles in the current load calculation cycle to obtain the actual number of cycles N, then: where, represents the CPU load rate of the current load calculation cycle, represents the number of DPDK cycles in the current load calculation cycle, represents the second baseline, represents the first baseline of the current load calculation cycle. Where, corresponds to 100% CPU load rate in the current load calculation cycle.

[0027] Furthermore, when the CPU of the spaceborne network device includes multiple cores, the operations of S1-1 to S1-2 can be executed separately for each CPU core, and the CPU load rate of each core is collected through a lock-free data method. As Figure 3 shown, each CPU core independently writes its own data into the local memory, and then the aggregator reads the data in batches. At the same time, the data writing operation ensures atomicity to avoid lock contention. After reading the data, the aggregator first normalizes the multi-core data to eliminate the influence of inter-core frequency differences, and then averages the CPU load rates of all cores to obtain the overall CPU load rate.

[0028] S1-4. Compensate the preliminarily determined CPU load rate according to the current temperature and spatial radiation to obtain the actual CPU load rate for the current load calculation cycle. As described above, the CPU load rate determined by S1-3 is based on the baseline cycle data without message processing. In this no-message state, the CPU may mainly execute basic instructions such as loop judgment and branch jump internally, and the operations are relatively simple. When there is message processing, the CPU will also involve data packet copying, verification, memory access, cache operations, etc., which may lead to more arithmetic, logical, and memory operations, thereby increasing the load on some hardware units (such as floating-point units, cache controllers, etc.), and there will be temperature differences. At the same time, the radiation situation in the satellite environment will also affect the CPU state. Therefore, in this module, considering the temperature and radiation effects comprehensively, an environmental compensation model for CPU load data is proposed.

[0029] In a specific embodiment, the model includes temperature compensation and radiation compensation. Among them, the temperature compensation aims to establish a linear relationship model between the chip temperature and clock drift, while the radiation compensation aims to adjust the calculation sensitivity of the load rate according to the predicted value of the spatial radiation intensity. Under the two compensations, the final load rate calculation formula is as follows: Among them, f(T) is a piecewise temperature compensation function, described as follows: Low-temperature region (<55°C): Disable compensation to avoid overcorrection at low loads; Medium-temperature region (55 - 75°C): Adopt a linear compensation model, and the compensation coefficient f(T)=0.12×(T - 55)+0.05×(dT / dt); High-temperature region (≥75°C): Enable a quadratic term compensation model, and the compensation coefficient f(T)=0.15×(T - 75)^2 + 0.18×(dT / dt), where ^2 represents squaring; RAD is the radiation intensity index. The above model introduces a temperature coupling factor in the radiation compensation, and enhances the radiation sensitivity when T>40°C; λ is the calibration coefficient, t represents time, and dT / dt represents the partial derivative of temperature with respect to time.

[0030] Based on the above model, substitute the preliminary load rate obtained by S1-3, as well as the current temperature and radiation intensity index into the above formula, and the final actual load rate can be obtained.

[0031] After the calculation is completed, this embodiment adopts a real-time output mechanism to output the load rate curve at fixed time intervals (100 ms). The format of the output data is compatible with the on-board system telemetry interface, and provides a load rate mutation warning function, and the warning threshold can be dynamically configured.

[0032] Further, in this embodiment, the values of the counting anchor points can be read in time slices. To ensure data accuracy, after obtaining the data of two timing anchor points, they can be verified and corrected to exclude single-particle interference in the space environment, so as to obtain accurate and effective DPDK loop count values (for example, each DPDK loop count value in S120 and S130 is the value read in time slices and verified and corrected).

[0033] Specifically, this embodiment adopts a three-level protection mechanism to check for errors in the received data. First, hardware-level protection is performed: memory ECC (Error Checking and Correcting) verification is enabled to correct single-bit flip errors in real time; then software-level verification is performed: the hash values of key data structures are calculated periodically to detect multi-bit errors; finally, timing continuity verification is performed: the time difference distribution between adjacent cycles is analyzed by statistical methods, and by comparing with the time difference distribution between each cycle in the baseline database, it is judged whether the count value data is reasonable.

[0034] After the detection is completed, an error recovery process is performed. Optionally, first, when an error in the count value data received in the memory is detected, a data rollback mechanism is automatically triggered to discard the error data and roll back to the previous correct data; when the verification fails three times in a row, the count value storage area is re-initialized. During this period, the error event is recorded in the radiation log for subsequent reliability analysis.

[0035] After three-level error detection and error recovery, according to the finally retained count value, the CPU load rate.

[0036] In summary, this embodiment provides a method for monitoring the CPU load based on dynamic compensation for a spaceborne network device, which can accurately monitor the true load rate of the DPDK exclusive core in the space radiation environment with single-event upsets, solve the problems of error accumulation and insufficient anti-interference ability existing in the traditional monitoring method in extreme environments, provide reliable data support for satellite resource scheduling and fault warning, and the whole method has small error, high reliability, and low resource consumption. Specifically, the method: 1. Introduce a non-intrusive timing anchor mechanism, implant double anchors in the main DPDK packet receiving loop, directly obtain the start and end time stamps of the period through dedicated clock instructions, and avoid system call overhead. Use a 4KB-aligned core-exclusive cache page to isolate and store data, and combine memory barrier instructions to ensure the timing measurement accuracy, with the error controlled at the 10-nanosecond level.

[0037] 2. A dynamic baseline calibration mode is proposed. Before the start of the load calculation cycle, the reference values are established through the operation in the no-packet state and the full-packet state. During operation, a sliding window algorithm with temperature compensation is used to dynamically update the baseline. By introducing a temperature weight factor (adjustable from 0.75 to 0.9), when the chip temperature fluctuation exceeds ±5°C, the window is automatically reduced to 1 / 3, improving the environmental adaptability.

[0038] 3. Through a three-level anti-radiation verification system, three-level protection of hardware ECC verification (single-bit error correction), software hash verification (integrity of key data structures), and timing continuity verification (analysis of the adjacent cycle time difference distribution) is achieved. The timestamp data is stored in a triple modular redundant manner, and the error recovery process can complete the baseline rollback within 2 ms, eliminating the cumulative error amplification phenomenon caused by memory bit flips, ensuring the continuous operation of the system, and solving the problem of monitoring data contamination caused by single-event upsets.

[0039] 4. A dynamic model for environmental compensation of CPU load data is proposed. A linear compensation model for temperature-clock drift and a sensitivity adjustment model for radiation intensity (λ coefficient) are established to achieve real-time compensation calculation and further improve the environmental adaptability.

[0040] Figure 4 The structural schematic diagram of an electronic device provided by an embodiment of the present invention is as Figure 4 shown. The device includes a processor 60, a memory 61, an input device 62, and an output device 63. The number of processors 60 in the device can be one or more. Figure 4 Here, one processor 60 is taken as an example. The processor 60, the memory 61, the input device 62, and the output device 63 in the device can be connected through a bus or other means. Figure 4 Here, the connection through the bus is taken as an example.

[0041] The memory 61, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the CPU load monitoring method based on dynamic compensation of the spaceborne network device in the embodiment of the present invention. The processor 60 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 61, that is, implementing the above-mentioned CPU load monitoring method based on dynamic compensation of the spaceborne network device.

[0042] The memory 61 may mainly include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 61 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some instances, the memory 61 may further include a memory remotely provided with respect to the processor 60, and these remote memories may be connected to the device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0043] The input device 62 can be used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the device. The output device 63 may include a display device such as a display screen.

[0044] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the CPU load monitoring method based on dynamic compensation of the on-board network device in any embodiment.

[0045] The computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.

[0046] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal may take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable medium may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0047] The program code contained on a computer-readable medium can be transmitted using any appropriate medium, including but not limited to wireless, wire, optical fiber cable, RF, and the like, or any suitable combination of the foregoing.

[0048] The computer program code for performing the operations of the present invention can be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the C language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., connected through the Internet using an Internet service provider).

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. A CPU load monitoring method based on dynamic compensation for a spaceborne network device, characterized in that, Including: Obtain a first baseline and a second baseline at the start of the load calculation cycle of the spaceborne network device, where the first baseline is the number of DPDK cycles in which the CPU of the spaceborne network device remains in a packet-free state within one load calculation cycle, and the second baseline is the number of DPDK cycles in which the CPU of the spaceborne network device remains in a full-packet state within one load calculation cycle; Perform the following operations respectively in each load calculation cycle: S1-1. Dynamically determine a baseline observation window according to the current CPU temperature, and extract the packet-free time period within the baseline observation window; S1-2. Dynamically update the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles in the packet-free time period; S1-3. Preliminarily determine the CPU load rate of the current load calculation cycle according to the first baseline of the current load calculation cycle, the second baseline, and the number of DPDK cycles in the current load calculation cycle; S1-4. Compensate the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation cycle.

2. The method according to claim 1, characterized in that, The obtaining of the first baseline and the second baseline at the start of the load calculation cycle of the spaceborne network device includes: Insert a first counting anchor point and a second counting anchor point within the DPDK cycle of the spaceborne network device, where the first counting anchor point is used to record the number of DPDK cycles, and the second counting anchor point is used to record the number of DPDK cycles with packets; Before the start of the load calculation cycle of the spaceborne network device, perform the following operations respectively in two time periods of the same length as the load calculation cycle: Simulate a packet-free state in one time period, and use the first counting anchor point to record the number of DPDK cycles in this time period as the first baseline at the start of the load calculation cycle; Simulate a full-packet state in the other time period, and use the second counting anchor point to record the number of DPDK cycles in the other time period as the second baseline at the start of the load calculation cycle.

3. The method according to claim 1, wherein The dynamically determining the baseline observation window according to the current CPU temperature includes: When the CPU temperature fluctuation exceeds the set threshold, reduce the length of the baseline observation window.

4. The method according to claim 1, wherein The dynamically updating the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles in the packet-free time period includes: Convert the number of DPDK cycles in the packet-free time period into the number of DPDK cycles within one load calculation cycle; Perform a weighted average on the converted number of DPDK cycles and the first baseline at startup as the first baseline of the current load calculation cycle.

5. The method according to claim 1, characterized in that, The preliminarily determining the CPU load rate of the current load calculation cycle according to the first baseline of the current load calculation cycle, the second baseline, and the number of DPDK cycles in the current load calculation cycle includes: Among them, represents the CPU load rate of the current load calculation cycle, represents the number of DPDK loops within the current load calculation cycle, represents the second baseline, represents the first baseline of the current load calculation cycle.

6. The method according to claim 1, wherein Each number of DPDK cycles is recorded by the first counting anchor point and the second counting anchor point set within the DPDK cycle of the spaceborne network device, where the working mode of the two counting anchor points is: Each time the CPU enters the DPDK cycle, the first counting anchor point is incremented by 1; If there is no data packet in the current DPDK loop, directly enter the next DPDK loop; If there is a data packet in the current DPDK loop, increment the second counting anchor by 1, and enter the next DPDK loop after the data packet is processed.

7. The method according to claim 1, characterized in that, The number of each DPDK loop is obtained by recording the first counting anchor and the second counting anchor set in the DPDK loop of the on-board network device; The method further includes: In response to the counting anchor data from the on-board network device, perform memory ECC check, hash value check, and statistical method school check on the data to detect single-event interference; Perform error recovery on the verified data; Perform subsequent operations using the recovered data.

8. The method according to claim 1, wherein The compensating the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation period includes: Determine the actual load rate of the current load calculation period according to the following formula: Actual load rate = preliminarily determined CPU load rate × [1 + f(T) + λ × RAD × (1 + A × (T - B))] where T is the current temperature, f(T) is the temperature compensation function, RAD is the radiation intensity index, and λ, A, and B are calibration coefficients.

9. The method according to claim 8, characterized in that, f(T) is a piecewise temperature compensation function, where In the low-temperature region, f(T) = 0; In the medium-temperature region, f(T) is a linear temperature compensation function; In the high-temperature region, f(T) is a quadratic temperature compensation function.

10. An electronic device, characterized in that, Includes: One or more processors; A memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method for monitoring the CPU load based on dynamic compensation of the on-board network device according to any one of claims 1-9.

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