Back contact battery of opening semiconductor without etching and preparation method of back contact battery

Abstract

The invention belongs to the technical field of back contact cell preparation, and particularly relates to a back contact cell of an opening semiconductor without etching and a preparation method thereof, and the method comprises the steps: S103, carrying out the polishing or texturing of the back surface of a silicon wafer obtained in S102; s104, depositing an intrinsic crystalline silicon layer on the back surface of the silicon wafer; s105, the non-target deposition area is masked through a hard mask plate, and N-type crystalline silicon layers which are alternately arranged are deposited on the back face; replacing the mask of the hard mask plate to form a P-type crystalline silicon layer and an overlapping region; s106, depositing a conductive film layer on the back surface of the silicon wafer; s107, an opening is formed in the conductive film layer to form an isolation groove, and the width W4 of the isolation groove is controlled to range from 0.03 mm to 0.15 mm; and S108, forming a metal electrode on the back surface. According to the invention, the back semiconductor does not need to be opened by etching, the technological process is greatly simplified, etching damage is avoided, and the cell conversion efficiency, the cell stability and the production yield are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact battery preparation, and particularly relates to a back-contact battery that does not require etching an opening in a semiconductor and a preparation method thereof. Background Art

[0002] Currently, the general process flow of a back-contact battery is as follows: S1. Double-sided polishing of a silicon wafer; S2. Protecting the back side of the silicon wafer by plating a first mask layer, where the first mask layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide; S3. Texturing and cleaning the silicon wafer to form a pyramid-shaped textured surface on the opposite side of the first mask layer, and then removing the first mask layer to form a silicon wafer with a single-sided textured and single-sided polished structure; S4. Sequentially plating a first semiconductor layer and a second mask layer on the back side of the silicon wafer, where the second mask layer is generally silicon nitride; S5. Laser or etching an opening on the back side of the silicon wafer to remove the second mask layer and part of the first semiconductor layer to form a second semiconductor opening region; S6. Cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening region; S7. Sequentially forming an amorphous layer passivation layer and an antireflection layer on the front side of the silicon wafer, and forming a second semiconductor layer on the back side; S8. Laser or etching an opening on the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region arranged alternately with the second semiconductor opening region; S9. Cleaning the silicon wafer to remove the second mask layer in the first semiconductor opening region; S10. Depositing a conductive film layer on the back side of the silicon wafer; S11. Forming an isolation groove between the first semiconductor opening region and the second semiconductor opening region by laser or etching; S12. Forming metal electrodes on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0003] However, in the above existing preparation method, the first semiconductor and the second semiconductor need to be formed through two etching opening and cleaning processes, and the process flow is cumbersome; and after S5, when laser or etching an opening on the back side of the silicon wafer, removing the second mask layer and part of the first semiconductor layer to form a second semiconductor opening region, passivation defects are likely to occur at the edge of the first semiconductor layer, thereby affecting the battery conversion efficiency.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. [[ID= forty]]Summary of the Invention

[0005] The object of the present invention is to overcome the defects existing in the prior art that in the preparation of back-contact batteries, two etching openings are required to be formed, resulting in a cumbersome process flow, and passivation defects are likely to occur at the edges of the first semiconductor layer, thereby affecting the battery conversion efficiency. The present invention provides a back-contact battery that does not require etching openings in the semiconductor and a preparation method thereof, which can realize that the back semiconductor does not require etching openings, greatly simplifies the process flow, and at the same time does not cause etching damage, thereby improving the battery passivation effect, reducing the leakage current, and further improving the battery conversion efficiency, battery stability, and production yield.

[0006] To achieve the above object, in a first aspect, the present invention provides a method for preparing a back-contact battery that does not require etching openings in the semiconductor, including the following steps: S101. Provide a double-sided textured silicon wafer; S102. Sequentially form a passivation layer and an antireflection layer on the front surface of the silicon wafer; S103. Polish or texture the back surface of the silicon wafer obtained in S102 to form a polished surface or a textured surface, and then perform cleaning; S104. Deposit an intrinsic crystalline silicon layer on the back surface of the silicon wafer; S105. Mask non-target deposition regions through a hard mask plate, and deposit alternately arranged N-type crystalline silicon layers outside the back surface intrinsic crystalline silicon layer; After that, replace the hard mask plate to mask part of the N-type crystalline silicon layer to form a P-type crystalline silicon layer arranged alternately with the N-type crystalline silicon layer, and make the two ends of the P-type crystalline silicon layer extend outward respectively to cover part of the back surface of the adjacent N-type crystalline silicon layer and the covered area is an overlapping area; the corresponding crystalline silicon layers of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer independently include amorphous silicon and / or microcrystalline silicon; S106. Deposit a conductive film layer on the back surface of the silicon wafer; S107. Open an isolation groove in the conductive film layer outside the junction region between the longitudinal edges of the N-type crystalline silicon layer and the P-type crystalline silicon layer, control the width W4 of the isolation groove to be 0.03 - 0.15 mm, and the width W5 of the isolation groove above the N-type crystalline silicon layer is 5% - 95% of the width W4 of the isolation groove, and the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove is 1:(0.1 - 1); S108. Form a metal electrode on the back surface.

[0007] In some preferred embodiments of the present invention, the width W2 of the overlapping area is 0.05 - 0.30 mm.

[0008] In some preferred embodiments of the present invention, the width of the N-type crystalline silicon layer is 0.2 - 0.8 mm, and / or, the width W1 of the P-type crystalline silicon layer between adjacent N-type crystalline silicon layers is 0.3 - 1 mm.

[0009] In some preferred embodiments of the present invention, the thickness ratio of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer is 1:(0.5 - 5):(0.5 - 5).

[0010] Preferably in the present invention, the thickness of the intrinsic crystalline silicon layer is 5 - 20 nm, the thickness of the N-type crystalline silicon layer is 5 - 40 nm, and the thickness of the P-type crystalline silicon layer is 5 - 40 nm.

[0011] In some preferred embodiments of the present invention, after forming the P-type crystalline silicon layer in S105, a first semiconductor opening region that does not cover the P-type crystalline silicon layer is naturally formed in the mask region on the back surface of the N-type crystalline silicon layer, and a second semiconductor opening region is formed between adjacent N-type crystalline silicon layers. The width W3 of the first semiconductor opening region is 0.1 - 0.7 mm.

[0012] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S106 is 20 - 500 nm.

[0013] In some preferred embodiments of the present invention, in S102, the passivation layer is a silicon dielectric film layer and / or alumina, and the antireflection layer is a silicon dielectric film layer. The silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0014] In some preferred embodiments of the present invention, in S102, the passivation layer and the antireflection layer are formed by one-time continuous coating using a tube-type PECVD.

[0015] In some preferred embodiments of the present invention, the passivation layer is a stack of a tunneling silicon oxide layer and a crystalline silicon layer arranged in sequence or a stack of a tunneling silicon oxide layer and an alumina layer arranged in sequence. Among them, the thickness of the tunneling silicon oxide layer is 0.3 - 2 nm, the thickness of the crystalline silicon layer is 2 - 10 nm, and the thickness of the alumina layer is 2 - 10 nm.

[0016] In some preferred embodiments of the present invention, the thickness ratio of the tunneling silicon oxide layer to the intrinsic crystalline silicon layer is 1:(1 - 20).

[0017] In some preferred embodiments of the present invention, the antireflection layer includes a stack of silicon nitride, silicon oxynitride, and silicon oxide arranged in sequence. The thickness of the silicon nitride is 50 - 90 nm, the thickness of the silicon oxynitride is 10 - 60 nm, and the thickness of the silicon oxide is 30 - 100 nm.

[0018] In a second aspect, the present invention provides a back-contact battery without etching an opening semiconductor, which is obtained by the method for preparing a back-contact battery without etching an opening semiconductor described in the first aspect.

[0019] Beneficial effects: Through the above technical solutions, especially by adopting S102 - S107, the present invention can achieve that the back semiconductor does not need to be etched to form an opening, greatly simplifying the process flow. Meanwhile, no etching damage will be generated, thereby improving the passivation effect of the battery and further enhancing the conversion efficiency of the battery. At the same time, taking advantage of the fact that the acid and alkali resistance of the P - type crystalline silicon layer is significantly better than that of the N - type crystalline silicon layer, the P - type crystalline silicon layer is extended and stacked on the N - type crystalline silicon layer. After the conductive film layer forms an isolation groove, the P - type crystalline silicon layer in the isolation groove area is exposed outside, which is beneficial to improving the stability of the battery. Moreover, the isolation groove is arranged outside the junction area between the edge of the N - type crystalline silicon layer and the P - type crystalline silicon layer. By controlling the proportion of the width W5 of the isolation groove above the N - type crystalline silicon layer and the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove, it is beneficial to reduce the leakage current of the battery and improve the insulation effect between the two semiconductor layers. The P - type crystalline silicon layer is directly deposited outside the N - type crystalline silicon layer without being deposited on the surface of the silicon nitride mask layer, greatly improving the adhesion of the second semiconductor layer and enhancing the product yield and stability.

[0020] Among them, the present invention utilizes the fact that the conductivity of the overlapping area formed by stacking the N - type crystalline silicon layer and the P - type crystalline silicon layer is very poor, providing a good insulation effect. In combination with its cooperation structure with the intrinsic crystalline silicon layer, a good insulation structure is formed. And by adopting an appropriately wide isolation groove and an appropriate ratio of its width to the overlapping area, a good insulation effect can be achieved without longitudinal isolation means. At the same time, this insulation structure takes into account enhancing the back passivation effect and improving the etching resistance effect of S107, thereby improving the conversion efficiency and reliability of the battery. Moreover, the back semiconductor passivation structure all adopts amorphous silicon and / or microcrystalline silicon, enabling the whole process to be formed by a low - temperature process, which simplifies the process. If the back semiconductor passivation structure adopts polysilicon, even with an isolation groove, it does not meet the insulation requirements. Polysilicon has better conductivity and serious leakage current, and thus cannot form a good insulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic structural diagram of the N - type monocrystalline silicon wafer after double - sided texturing provided by the embodiment of the present invention; Figure 2 It is a schematic structural diagram of forming a passivation layer and an antireflection layer on the front side of the silicon wafer in the embodiment of the present invention; Figure 3 It is a schematic structural diagram of forming a polished surface on the back side of the silicon wafer in the embodiment of the present invention; Figure 4This is a schematic diagram of the structure of depositing an intrinsic amorphous silicon layer on the back side of a silicon wafer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of depositing an N-type crystalline silicon layer on the back side of a silicon wafer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of depositing a P-type crystalline silicon layer on the back side of a silicon wafer according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of depositing a conductive film layer on the back side of a silicon wafer according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a structure in which an isolation trench is formed on the back side of a silicon wafer according to an embodiment of the present invention; Figure 9 Schematic diagram of the structure of forming a metal electrode on the back side of a silicon wafer according to an embodiment of the present invention.

[0023] Description of Reference Numerals Silicon wafer 10 , passivation layer 11 , anti-reflection layer 12 , intrinsic amorphous silicon layer 13 , N-type amorphous silicon layer 14 , P-type amorphous silicon layer 15 , conductive film layer 16 , metal electrode 17 . DETAILED DESCRIPTION

[0024] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0025] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0026] The endpoints of the ranges and any values disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0027] In the present invention, the side close to the silicon wafer is defined as the inner side, and the side far from the silicon wafer is defined as the outer side.

[0028] In a first aspect, the present invention provides a method for preparing a back-contact battery of a semiconductor without etching an opening, comprising the following steps: S101: Provide a silicon wafer with double-sided texturing. S102: Sequentially form a passivation layer and an antireflection layer on the front surface of the silicon wafer. S103: Polish or texture the back surface of the silicon wafer obtained in S102 to form a polished surface or a textured surface, and then perform cleaning. S104: Deposit an intrinsic crystalline silicon layer on the back surface of the silicon wafer. S105: Mask non-target deposition areas through a hard mask plate, and deposit alternately arranged N-type crystalline silicon layers outside the back surface intrinsic crystalline silicon layer. After that, replace the hard mask plate to mask part of the area of the N-type crystalline silicon layer, and form a P-type crystalline silicon layer arranged alternately with the N-type crystalline silicon layer, and make both ends of the P-type crystalline silicon layer extend outward to cover part of the back surface of the adjacent N-type crystalline silicon layer, and the covered area is an overlapping area; the corresponding crystalline silicon layers of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer each independently comprise amorphous silicon and / or microcrystalline silicon. S106: Deposit a conductive film layer on the back surface of the silicon wafer. S107: Open an isolation groove in the conductive film layer outside the junction region between the longitudinal edges of the N-type crystalline silicon layer and the P-type crystalline silicon layer. S108: Form a metal electrode on the back surface.

[0029] In the present invention, the width W4 of the isolation groove is controlled to be 0.03 - 0.15 mm, for example, it can be 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.10 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, 0.15 mm, and the range between any two point values.

[0030] And the width W5 of the isolation groove above the N-type crystalline silicon layer is 5% - 95% of the width W4 of the isolation groove, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, and the range between any two point values. For example, 35% - 95% can be preferably selected.

[0031] Preferably, in the present invention, the ratio of the width W2 of the overlapping region to the width W4 of the isolation groove is 1:(0.1 - 1), preferably 1:(0.30 - 1.00), which is beneficial to ensuring excellent insulation effect without etching openings in the semiconductor and without longitudinal isolation means, and improving the passivation level.

[0032] In step S101 of the present invention, the solution for texturing can refer to the prior art. For example, a solution containing an alkali with a mass concentration of 0.5% - 5% and a texturing additive with a mass concentration of 0.05% - 1% can be used, where the alkali can be potassium hydroxide or sodium hydroxide. In addition, exemplarily, the temperature of the texturing solution is 70 - 90°C. After texturing, the present invention can also perform conventional cleaning. The texturing additive is a commercially available product and will not be elaborated here.

[0033] In some preferred embodiments of the present invention, the width W2 of the overlapping region is 0.05 - 0.30 mm, for example, it can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.10 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, 0.15 mm, 0.16 mm, 0.17 mm, 0.18 mm, 0.19 mm, 0.20 mm, 0.21 mm, 0.22 mm, 0.23 mm, 0.24 mm, 0.25 mm, 0.26 mm, 0.27 mm, 0.28 mm, 0.29 mm, 0.30 mm and the range between any two point values. Adopting an overlapping region with an appropriate width is more conducive to improving the process window, thereby improving the battery efficiency and production yield.

[0034] In some preferred embodiments of the present invention, the width of the N-type crystalline silicon layer is 0.2 - 0.8 mm.

[0035] In some preferred embodiments of the present invention, the width W1 of the P-type crystalline silicon layer located between adjacent N-type crystalline silicon layers is 0.3 - 1 mm.

[0036] In some preferred embodiments of the present invention, the thickness ratio of the intrinsic crystalline silicon layer, N-type crystalline silicon layer, and P-type crystalline silicon layer is 1:(0.5 - 5):(0.5 - 5). Adopting this preferred scheme is more conducive to improving the battery efficiency.

[0037] In some preferred embodiments of the present invention, the thickness of the intrinsic crystalline silicon layer is 5 - 20 nm.

[0038] In some preferred embodiments of the present invention, the thickness of the N-type crystalline silicon layer is 5 - 40 nm.

[0039] In some preferred embodiments of the present invention, the thickness of the P-type crystalline silicon layer is 5 - 40 nm.

[0040] In some preferred embodiments of the present invention, after the P-type crystalline silicon layer is formed in S105, a first semiconductor opening region that does not cover the P-type crystalline silicon layer is naturally formed in the mask region on the back surface of the N-type crystalline silicon layer, and a second semiconductor opening region is formed between adjacent N-type crystalline silicon layers.

[0041] Further preferably, the width W3 of the first semiconductor opening region is 0.1 - 0.7 mm.

[0042] In the present invention, the formation methods of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer can each refer to those in the prior art respectively. For example, they can be formed by PECVD, hot wire CVD, etc., and PECVD technology is preferably used.

[0043] In the present invention, it can be understood that the hard mask plate masking in S105 means covering and attaching the hard mask plate on the silicon wafer, and the covered area is the non-target deposition area.

[0044] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S106 is 20 - 500 nm. The conductive film layer is preferably a transparent conductive film layer, and can be a conventional conductive film layer in the art such as ITO, etc., all of which can be used in the present invention and will not be elaborated here.

[0045] The formation method of the isolation groove in the present invention can adopt laser or chemical etching technology, etc.

[0046] In some preferred embodiments of the present invention, in S102, the passivation layer is a silicon dielectric film layer and / or alumina, and the antireflection layer is a silicon dielectric film layer.

[0047] Further preferably, the silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide. It can be understood that the silicon dielectric film layers of the passivation layer and the antireflection layer can be the same or different.

[0048] In S102, the passivation layer and the antireflection layer can be formed by equipment such as ALD, PECVD, and LPCVD. In some preferred embodiments of the present invention, in S102, the passivation layer and the antireflection layer are formed by one-time continuous coating with a tube-type PECVD, which is more conducive to simplifying the process flow and at the same time taking into account improving the passivation quality. Further preferably, the deposition temperatures of the passivation layer and the antireflection layer can each independently be 400 - 500 °C.

[0049] In some preferred embodiments of the present invention, the passivation layer is a stack of a tunneling silicon oxide layer and a crystalline silicon layer arranged in sequence or a stack of a tunneling silicon oxide layer and an alumina layer arranged in sequence. Adopting this preferred solution, combined with the specific preparation method of the present invention, it is more conducive to reducing UV attenuation, thereby improving the battery reliability. Among them, the crystalline silicon layer includes amorphous silicon and / or microcrystalline silicon.

[0050] Preferably, in the passivation layer, the thickness of the tunneling silicon oxide layer is 0.3 - 2 nm, the thickness of the crystalline silicon layer is 2 - 10 nm, and the thickness of the aluminum oxide layer is 2 - 10 nm.

[0051] In some preferred embodiments of the present invention, the thickness ratio of the tunneling silicon oxide layer to the intrinsic crystalline silicon layer is 1:(1 - 20), which is more conducive to improving passivation and thus improving the battery efficiency.

[0052] In some preferred embodiments of the present invention, the antireflection layer includes a stack of silicon nitride, silicon oxynitride, and silicon oxide arranged in sequence. Using the antireflection layer with this specific combination is more conducive to reducing reflection and improving the battery efficiency.

[0053] Further preferably, in the antireflection layer, the thickness of the silicon nitride is 50 - 90 nm, the thickness of the silicon oxynitride is 10 - 60 nm, and the thickness of the silicon oxide is 30 - 100 nm.

[0054] The polishing solution used in the polishing treatment S103 of the present invention can refer to the prior art. For example, a solution containing an alkali with a mass concentration of 2% - 10% and a polishing additive with a mass concentration of 0% - 1% can be used, where the alkali can be potassium hydroxide or sodium hydroxide. In addition, by way of example, the temperature of the polishing solution is 70 - 90 °C. The polishing additive is a commercially available product and will not be elaborated here.

[0055] In a second aspect, the present invention provides a back - contact battery without etching openings in the semiconductor, which is prepared by the method for preparing a back - contact battery without etching openings in the semiconductor described in the first aspect. The back - contact battery of the present invention has no etching defects, can improve the battery passivation effect, reduce the leakage current, and further improve the battery conversion efficiency, battery stability, and production yield.

[0056] The following details the embodiments of the present invention. They are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0057] Example 1 A back - contact battery is prepared by the following preparation method: S101, as Figure 1 shown, provide a double - side textured silicon wafer 10 (N - type single - crystal silicon); The solution for texturing uses an aqueous solution of sodium hydroxide with a temperature of 80 °C and a mass concentration of 1% and a texturing additive with a mass concentration of 0.25%. After texturing, the surface of the silicon wafer 10 is cleaned; S102, as Figure 2As shown in the figure, a passivation layer 11 and an antireflection layer 12 are successively formed on the front surface of the silicon wafer 10. The passivation layer 11 and the antireflection layer 12 are formed by one-time continuous coating using tube PECVD, and the deposition temperature is 450 °C. A tunneling oxide layer with a thickness of 1 nm and an amorphous silicon layer with a thickness of 5 nm are successively formed on the front surface of the silicon wafer 10 as the passivation layer 11, and then a silicon nitride layer with a thickness of 60 nm, a silicon oxynitride layer with a thickness of 10 nm, and a silicon oxide layer with a thickness of 80 nm are successively formed as the antireflection layer 12; S103, as Figure 3 shown in the figure, the back surface of the silicon wafer 10 is polished so that a polished surface is formed on the back surface, and then the surface of the silicon wafer 10 is cleaned; the polishing treatment is carried out with an aqueous solution of sodium hydroxide with a temperature of 70 °C, a mass concentration of 3%, and a polishing additive with a mass concentration of 0.5%; S104, as Figure 4 shown in the figure, an intrinsic amorphous silicon layer 13 with a thickness of 10 nm is deposited on the back surface of the silicon wafer 10 by PECVD technology; after calculation, the thickness ratio of the tunneling oxide layer to the intrinsic amorphous silicon layer 13 is 1:10.

[0058] S105, as Figure 5 、 Figure 6 shown in the figure, through the masking of a hard mask plate, an N-type amorphous silicon layer 14 with a thickness of 15 nm is deposited on the back surface of the silicon wafer 10 by chemical vapor deposition technology, and then the hard mask plate is replaced to form a P-type amorphous silicon layer 15 with a thickness of 15 nm that is alternately arranged with the N-type amorphous silicon layer 14. The two ends of the P-type amorphous silicon layer 15 extend outward to cover a part of the back surface of the adjacent N-type amorphous silicon layer 14 and the covered area is an overlapping area, and a first semiconductor opening area that does not cover the P-type amorphous silicon layer 15 is naturally formed in the masked area on the back surface of the N-type amorphous silicon layer 14. The width W3 of the first semiconductor opening area is 0.3 mm. The width W2 of the overlapping area is 0.1 mm, the width of the N-type amorphous silicon layer 14 is 0.5 mm, and the width W1 of the P-type amorphous silicon layer 15 located between adjacent N-type amorphous silicon layers 14 is 0.5 mm. After calculation, the thickness ratio of the intrinsic amorphous silicon layer 13, the N-type amorphous silicon layer 14, and the P-type amorphous silicon layer 15 is 1:1.5:1.5.

[0059] S106, as Figure 7 shown in the figure, a conductive film layer 16 (ITO) with a thickness of 60 nm is deposited on the back surface of the silicon wafer 10; S107, as Figure 8 shown in the figure, using laser etching technology, an isolation groove is formed in the conductive film layer 16 at the junction area between the edge of the N-type amorphous silicon layer 14 and the P-type amorphous silicon layer 15. The width W4 of the isolation groove is 0.05 mm, and the ratio of the width W5 of the isolation groove above the N-type amorphous silicon layer 14 to the width W4 of the isolation groove is 50%; after calculation, the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove is 1:0.5.

[0060] S108, as Figure 9 shown, a metal electrode 17 is formed on the back surface of the silicon wafer 10.

[0061] Example 2 It is carried out with reference to Example 1, except that the amorphous silicon layer in the front passivation layer is replaced with an alumina layer of the same thickness.

[0062] Example 3 It is carried out with reference to Example 1, except that in S105, the width W2 of the overlapping region is controlled to be 0.2 mm, so that the ratio of the width W2 of the overlapping region to the width W4 of the isolation groove is 1:0.25.

[0063] Example 4 It is carried out with reference to Example 1, except that in S107, the width W5 of the isolation groove above the N-type crystalline silicon layer is controlled to be 0.018 mm, so that W5 is 30% of the width W4 of the isolation groove.

[0064] Example 5 It is carried out with reference to Example 1, except that in S103, the back surface of the silicon wafer is textured to form a textured surface, and then it is cleaned.

[0065] Comparative Example 1 It is carried out with reference to Example 1, except that no overlapping region is provided. Specifically, in S105, part of the region of the N-type amorphous silicon layer is masked by replacing the hard mask plate, so that the N-type amorphous silicon layer and the P-type amorphous silicon layer are only arranged alternately without overlapping.

[0066] Comparative Example 2 It is carried out with reference to Example 1, except that in S107, the width W5 of the isolation groove above the N-type amorphous silicon layer is controlled to be 0 mm.

[0067] Comparative Example 3 It is carried out with reference to Example 1, except that in S105, the width W2 of the overlapping region is controlled to be 0.04 mm, so that the ratio of the width W2 of the overlapping region to the width W4 of the isolation groove is 1:1.5.

[0068] Comparative Example 4 It is carried out with reference to Example 1, except that in S105, the NP types of the two amorphous silicon layer semiconductors are swapped, and other structures, film thicknesses, widths, etc. remain unchanged. That is: in S105, the non-target deposition regions are masked by a hard mask plate, and a P-type amorphous silicon layer arranged alternately is deposited outside the back surface intrinsic amorphous silicon layer; After that, a part of the P-type amorphous silicon layer is masked by replacing the hard mask plate, and an N-type amorphous silicon layer is formed to be alternately arranged with the P-type amorphous silicon layer, and both ends of the N-type amorphous silicon layer extend outward to cover a part of the back surface of the adjacent P-type amorphous silicon layer, and the covered area is an overlapping area.

[0069] Test example The back-contact batteries obtained in the above Examples 1-5 and Comparative Examples 1-4 were subjected to performance tests, and the results are shown in Table 1. Among them, the battery efficiency, open-circuit voltage, and leakage current were all obtained through tests according to the IEC60904 standard. The test method for the battery production yield is as follows: 1000 pieces are produced as a batch, and the yield data is collected according to the same qualified standard. The test method for DH attenuation is as follows: Refer to the IEC61215 standard to test the DH test attenuation data before and after 1000h in an environment with a humidity of 85% and a temperature of 85°C, which is used to characterize the battery stability. The smaller the value, the better the battery stability.

[0070] Table 1

[0071] From the above results, it can be seen that compared with the comparative examples, by adopting the embodiment scheme of the present invention, it is possible to avoid etching openings on the back semiconductor, greatly simplify the process flow, and at the same time, no etching damage will be generated, thereby improving the battery passivation effect, reducing the leakage current, and further improving the battery conversion efficiency, battery stability, and production yield.

[0072] Furthermore, according to Example 1 and Examples 2-4, it can be seen that by adopting the preferred scheme of the present invention, it is more conducive to taking into account the improvement of the battery conversion efficiency, battery stability, and production yield.

[0073] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for preparing a back-contact battery of a semiconductor without etching an opening, characterized in that, It includes the following steps: S101. Provide a double-sided textured silicon wafer; S102. Sequentially form a passivation layer and an antireflection layer on the front side of the silicon wafer; S103. Polish or texture the back side of the silicon wafer obtained in S102 to form a polished surface or a textured surface, and then perform cleaning; S104. Deposit an intrinsic crystalline silicon layer on the back side of the silicon wafer; S105. Mask the non-target deposition area through a hard mask plate, and deposit alternately arranged N-type crystalline silicon layers outside the back-side intrinsic crystalline silicon layer; After that, replace the hard mask plate to mask part of the area of the N-type crystalline silicon layer to form a P-type crystalline silicon layer arranged alternately with the N-type crystalline silicon layer, and make the two ends of the P-type crystalline silicon layer extend outward respectively to cover part of the back side of the adjacent N-type crystalline silicon layer and the covered area is an overlapping area; the corresponding crystalline silicon layers of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer each independently include amorphous silicon and / or microcrystalline silicon; S107. Open an isolation groove on the conductive film layer outside the junction area between the longitudinal edges of the N-type crystalline silicon layer and the P-type crystalline silicon layer, control the width W4 of the isolation groove to be 0.03 - 0.15 mm, and the width W5 of the isolation groove above the N-type crystalline silicon layer is 5% - 95% of the width W4 of the isolation groove, and the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove is 1:(0.1 - 1); S108. Form a metal electrode on the back side. The width W2 of the overlapping area is 0.05 - 0.30 mm.

2. The method for preparing a back-contact battery of a semiconductor without an etched opening according to claim 1, wherein The width of the N-type crystalline silicon layer is 0.2 - 0.8 mm, and / or the width W1 of the P-type crystalline silicon layer between adjacent N-type crystalline silicon layers is 0.3 - 1 mm.

3. The method for preparing a back-contact battery of a semiconductor without an etched opening according to claim 1, characterized in that, The thickness ratio of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer is 1:(0.5 - 5):(0.5 - 5); and / or, 4. The method for preparing a back-contact battery of a semiconductor without an etched opening according to claim 1, wherein The thickness of the intrinsic crystalline silicon layer is 5 - 20 nm, the thickness of the N-type crystalline silicon layer is 5 - 40 nm, and the thickness of the P-type crystalline silicon layer is 5 - 40 nm. After forming the P-type crystalline silicon layer in S105, a first semiconductor opening area that does not cover the P-type crystalline silicon layer is naturally formed in the masked area on the back side of the N-type crystalline silicon layer, and a second semiconductor opening area is formed between adjacent N-type crystalline silicon layers. The width W3 of the first semiconductor opening area is 0.1 - 0.7 mm; 5. The method for preparing a back-contact battery of a semiconductor without an etched opening according to claim 1, wherein and / or, In S106, the thickness of the conductive film layer is 20 - 500 nm. In S102, the passivation layer is a silicon dielectric film layer and / or alumina, and the antireflection layer is a silicon dielectric film layer. The silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide; 6. The method for preparing a back contact battery of a semiconductor without an etched opening according to claim 1, wherein, and / or, In S102, the passivation layer and the antireflection layer are formed by one-time continuous coating with a tube-type PECVD. The passivation layer is a stack of a tunneling oxide silicon layer and a crystalline silicon layer arranged in sequence or a stack of a tunneling oxide silicon layer and an alumina layer arranged in sequence. Among them, the thickness of the tunneling oxide silicon layer is 0.3 - 2 nm, the thickness of the crystalline silicon layer is 2 - 10 nm, and the thickness of the alumina layer is 2 - 10 nm.

7. The method for preparing a back contact battery of a semiconductor without an etched opening according to claim 6, wherein The thickness ratio of the tunneling oxide silicon layer to the intrinsic crystalline silicon layer is 1:(1 - 20).

8. The method for preparing a back-contact battery of a semiconductor without an etched opening according to claim 7, characterized in that, ​ 9. The method for preparing a back contact battery of a semiconductor without an etched opening according to claim 6 or 7, characterized in that, The antireflection layer includes a stack of silicon nitride, silicon oxynitride, and silicon oxide arranged in sequence. The thickness of the silicon nitride is 50 - 90 nm, the thickness of the silicon oxynitride is 10 - 60 nm, and the thickness of the silicon oxide is 30 - 100 nm.

10. A back-contact battery for a semiconductor without an etched opening, characterized in that, It is obtained by the method for preparing a back-contact battery without etching an opening semiconductor as described in any one of claims 1 - 9.

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