Convolutional decoder, decoding method and electronic equipment

Abstract

The invention discloses a convolutional decoder, a decoding method and electronic equipment, relates to the technical field of communication, and is used for reducing the time overhead of convolutional code decoding. The convolutional decoder is used for decoding a coding sequence, the coding sequence is divided into P first subsequences, tail sequences of the P first subsequences are P second subsequences, and the convolutional decoder comprises the following steps: for a first round of decoding, P Viterbi decoders respectively decode the P second subsequences and update cumulative fraction vectors of the P second subsequences; starting from the second round of decoding, the pth Viterbi decoder performs cyclic decoding on the coding sequence from the initial position of the pth first sub-sequence, and updates the cumulative fraction vectors of the P first sub-sequences; and the P comparators compare the cumulative score vectors of the two subsequences with the same ending position of the last two rounds of decoding, and if the maximum probability state transition paths of the two subsequences with the same ending position are the same, the decoding sequence of the maximum probability state transition path is output.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a convolutional decoder, a decoding method and an electronic device. Background Art

[0002] Convolutional codes are a channel coding technique widely used in various wireless communication scenarios. Tail-biting convolutional codes are an optimized form of convolutional codes. For the transmitter's convolutional encoder, initializing its registers with the last few bits of the coded sequence reduces coding overhead. However, for the receiver's convolutional decoder, the decoding process requires multiple iterations to determine whether the initial state of the convolutional decoder's convolutional code status registers is correct, which is time-consuming. Summary of the Invention

[0003] Embodiments of the present application provide a convolutional decoder, a decoding method, and an electronic device for reducing the time overhead of convolutional code decoding.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a convolutional decoder is provided for decoding a coding sequence, wherein the coding sequence is divided into P first subsequences, and the tail sequences of the P first subsequences are P second subsequences. The convolutional decoder includes: P Viterbi decoders and P comparators, where P is an integer greater than 1. For a first round of decoding, at least one of the P Viterbi decoders is used to decode the P second subsequences respectively and update cumulative score vectors of the P second subsequences. The cumulative score vector of the second subsequence represents the cumulative score of each state transition path obtained by decoding the second subsequence. The cumulative score of each state transition path represents the probability of obtaining a set of decoding sequences by decoding along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second subsequences is all 0; At the beginning of the second round of decoding, the pth Viterbi decoder starts from the starting position of the pth first subsequence and cyclically decodes the encoded sequence. The cumulative score vectors of the P first subsequences are updated in each round of decoding. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence decoded in the first round; p is an integer less than or equal to P; P comparators are used to compare the cumulative score vectors of two subsequences with the same end position obtained in the most recent two rounds of decoding. If both satisfy the same maximum probability state transition path for the two subsequences with the same end position, the decoding sequence corresponding to the maximum probability state transition path is output.

[0006] The convolution decoder provided by the embodiment of the present application has the following characteristics: in the first round of decoding, the sum of the lengths of the P second subsequences is less than the length of the entire coding sequence. Therefore, the time to complete the first round of decoding by decoding the P second subsequences is shorter. Starting from the second round of decoding, the P Viterbi decoders start from P different first subsequences and perform cyclic decoding on the coding sequence in parallel, and update the cumulative score vectors of the P first subsequences in each round of decoding. P comparators compare the cumulative score vectors of the two subsequences with the same end position in the last two rounds of decoding to determine whether the decoding has converged. The time for each round of decoding is reduced to one-Pth of the original time. This reduces the time overhead of convolutional code decoding.

[0007] In a possible implementation, P Viterbi decoders are used to decode the P second subsequences in parallel, respectively, which can further reduce the time of the first round of decoding.

[0008] In one possible implementation, the P first subsequences have the same length, and / or the P second subsequences have the same length. Each Viterbi decoder takes the same time to decode the subsequences, and the decoding efficiency of the entire convolutional decoder is the highest.

[0009] In one possible implementation, the system further includes P first registers and P second registers, where each first register is used to store a cumulative score vector for a subsequence in the current decoding round, and each second register is used to store a cumulative score vector for a subsequence in the previous decoding round. During a new decoding round, the cumulative score vectors in a first register are moved to a paired second register, and the unused first registers are used to store the cumulative score vectors obtained in the current decoding round. This can minimize the storage overhead of the cumulative score vectors.

[0010] In a possible implementation manner, the system further includes P output buffers, each configured to store a decoded sequence output by each Viterbi decoder.

[0011] In a possible implementation manner, an input buffer is further included, for storing the coding sequence.

[0012] In a possible implementation, a timer is further included to trigger the end of decoding when decoding cannot be completed within a preset time, thereby preventing the decoding time from being too long.

[0013] In a second aspect, a decoding method is provided, which is applied to the convolutional decoder as described in the first aspect and any embodiment thereof, and is used to decode a coding sequence, where the coding sequence is divided into P first subsequences, and the tail sequences of the P first subsequences are P second subsequences. The method includes: for a first round of decoding, at least one Viterbi decoder among the P Viterbi decoders decodes the P second subsequences respectively, and updates the cumulative score vectors of the P second subsequences, where the cumulative score vector of the second subsequence represents the cumulative score of each state transition path obtained by decoding the second subsequence, and the cumulative score of each state transition path represents the probability of obtaining a group of decoding sequences by decoding along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second subsequences is all 0; At the beginning of the second round of decoding, the pth Viterbi decoder starts from the starting position of the pth first subsequence and cyclically decodes the encoded sequence. The cumulative score vectors of the P first subsequences are updated in each round of decoding. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence decoded in the first round; p is an integer less than or equal to P; P comparators respectively compare the cumulative score vectors of the two subsequences with the same end position obtained in the most recent two rounds of decoding. If both satisfy the same maximum probability state transition path for the two subsequences with the same end position, the decoded sequence corresponding to the maximum probability state transition path is output.

[0014] In a possible implementation, at least one of the P Viterbi decoders decodes the P second subsequences respectively, including: P Viterbi decoders, configured to decode the P second subsequences respectively in parallel.

[0015] In a third aspect, an electronic device is provided, comprising a receiver, wherein the receiver comprises the convolutional decoder as described in the first aspect and any embodiment thereof.

[0016] In a fourth aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described in the second aspect and any embodiment thereof.

[0017] In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the second aspect and any embodiment thereof are implemented.

[0018] In a sixth aspect, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the steps of the method described in the second aspect and any embodiment thereof.

[0019] In a seventh aspect, a chip system is provided, comprising a processor configured to support an electronic device in implementing the functions described in the second aspect. In one possible design, the device further comprises an interface circuit configured to receive signals from other devices (e.g., a memory) or to send signals to other devices (e.g., a communication interface). The chip system may include a chip and may also include other discrete components.

[0020] The technical effects of the second to seventh aspects refer to the technical effects of the first aspect and any of its embodiments and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a convolutional encoder provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of a convolutional encoder for a tail-biting convolutional code provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of a state transition vector provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of a state transition matrix and cumulative score vector provided in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of a structure for decoding a coding sequence provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 7 A schematic structural diagram of a mobile communication module provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of the structure of a convolutional decoder provided in an embodiment of the present application;

[0029] Figure 9 A flowchart of a decoding method provided in an embodiment of the present application;

[0030] Figure 10 A schematic diagram of the structure of a first subsequence and a second subsequence of a coding sequence provided in an embodiment of the present application;

[0031] Figure 11 A schematic diagram of decoding time provided in an embodiment of the present application;

[0032] Figure 12A schematic diagram of a multi-round decoding method provided in an embodiment of the present application;

[0033] Figure 13 A schematic structural diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] First, some concepts involved in this application are described.

[0035] The terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0036] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0038] A convolutional code is a code sequence that is generated by convolving the input sequence to be encoded with the system impulse response. Convolutional codes are typically represented by (n, k, m), where n represents the length of the code sequence output by the convolutional encoder at each encoding step, k represents the length of the code sequence input to the convolutional encoder at each encoding step, and m represents the code memory size, which is equal to the number of registers in the convolutional encoder plus one.

[0039] The number of registers in a convolutional encoder is also called the memory depth. If a bit stored in a register is considered the register's state, since each bit can take on two values: 0 or 1, when the memory depth is K, there are a total of 2^K possible states. Each time a bit of the sequence to be encoded is input to the convolutional encoder, the register in the convolutional encoder transitions from its old state to its new state. This process is called a state transition. The convolutional encoder then outputs a two-bit encoding sequence as the result of the convolutional encoding. Since each input sequence to be encoded can be either 0 or 1, triggering two state transitions in the register's state, there are a total of 2*(2^K) possible state transitions. Since the encoding sequence length is n, there are a total of 2^n possible encoding sequences. The encoding sequence output by the convolutional encoder during a single encoding pass depends not only on the current encoding sequence, but also on the previous register state, and ultimately on all previous encoding sequences and the register's initial state. Therefore, the convolutional encoder has memory.

[0040] For example, Figure 1 It is a (2, 1, 4) convolutional encoder structure, where D1, D2, and D3 are binary registers, and each register is used to store a binary bit. Represents a binary adder (performing addition or XOR operations). For every one-bit sequence to be encoded inputted into the convolutional encoder's input port IN, the output ports OUT1 and OUT2 will each output a one-bit encoding sequence, i.e., the entire convolutional encoder will output a two-bit encoding sequence as the convolutional encoding result. Therefore, the encoding efficiency of the convolutional encoder is the number of input bits / the number of output bits = 1 / 2. In addition, every one-bit sequence to be encoded inputted triggers the sequence stored in the register to shift right to the next register, i.e., triggering the data in register D2 to shift into register D3, and the data in register D1 to shift into register D2, with register D1 storing the newly input one-bit sequence to be encoded. This process is called state transition. If the bits stored in these three registers are used as the states of the registers in the convolutional encoder, then K = 3, so there are a total of 8 states, for example, 000 to 111 in binary. Furthermore, there are 16 possible state transitions. For example, if the register state in the convolutional encoder is 000, an input of the to-be-encoded sequence 0 triggers a state transition from 000 to 000, while an input of the to-be-encoded sequence 1 triggers a state transition from 000 to 100. Furthermore, since the encoding sequence length n = 2, a total of four encoding sequences are output, for example, 00 to 11 in binary. Therefore, the encoding sequences for state transitions may overlap, meaning that the encoding sequences for multiple state transitions are the same.

[0041] Before the convolutional encoder begins encoding, the registers in the convolutional encoder need to be initialized to a preset state to restore to a certain state. Furthermore, after the convolutional encoder completes encoding, the registers in the convolutional encoder also need to be set to a preset state to restore to a certain state. In order for the convolutional decoder to correctly decode, the convolutional decoder needs to know the number (memory depth) and preset states of the registers in the convolutional encoder. Given a known convolutional encoder structure, the convolutional decoder can determine the encoding sequence output by the convolutional decoder by observing the state transitions of the registers in the convolutional encoder. However, the encoding sequence cannot be used to infer the exact state transitions.

[0042] For example, before inputting a sequence of valid data to be encoded into the convolutional encoder to generate a coding sequence of valid data, a redundant sequence to be encoded (for example, all 0s) can be input first to generate a redundant coding sequence. After inputting a sequence of valid data to be encoded into the convolutional encoder, a redundant sequence to be encoded (for example, all 0s) can also be input to generate a redundant coding sequence. The length of the redundant sequence to be encoded is equal to the memory length, that is, the number of registers in the convolutional encoder. For example, for Figure 1 For the convolutional encoder shown, the length of the redundant sequence to be encoded is 3. Given the number and preset states of the registers in the convolutional encoder, the convolutional decoder can directly decode the valid data sequence after receiving the encoded sequence by removing the redundant sequence at the head. However, for the convolutional encoder, these redundant sequences to be encoded increase the encoding overhead.

[0043] In order to solve the problem of increased coding overhead, a tail-biting convolutional code is proposed. That is, before inputting the valid data sequence to be encoded into the convolutional encoder, a sequence at the end of the valid data sequence to be encoded with a length equal to the memory length is first input into the convolutional encoder as a redundant sequence to be encoded. In this way, at the end of encoding, the state of the register in the convolutional encoder is the same as the initial state. For example, Figure 2 As shown in the figure, before the sequence C1-C8 of valid data to be encoded is input to the convolutional encoder, the sequence C6-C8 is first input to the convolutional encoder, so that the initial state of register D3 is C6, the initial state of register D2 is C7, and the initial state of register D1 is C8. Although tail-biting convolutional codes save encoding overhead, because the convolutional decoder does not know the initial states of the registers in the convolutional encoder, it will significantly increase the decoding overhead of the convolutional decoder.

[0044] A commonly used convolutional decoder for tail-biting convolutional codes is the Viterbi decoder. The Viterbi decoder uses the circular Viterbi algorithm (CVA) to decode the code. The following explains how it works:

[0045] For example, Figure 1 The (2, 1, 4) convolutional encoder shown encodes each bit of the sequence to be encoded once, resulting in a two-bit encoded sequence. This also triggers a state transition of the register in the convolutional encoder from the old state to the new state. Therefore, the Viterbi decoder decodes each two-bit encoded sequence once to obtain a one-bit decoded sequence, meaning the length of the decoded sequence is half the length of the encoded sequence. Ideally, the decoded sequence for that one bit is identical to the one-bit sequence to be encoded, indicating a correct decoding.

[0046] As mentioned above, when the memory depth of the convolutional encoder is K, the registers in the convolutional encoder have a total of 2^K states and a total of 2*(2^K) possible state transitions. For example, Figure 3 As shown in A, Figure 1 Taking the (2, 1, 4) convolutional encoder shown as an example, the register has a total of 8 states, for example, represented as 000 to 111 in binary. Since the sequence to be encoded can be either 0 or 1 at a time, there are a total of 16 state transitions from the old state to the new state. Assuming that the old state of the register in the convolutional encoder is 010, inputting the sequence to be encoded 0 into the convolutional encoder will trigger the register to transition from the old state 010 to the new state 001 (i.e., state transition a). Conversely, the sequence to be encoded 0 is the decoding sequence of state transition a. Inputting the sequence to be encoded 1 into the convolutional encoder will trigger the register to transition from the old state 010 to the new state 101 (i.e., state transition c). Conversely, the sequence to be encoded 1 is the decoding sequence of state transition c. Similarly, assuming the old state of the register in the convolutional encoder is 011, inputting the sequence to be encoded 0 into the convolutional encoder will trigger the register in the convolutional encoder to transition from the old state 011 to the new state 001 (i.e., state transition b). Conversely, the sequence to be encoded 0 is the decoding sequence of state transition b. Inputting the sequence to be encoded 1 into the convolutional encoder will trigger the register to transition from the old state 011 to the new state 101 (i.e., state transition d). Conversely, the sequence to be encoded 1 is the decoding sequence of state transition d. In summary, decoding according to each state transition will produce the corresponding decoding sequence.

[0047] Because the Viterbi decoder doesn't know the state of the convolutional encoder's registers, to assess the probability of various state transitions, it calculates scores for each state transition based on the actual received code sequence and the code sequence output by the convolutional encoder under various state transitions (e.g., 16 state transitions). A state transition with a higher score is more likely to be the correct state transition. The state transition score is calculated as follows: if the code sequence actually received by the Viterbi decoder and the code sequence output by the convolutional encoder under a particular state transition have one bit in common, the state transition score is 1; if they have two bits in common, the state transition score is 2; and if there are no bits in common, the state transition score is 0.

[0048] For example, Figure 3 As shown in Figure A, assuming the Viterbi decoder actually receives a two-bit code sequence of 10, the convolutional encoder state transition a outputs a code sequence of 01, which is completely different from the received code sequence 10. Therefore, the score corresponding to state transition a is 0. The convolutional encoder state transition b outputs a code sequence of 10, which is exactly the same as the received code sequence 10. Therefore, the score corresponding to state transition b is 2. Therefore, state transition b is more likely than state transition a. Similarly, assuming the Viterbi decoder actually receives a two-bit code sequence of 10, the convolutional encoder state transition c outputs a code sequence of 11, which has one bit in common with the received code sequence 10. Therefore, the score corresponding to state transition c is 1. The convolutional encoder state transition d outputs a code sequence of 00, which has one bit in common with the received code sequence 10. Therefore, the score corresponding to state transition d is 1. The probabilities of state transition c and state transition d are equal, that is, the new state 101 may be triggered by the convolution encoder inputting the sequence to be encoded 0 and transitioning from the old state 010, or it may be triggered by the convolution encoder inputting the sequence to be encoded 1 and transitioning from the old state 011.

[0049] In order to retain the state transition with the highest probability, the state transition with the highest score can be retained first, and the remaining state transitions can be retained according to the mutual exclusion principle, so that each new state corresponds to the old state through a state transition. For example, Figure 3 As shown in Figure B, among state transitions a, b, c, and d, state transition b has the highest score, so it is retained. State transition b can also be called the survivor path, and the to-be-encoded sequence 0 that triggers state transition b is the decoding sequence. State transitions c and d have the same score, but since state transitions b and d are mutually exclusive, state transition c is retained. State transition c can also be called the survivor path, and the to-be-encoded sequence 1 that triggers state transition c is the decoding sequence. Based on the same principle, the other state transitions can be retained.

[0050] To facilitate inferring the old state corresponding to the state transition with the highest probability (i.e., the highest score) from the new state, we define a state transition vector of dimension M*1, where M = 2^K. Each row of the state transition vector indexes a new state of a register in the convolutional encoder, and each row stores the index of the old state corresponding to the state transition with the highest score for that new state.

[0051] For example, Figure 3 As shown in Figure C, the indices in the first to eighth rows of the state transition vector represent register states 000 to 111, respectively. For state 001, to facilitate inferring the old state 011 corresponding to state transition b from the new state 001, the data stored at index 001 in the state transition vector is the old state 011 corresponding to state transition b. For state 101, to facilitate inferring the old state 010 corresponding to state transition c from the new state 101, the data stored at index 101 in the state transition vector is the old state 010 corresponding to state transition c. Based on the same principle, the indices of the corresponding old states are stored in other locations in the state transition vector. This way, the old state corresponding to the state transition with the highest probability (i.e., the highest score) can be inferred from the index of any row of the state transition vector (i.e., the new state).

[0052] Furthermore, when the Viterbi decoder receives a new coding sequence, it indicates that a new state transition has occurred, and the original new state also becomes the old state. Similarly, multiple state transitions connected end to end will form a state transition path, with a total of 2^K state transition paths. Since decoding according to a state transition can obtain a decoding sequence (i.e., the sequence to be encoded that triggers the state transition), decoding according to a state transition path can obtain a set of decoding sequences. For example, Figure 4 As shown in A, after two rounds of state transitions in the direction of the arrows, state 000->state 100->state 010 is the first state transition path, state 001->state 000->state 000 is the second state transition path, and so on.

[0053] In order to store the state transition path so that the earlier old state can be continuously forward-pushed forward through the new state, a state transition matrix with a dimension of M*N is defined based on the state transition vector, where N represents the backtracking length of the state transition, that is, data of up to N consecutive state transitions can be stored. Each column of the state transition matrix is a state transition vector as described above. Similar to the state transition vector, the index of each row of the state transition matrix is a new state of the register in the convolution encoder, and the data stored in each row is the index of the old state of the maximum score state transition corresponding to the new state. For example, Figure 4Figure B shows the state transfer matrix after two rounds of state transfers. It should be noted that since the backtracking length N is finite, when the state transfer matrix is full and the Viterbi decoder receives a new coded sequence, the data in the original first column of the state transfer matrix is removed from the matrix. The data in the remaining columns is shifted left one column, leaving the Nth column free to store the new data.

[0054] In addition, an M*1 dimensional cumulative score vector is also defined to store the sum of the scores of the state transitions included in each state transition path, that is, each state transition path corresponds to a cumulative score, and the cumulative score of the state transition path essentially represents the probability of obtaining a set of decoding sequences by decoding along the state transition path. The index of each row of the cumulative score vector is a state of a register in the convolution encoder, that is, the state of the latest end point of a state transition path. In the initial state, the data in the state transition matrix are all invalid values, and the data in the cumulative score vector are all 0. For example, Figure 4 Figure C shows the change in the cumulative score vector after two rounds of state transitions. S1-S8 represent the scores of each state transition in the first round of state transitions, while s1-s8 represent the scores of each state transition in the second round. The score of the first state transition path (state 000 -> state 100 -> state 010) is S5 + s3, the score of the second state transition path (state 001 -> state 000 -> state 000) is S1 + s1, and so on. Since each state transition path corresponds to a set of decoding sequences, when decoding is complete, the state transition path with the highest cumulative score (i.e., the highest probability) is the decoding path, and the set of decoding sequences corresponding to this state transition path is the decoding result.

[0055] When the Viterbi decoder decodes normally, the received coded sequence ( Figure 5 Multiple copies of the sequence (shown in A) are connected end to end to form a long sequence ( Figure 5 B in the figure), and then the Viterbi decoder decodes this long sequence ( Figure 5 CG in the figure), which is equivalent to performing multiple rounds of decoding on the received coded sequence. Figure 5 As shown in CE, the Viterbi decoder decodes every two-bit coded sequence once to obtain a one-bit decoded sequence corresponding to each state transition path. Each row in the decoded sequence refers to the decoded sequence corresponding to a state transition path. And as the decoding process progresses, the data in the state transition matrix increases column by column. Figure 5As shown in F and G, at the end of each decoding round, the state transition path (the black part in the state transition matrix) with the largest cumulative score (the black part in the cumulative score vector, i.e., the highest probability) is selected as the decoding path, and the decoding sequence corresponding to the state transition path (the black part in the decoding sequence) is the decoding result. And when the decoding path finally converges after multiple rounds of decoding, that is, the state transition path with the highest probability is the same, for example Figure 5 When the decoding paths obtained from the two most recent decoding rounds shown in F and G are the same (ie, the index with the largest cumulative score in the cumulative score vector is the same), the decoding is completed and the decoding result is output.

[0056] It's important to note that during the first decoding round, the data in the cumulative score vector is initialized to 0. The cumulative score vector from the previous decoding round is not cleared during subsequent decoding rounds. In other words, the cumulative score vector from the previous decoding round serves as the initial value for the cumulative score vector in the next decoding round. Therefore, for multiple decoding rounds, the decoded code sequence remains unchanged; only the initial value of the cumulative score vector changes.

[0057] As can be seen from this, when signal quality is poor, CVA decoding will repeat many rounds of decoding to achieve final convergence of the decoding path. The decoding time is t = NT, where N is the number of decoding rounds and T is the time required to complete one round of decoding of the complete code sequence. Furthermore, the convergence criterion for CVA decoding is unstable. If the memory depth is small, even if the decoding paths of two rounds are consistent, this may be a coincidence rather than true convergence. For example, in the aforementioned case of a memory depth of 3, there are only eight possible register states, and even if a decoding error occurs, there is a 1 / 8 probability of convergence.

[0058] The convolutional decoder, decoding method, and electronic device provided by the embodiments of the present application decode P subsequences of a coded sequence during the first decoding round. Because the sum of the lengths of these P subsequences is less than the length of the entire coded sequence, the first decoding round takes less time to complete. Starting with the second decoding round, P Viterbi decoders, each starting from P different subsequences, perform cyclic decoding on the coded sequence in parallel, reducing the decoding time per round to one-P times the original time. This reduces the time overhead of convolutional code decoding. P is a positive integer greater than 1.

[0059] An embodiment of the present application provides an electronic device, which is an electronic device with wireless communication function. The electronic device can be mobile or fixed. The electronic device can be deployed on land (for example, indoors or outdoors, handheld or vehicle-mounted, etc.), on water (for example, ships, etc.), or in the air (for example, airplanes, balloons, and satellites, etc.). The electronic device can be called user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent or terminal device, etc. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, smart bracelet, smart screen, smart watch, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. The embodiments of the present application do not limit the specific type and structure of the electronic device. A possible structure of the electronic device is described below.

[0060] Taking mobile phones as an example, Figure 6 FIG2 shows a possible structure of an electronic device 101. The electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, a sensor module 280, a button 290, a motor 291, an indicator 292, a camera 293, a display 294, and a subscriber identification module (SIM) card interface 295. Optionally, in some embodiments, an audio digital signal processor (ADSP) 243 is also included.

[0061] It should be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0062] The processor 210 may include one or more processing units, for example: the processor 210 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, and a neural network processing unit (NPU). Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 210 may be an application processor AP. Alternatively, the processor 210 may be integrated into a system on chip (SoC). Alternatively, the processor 210 may be integrated into an integrated circuit (IC) chip. The processor 210 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0063] The processor 210 implements the decoding method involved in this application by executing the computer program stored in the internal memory 221.

[0064] Processor 210 may also include a memory for storing computer instructions and data. In some embodiments, the memory in processor 210 is a cache memory. This memory can store computer instructions or data that have just been used or are being recycled by processor 210. If processor 210 needs to use the computer instructions or data again, it can directly access the memory. This avoids repeated accesses, reduces processor 210 latency, and thus improves system efficiency.

[0065] In some embodiments, the processor 210 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface.

[0066] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can be used to process audio signals and sensor data. When the processor is in a dormant state, the ADSP 243 can still keep working, thereby reducing the power consumption of the electronic device.

[0067] It is understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may also adopt a different interface connection method from the above embodiments, or a combination of multiple interface connection methods.

[0068] The external memory interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 101. The external memory card communicates with the processor 210 via the external memory interface 220 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0069] The internal memory 221 can be used to store computer executable program code, which includes computer instructions. The processor 210 executes various functional applications and data processing of the electronic device 101 by running the computer instructions stored in the internal memory 221. In addition, the internal memory 221 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0070] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0071] The electronic device 101 can implement audio functions such as music playback and recording through the audio module 270 , the speaker 270A, the receiver 270B, the microphone 270C, the headphone jack 270D, and the application processor.

[0072] The audio module 270 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. In some embodiments, the audio module 270 can be set in the processor 210, or some functional modules of the audio module 270 can be set in the processor 210. The speaker 270A, also known as the "speaker", is used to convert audio electrical signals into sound signals. The receiver 270B, also known as the "earpiece", is used to convert audio electrical signals into sound signals. The microphone 270C, also known as the "microphone" or "microphone", is used to convert sound signals into electrical signals. The electronic device 101 can be provided with at least one microphone 270C. The headphone jack 270D is used to connect wired headphones. The headphone jack 270D can be a USB interface 230, or it can be a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0073] The buttons 290 include a power button, a volume button, and the like. The buttons 290 may be mechanical buttons. They may also be touch buttons. The electronic device 101 may receive button inputs and generate key signal inputs related to the user settings and function controls of the electronic device 101. The motor 291 may generate vibration prompts. The motor 291 may be used for incoming call vibration prompts or for touch vibration feedback. The indicator 292 may be an indicator light that may be used to indicate the charging status, power level changes, messages, missed calls, notifications, and the like. The SIM card interface 295 is used to connect a SIM card. The SIM card may be connected to or disconnected from the electronic device 101 by inserting or removing the SIM card interface 295. The electronic device 101 may support one or N SIM card interfaces, where N is a positive integer greater than one. The SIM card interface 295 may support nano SIM cards, micro SIM cards, SIM cards, and the like. In some embodiments, the electronic device 101 uses an embedded SIM (eSIM) card. The eSIM card can be embedded in the electronic device 101 and cannot be separated from the electronic device 101.

[0074] The electronic device 101 can implement a camera function using an ISP, a camera 293, a video codec, a GPU, a display 294, and an application processor. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be provided within the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, the electronic device 101 can include one or N cameras 293, where N is a positive integer greater than one.

[0075] Electronic device 101 can implement display functions through a GPU, display screen 294, and an application processor. A GPU is a microprocessor for image processing that connects display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 210 may include one or more GPUs that execute computer instructions to generate or modify display information.

[0076] The sensor module 280 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, an angle sensor, etc. When the display screen 294 is a foldable screen, the angle sensor can detect the folding angle of the display screen 294, and the folding angle range is 0-180 degrees.

[0077] The battery 241 may include one or more batteries to power the load.

[0078] The power management module 240 is configured to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock or another electronic device 101 with reverse wireless charging functionality. The power management module 240 can receive wireless charging input via the electronic device's wireless charging coil 242. Alternatively, the charger can be a wired charger, for example, via the USB port 230. The power management module 240 is also referred to as a charging chip.

[0079] The power management module 240 can not only charge the battery 241 but also power the electronic device. The power management module 240 receives input from the battery 241 and provides power to the processor 210, the internal memory 221, the external memory interface 220, the display 294, the camera 293, and the wireless communication module 260. The power management module 240 can also be used to monitor parameters such as the capacity, voltage, battery cycle count, and battery health status (leakage, impedance) of the battery 241. In other embodiments, the power management module 240 can also be provided in the processor 210.

[0080] The display screen 294 is used to display images, videos, etc. The display screen 294 includes a display panel. In some embodiments, the electronic device 101 may include one or more display screens 294 .

[0081] The wireless communication function of the electronic device 101 can be implemented through the antenna 1, the antenna 2, the mobile communication module 250, the wireless communication module 260, the modulation and demodulation processor, etc.

[0082] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 101 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0083] The mobile communication module 250 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 101. The wireless communication module 260 can provide solutions for wireless communications including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., applied to the electronic device 101. In some embodiments, the antenna 1 of the electronic device 101 is coupled to the mobile communication module 250, and the antenna 2 is coupled to the wireless communication module 260, so that the electronic device 101 can communicate with the network and other devices through wireless communication technology.

[0084] like Figure 7 As shown, the mobile communication module 250 may include a baseband chip 31 , a radio frequency integrated circuit (RFIC) 32 and a radio frequency front-end module (FEM) 33 .

[0085] The baseband chip 31 is used to convert data from the processor 210 into baseband signals, including performing modulation and demodulation, digital filtering, and equalization on the baseband signals. The RFIC 32 integrates a transmitter and a receiver. The transmitter is used to convert the baseband signals from the baseband chip 31 into RF signals and transmit them through the RF front-end module 33 and at least one of the multiple antennas 34. The receiver is used to receive RF signals through at least one antenna and the RF front-end module 33, convert them into baseband signals, and send them to the baseband chip 31. The receiver of the RFIC 32 includes a convolutional decoder (e.g., a Viterbi decoder) for decoding the received coded sequence. The baseband chip 31 converts the baseband signals into data and sends them to the processor 210. It should be noted that the baseband chip 31 and RFIC 32 can also be integrated with the processor 210 in an SoC.

[0086] like Figure 8 As shown, the convolution decoder includes an input buffer 801, P (P is a positive integer greater than 1) Viterbi decoders (e.g., Viterbi decoder 8021-Viterbi decoder 8023), P comparators (e.g., comparator 8031-comparator 8033), P first registers (e.g., first register 8041-first register 8043), P second registers (e.g., second register 8051-second register 8053), P output buffers (e.g., output buffer 8061-output buffer 8063), and a timer 807. Exemplarily, Figure 8 In the following, we take P equal to 3 as an example to explain. The following describes the functions of each component in the convolutional decoder in combination with the decoding method performed by the convolutional decoder. Figure 9 As shown, the decoding method includes:

[0087] S101. For a first round of decoding, at least one of the P Viterbi decoders decodes the P second subsequences in the coded sequence, obtains a decoding sequence corresponding to each state transition path of the P second subsequences, and updates the cumulative score vectors of the P second subsequences.

[0088] The input buffer 801 can be used to cache the code sequence received by the receiver. By cyclically accessing the code sequence, it is equivalent to connecting multiple copies of the code sequence end to end to form a Figure 5 A long sequence is shown in Figure A.

[0089] For example, Figure 10As shown, the entire coding sequence can be divided into P first subsequences, such as first subsequence 1, first subsequence 2, and first subsequence 3. The lengths of the P first subsequences can be the same or different. The tail sequence of each first subsequence is a second subsequence, such as second subsequence 1, second subsequence 2, and second subsequence 3. That is, each first subsequence includes a second subsequence, the second subsequence has the same end position as the first subsequence, and the length of the second subsequence is less than the length of the first subsequence. The tail sequence of the P first sequences has a total of P second subsequences, and the lengths of these P second subsequences can be the same or different. Each first subsequence and each second subsequence are continuous sequences.

[0090] This application does not limit the correspondence between P Viterbi decoders and P subsequences (first subsequences or second subsequences), that is, one Viterbi decoder can decode multiple subsequences (for example, P second subsequences) or one subsequence. Figure 11 As shown, for the first round of decoding (i.e., decoding round number 1), since the sum of the lengths of the P second subsequences is less than the length of the entire encoded sequence, if a Viterbi decoder decodes the P second subsequences serially, the time to complete the first round of decoding is shorter than that of the prior art. Furthermore, the P Viterbi decoders can decode the P second subsequences in parallel, respectively, to further reduce the time of the first round of decoding. For example, Figure 8 The Viterbi decoder 8021 shown can decode the second subsequence 1. Figure 8 The Viterbi decoder 8022 shown can decode the second subsequence 2. Figure 8 The Viterbi decoder 8023 shown can decode the second subsequence 3. When the lengths of the P first subsequences are the same, and / or when the lengths of the P second subsequences are the same, for the same decoding round, each Viterbi decoder takes the same time to decode the subsequence, and the decoding efficiency of the entire convolutional decoder is the highest.

[0091] It should be noted that the present application decodes each subsequence to obtain a decoded sequence corresponding to each state transition path of each subsequence. Referring to the above description, the entire coding sequence can be decoded to obtain a decoded sequence corresponding to each state transition path. The decoded sequence obtained by the Viterbi decoder from decoding each subsequence (e.g., the first subsequence or the second subsequence) can be cached in the output buffer corresponding to the Viterbi decoder. For example, Figure 8 The decoded sequence obtained by the Viterbi decoder 8021 shown in FIG. 1 can be cached in Figure 8 The output buffer 8061 is shown. Figure 8 The decoded sequence obtained by the Viterbi decoder 8022 shown in FIG. 8 decodes the subsequence can be cached in Figure 8 In the output buffer 8062 shown. Figure 8 The decoded sequence obtained by the Viterbi decoder 8023 shown in FIG. 8 decodes the subsequence can be cached in Figure 8 The output buffer 8063 is shown in FIG. The difference between the present application and the prior art lies in the different decoding start position, the different decoding end position, the different number of state transition paths obtained, and the different initial value of the cumulative score vector.

[0092] In the prior art, each decoding round starts from the start position of the entire coding sequence and ends at the end position of the entire coding sequence. In the present application, each decoding round starts from the start position of each subsequence and ends at the end position of the subsequence.

[0093] Assuming the number of stored states is M, in the prior art, decoding the entire coded sequence can obtain M state transition paths. In this application, decoding each subsequence can obtain M state transition paths, so decoding P subsequences will result in a total of P*M state transition paths.

[0094] In the prior art, the cumulative score vector represents the cumulative score of each state transition path obtained by decoding the entire coding sequence. In the present application, the cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence; the cumulative score vector of the second subsequence represents the cumulative score of each state transition path obtained by decoding the second subsequence. The cumulative score of each state transition path essentially represents the probability of obtaining a set of decoding sequences by decoding along the state transition path. In the present application, the cumulative score vector Sab represents the cumulative score vector of the bth subsequence (first subsequence or second subsequence) obtained by the ath round of decoding. For example, Figure 12 As shown, before the first round of decoding, the initial value of the cumulative score vector of each second subsequence is all 0. The first round of decoding decodes the second subsequence 1 to obtain the cumulative score vector S11 of the second subsequence 1; decodes the second subsequence 2 to obtain the cumulative score vector S12 of the second subsequence 2; and decodes the second subsequence 3 to obtain the cumulative score vector S13 of the second subsequence 3. For an example of how to update the cumulative score vector, refer to Figure 4 The relevant description of C will not be repeated here.

[0095] Each first register is used to store the cumulative score vector of a subsequence (first subsequence or second subsequence) in the current round of decoding, and each second register is used to store the cumulative score vector of a subsequence (first subsequence or second subsequence) in the previous round of decoding. Therefore, the first register and the second register are paired, and are used to store the cumulative score vectors of two subsequences with the same end position obtained in the last two rounds of decoding (this round and the previous round). In a new round of decoding, the cumulative score vector in the first register will be moved to the paired second register, so that the first register can be free to store the cumulative score vector obtained in this round of decoding. In the first round of decoding, each first register stores a cumulative score vector of the second subsequence. The storage overhead of the cumulative score vector can be minimized. For example, in the first round of decoding, Figure 8 The first register 8041 shown is used to store the cumulative score vector S11 of the second subsequence 1, Figure 8 The first register 8042 is used to store the cumulative score vector S12 of the second subsequence 2. Figure 8 The first register 8043 shown is used to store the cumulative score vector S13 of the second subsequence 3.

[0096] S102. Starting from the second round of decoding, the pth Viterbi decoder starts from the starting position of the pth first subsequence and cyclically decodes the encoded sequence. In each round of decoding, a decoding sequence corresponding to each state transition path of the P first subsequences is obtained, and the cumulative score vector of the P first subsequences is updated, where p is an integer less than or equal to P.

[0097] Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence in the first round of decoding. Among them, the initial value of the cumulative score vector of the first first subsequence in the second round of decoding (first subsequence 1) is the cumulative score vector of the last second subsequence in the first round of decoding (second subsequence 3). For example, Figure 12 As shown, for the second round of decoding, the initial value of the cumulative score vector of the first subsequence 1 is the cumulative score vector S13 of the second subsequence 3 of the first round of decoding.

[0098] Exemplarily, starting from the second round of decoding, the first Viterbi decoder ( Figure 8 The Viterbi decoder 8021 shown in FIG. 8 starts from the starting position of the first subsequence (the first subsequence 1) and performs cyclic decoding on the coded sequence. The second Viterbi decoder ( Figure 8 The Viterbi decoder 8022 shown in FIG. 8 starts from the starting position of the second first subsequence (first subsequence 2) and performs cyclic decoding on the coded sequence. The third Viterbi decoder ( Figure 8The Viterbi decoder 8023 shown in FIG. 2 , starting from the start position of the third first subsequence (first subsequence 3), performs cyclic decoding on the coded sequence. Each Viterbi decoder performs cyclic decoding on the coded sequence, which is compatible with cyclic decoding in the prior art. This eliminates the need for frequent data transfer between Viterbi decoders, reducing implementation complexity.

[0099] Starting from the second round of decoding, one round of decoding is completed by P Viterbi decoders decoding different first subsequences respectively, and the P first subsequences can just be spliced into a complete coding sequence. Figure 11 As shown, starting from the second round of decoding (i.e., decoding round numbers 2, 3, 4, 5...), the time length of each round of decoding is equal to the time length of a Viterbi decoder decoding a first subsequence. Exemplarily, when P is 3, it is equivalent to one third of the decoding time length of the entire coding sequence in the prior art.

[0100] Circular decoding of a code sequence means decoding the code sequence in the order of the first subsequences, with the initial value of the cumulative score vector of the next first subsequence being equal to the cumulative score vector of the previous first subsequence. After decoding the last first subsequence of the code sequence, decoding restarts from the first first subsequence of the code sequence.

[0101] Figure 8 The Viterbi decoder 8021 shown decodes the first subsequence 1 to obtain a decoded sequence corresponding to each state transition path of the second subsequence 1, and updates the cumulative score vector of the first subsequence 1 to S21. The initial value of the cumulative score vector of the first subsequence 2 is the cumulative score vector S11 of the second subsequence 1 from the first round of decoding. Figure 8 The Viterbi decoder 8022 shown decodes the first subsequence 2 to obtain a decoded sequence corresponding to each state transition path of the second subsequence 2, and updates the cumulative score vector of the first subsequence 2 to S22. The initial value of the cumulative score vector of the first subsequence 3 is the cumulative score vector S12 of the second subsequence 2 from the first round of decoding. Figure 8 The Viterbi decoder 8023 shown decodes the first subsequence 3 to obtain a decoding sequence corresponding to each state transition path of the second subsequence 3, and updates the cumulative score vector of the first subsequence 3 to S23.

[0102] During the second round of decoding, the accumulated score vectors in the first register are moved to the paired second register, leaving the first register free to store the accumulated score vectors obtained from the second round of decoding. Starting from the second round of decoding, each first register stores a accumulated score vector of the first subsequence.

[0103] For example, in the second round of decoding, Figure 8The first register 8041 shown is used to store the cumulative score vector S21 of the first subsequence 1 of the second round of decoding. Figure 8 The second register 8051 is shown to store the cumulative score vector S11 of the second subsequence 1 of the first round of decoding. Figure 8 The first register 8042 shown is used to store the cumulative score vector S22 of the first subsequence 2 of the second round of decoding. Figure 8 The second register 8052 is shown to store the cumulative score vector S12 of the second subsequence 2 of the first round of decoding. Figure 8 The first register 8043 shown is used to store the cumulative score vector S23 of the first subsequence 3 of the second round of decoding. Figure 8 The second register 8053 is shown to store the cumulative score vector S13 of the second subsequence 3 of the first round of decoding.

[0104] For example, in the third round of decoding, Figure 8 The first register 8041 shown is used to store the cumulative score vector S31 of the first subsequence 1 of the third round of decoding. Figure 8 The second register 8051 is shown to store the cumulative score vector S21 of the first subsequence 1 of the second round of decoding. Figure 8 The first register 8042 shown is used to store the cumulative score vector S32 of the first subsequence 2 of the third round of decoding. Figure 8 The second register 8052 is shown to store the cumulative score vector S22 of the first subsequence 2 of the second round of decoding. Figure 8 The first register 8043 shown is used to store the cumulative score vector S33 of the first subsequence 3 of the third round of decoding. Figure 8 The second register 8053 is shown to store the cumulative score vector S23 of the first subsequence 3 of the second round of decoding.

[0105] Similarly, in the fourth round of decoding, we can obtain the cumulative score vector S41 of the first subsequence 1 decoded in the fourth round, the cumulative score vector S42 of the first subsequence 2 decoded in the fourth round, and the cumulative score vector S43 of the first subsequence 3 decoded in the fourth round. In the fifth round of decoding, we can obtain the cumulative score vector S51 of the first subsequence 1 decoded in the fifth round, the cumulative score vector S52 of the first subsequence 2 decoded in the fifth round, and the cumulative score vector S53 of the first subsequence 3 decoded in the fifth round. These details will not be repeated here.

[0106] Starting from the second round of decoding, the judgment process of S103 is executed once after each round of decoding is completed.

[0107] S103, P comparators, starting from the second round of decoding, after each round of decoding, compare the cumulative score vectors of the two subsequences with the same end position obtained from the two most recent rounds of decoding. If the maximum probability state transition paths of the two subsequences with the same end position are the same, then output the decoding sequence corresponding to the maximum probability state transition path (i.e., end decoding); otherwise, continue to the next round of decoding.

[0108] The two subsequences with the same end position may be the first subsequence and the second subsequence with the same end position in the two most recent decoding rounds (for example, in the second decoding round, the first subsequence 1 in the second decoding round and the second subsequence 1 in the first decoding round), or may be the two first subsequences with the same end position in the two most recent decoding rounds (for example, in the third decoding round, the first subsequence 1 in the second decoding round and the first subsequence 1 in the third decoding round).

[0109] For example, Figure 12 As shown, in the second round of decoding, Figure 8 The illustrated comparator 8031 may compare the cumulative score vector S21 of the first subsequence 1 of the second decoding round with the cumulative score vector S11 of the second subsequence 1 of the first decoding round. Figure 8 The illustrated comparator 8032 may compare the cumulative score vector S22 of the first subsequence 2 of the second decoding round with the cumulative score vector S12 of the second subsequence 2 of the first decoding round. Figure 8 The comparator 8033 shown can compare the cumulative score vector S23 of the first subsequence 3 of the second round of decoding with the cumulative score vector S13 of the second subsequence 3 of the first round of decoding. If the comparator 8031 determines that the maximum probability state transition path of the first subsequence 1 of the second round of decoding is the same as the maximum probability state transition path of the second subsequence 1 of the first round of decoding, and if the comparator 8032 determines that the maximum probability state transition path of the first subsequence 2 of the second round of decoding is the same as the maximum probability state transition path of the second subsequence 2 of the first round of decoding, and if the comparator 8033 determines that the first subsequence 3 of the second round of decoding is the same as the maximum probability state transition path of the second subsequence 3 of the first round of decoding: then the decoding has converged, and the comparator 8031 will Figure 8 The decoded sequence corresponding to the maximum probability state transition path of the first subsequence 1 is output by the output buffer 8061 shown in FIG. Figure 8 The decoded sequence corresponding to the maximum probability state transition path of the first subsequence 2 is output by the output buffer 8062 shown in FIG. Figure 8 The decoding sequence corresponding to the maximum probability state transition path of the first subsequence 3 cached in the output buffer 8063 is output, and the three decoding sequences are combined into the final decoding result, and the decoding is completed. Otherwise, the next round of decoding is continued.

[0110] For example, Figure 12 As shown, in the third round of decoding, Figure 8 The illustrated comparator 8032 can compare the cumulative score vector S32 of the first subsequence 2 of the third decoding round with the cumulative score vector S22 of the first subsequence 2 of the second decoding round. Figure 8 The illustrated comparator 8033 may compare the cumulative score vector S33 of the first subsequence 3 of the third round of decoding with the cumulative score vector S33 of the first subsequence 3 of the second round of decoding. Figure 8 The comparator 8031 shown can compare the cumulative score vector S31 of the first subsequence 1 of the third round of decoding with the cumulative score vector S31 of the first subsequence 1 of the second round of decoding. If the comparator 8031 determines that the maximum probability state transition path of the first subsequence 1 of the third round of decoding is the same as that of the first subsequence 1 of the second round of decoding, and if the comparator 8032 determines that the maximum probability state transition path of the first subsequence 2 of the third round of decoding is the same as that of the first subsequence 2 of the second round of decoding, and if the comparator 8033 determines that the maximum probability state transition path of the first subsequence 3 of the third round of decoding is the same as that of the first subsequence 3 of the second round of decoding, then the decoding has converged, and the comparator 8031 will Figure 8 The decoded sequence corresponding to the maximum probability state transition path of the first subsequence 1 is output by the output buffer 8061 shown in FIG. Figure 8 The decoded sequence corresponding to the maximum probability state transition path of the first subsequence 2 is output by the output buffer 8062 shown in FIG. Figure 8 The decoded sequence corresponding to the maximum probability state transition path of the first subsequence 3, cached in output buffer 8063, is output. These three decoded sequences are combined into the final decoding result, and decoding ends. Otherwise, the next decoding round continues. This continues in this manner, and the comparison between the fourth and fifth decoding rounds will not be further described.

[0111] Compared with the prior art, which only determines the state transition path once at the end of each decoding round, the present application determines the state transition path at point P in each decoding round, and these points P are evenly distributed throughout the entire coding sequence, so the accuracy of determining whether the decoding has converged is higher.

[0112] Figure 8 The timer shown is used for timing. If the decoding cannot be completed within the preset time, the timer triggers the end of the decoding and uses the decoding sequence obtained in the last round of decoding as the decoding result. This can avoid excessive decoding time.

[0113] The convolution decoder, decoding method, and electronic device provided by the embodiments of the present application are such that, during the first round of decoding, the sum of the lengths of the P second subsequences is less than the length of the entire coding sequence. Therefore, decoding the P second subsequences takes less time to complete the first round of decoding. Starting from the second round of decoding, P Viterbi decoders start from P different first subsequences and perform cyclic decoding on the coding sequence in parallel, updating the cumulative score vectors of the P first subsequences in each round of decoding. P comparators compare the cumulative score vectors of the two subsequences with the same end position in the last two rounds of decoding to determine whether the decoding has converged. The time for each round of decoding is reduced to one-Pth of the original time. This reduces the time overhead of convolutional code decoding, greatly improves decoding efficiency, and shortens decoding delay when signal quality is poor. It can be applied to any scenario that decodes tail-biting convolutional codes, such as the Geostationary Earth Orbit Mobile Radio Interface 1 (GMR-1) protocol for satellite communications, the World Interoperability for Microwave Access (WiMAX) protocol for connecting Wi-Fi hotspots, and the Long Term Evolution (LTE) protocol for cellular communications.

[0114] like Figure 13 As shown, the embodiment of the present application also provides a chip system. The chip system 130 includes at least one processor 1301 and at least one interface circuit 1302. The at least one processor 1301 and the at least one interface circuit 1302 can be interconnected via a line. The processor 1301 is used to support the electronic device to implement each step in the above method embodiment, such as Figure 9 In the method shown, at least one interface circuit 1302 may be used to receive signals from other devices (eg, memory) or to send signals to other devices (eg, communication interface). The chip system may include a chip and may also include other discrete devices.

[0115] The present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the electronic device executes each step in the above method embodiment, such as executing Figure 9 The method shown.

[0116] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the electronic device executes each step in the above method embodiment, such as executing Figure 9 The method shown.

[0117] Regarding the technical effects of the chip system, computer-readable storage medium, and computer program product, refer to the technical effects of the previous method embodiments.

[0118] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0119] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0122] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0123] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0124] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0125] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A convolutional decoder, characterized in that Used to decode a coded sequence, the coded sequence is divided into P first subsequences, the tail sequences of the P first subsequences are P second subsequences, the convolutional decoder includes: P Viterbi decoders and P comparators, where P is an integer greater than 1; For the first round of decoding, at least one of the P Viterbi decoders is configured to decode the P second subsequences respectively and update cumulative score vectors of the P second subsequences, where the cumulative score vectors of the second subsequences represent cumulative scores of each state transition path obtained by decoding the second subsequence, and the cumulative scores of each state transition path represent probabilities of obtaining a set of decoded sequences by decoding along each state transition path. Before the first round of decoding, the cumulative score vectors of the P second subsequences are initially all zeros. Starting from the second round of decoding, the pth Viterbi decoder starts from the starting position of the pth first subsequence and cyclically decodes the coded sequence. The cumulative score vectors of the P first subsequences are updated in each decoding round. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence in the first round of decoding. P is an integer less than or equal to P. The P comparators are used to compare the cumulative score vectors of two subsequences with the same end position obtained from the two most recent decoding rounds, and if both satisfy the same maximum probability state transition path of the two subsequences with the same end position, output the decoding sequence corresponding to the maximum probability state transition path.

2. The convolutional decoder according to claim 1, wherein The P Viterbi decoders are used to decode the P second subsequences in parallel.

3. The convolutional decoder according to claim 1 or 2, characterized in that The P first subsequences have the same length, and / or the P second subsequences have the same length.

4. The convolutional decoder according to any one of claims 1 to 3, wherein: It also includes P first registers and P second registers, each first register is used to store the cumulative score vector of a subsequence in the current round of decoding, and each second register is used to store the cumulative score vector of a subsequence in the previous round of decoding; in a new round of decoding, the cumulative score vector in the first register is moved to the paired second register, and the idle first register is used to store the cumulative score vector obtained in the current round of decoding.

5. The convolutional decoder according to any one of claims 1 to 4, characterized in that: The system also includes P output buffers, which are respectively used to store the decoded sequences output by each Viterbi decoder.

6. The convolutional decoder according to any one of claims 1 to 5, wherein: An input buffer is also included for storing the coding sequence.

7. The convolutional decoder according to any one of claims 1 to 6, wherein: A timer is also included for triggering the end of decoding when decoding cannot be ended within a preset time.

8. A decoding method, characterized in that: The convolutional decoder according to any one of claims 1 to 7 is applied to decode a coded sequence, wherein the coded sequence is divided into P first subsequences, and the tail sequences of the P first subsequences are P second subsequences, and the method comprises: For a first round of decoding, at least one of the P Viterbi decoders decodes the P second subsequences respectively, and updates cumulative score vectors of the P second subsequences, where the cumulative score vectors of the second subsequences represent cumulative scores of each state transition path obtained by decoding the second subsequence, and the cumulative scores of each state transition path represent probabilities of obtaining a set of decoded sequences by decoding along each state transition path. Before the first round of decoding, the cumulative score vectors of the P second subsequences are initially all zeros. Starting from the second round of decoding, the pth Viterbi decoder starts from the starting position of the pth first subsequence and cyclically decodes the coded sequence. The cumulative score vectors of the P first subsequences are updated in each decoding round. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence in the first round of decoding. P is an integer less than or equal to P. P comparators compare the cumulative score vectors of the two subsequences with the same end position obtained from the last two rounds of decoding. If both satisfy the same maximum probability state transition path of the two subsequences with the same end position, the decoding sequence corresponding to the maximum probability state transition path is output.

9. The method according to claim 8, characterized in that At least one of the P Viterbi decoders decodes the P second subsequences respectively, including: the P Viterbi decoders are used to decode the P second subsequences respectively in parallel.

10. An electronic device, characterized in that: The invention comprises a receiver, wherein the receiver comprises a convolutional decoder as claimed in any one of claims 1 to 7.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to claim 8 or 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 8 or 9 are implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 8 or 9 are implemented.

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