Convolutional decoder, decoding method and electronic device

Abstract

The application discloses a convolutional decoder, a decoding method and an electronic device, relates to the technical field of communication, and is used for reducing time overhead of convolutional code decoding. The application is used for decoding an encoded sequence, the encoded sequence is divided into P first sub-sequences, tail sequences of the P first sub-sequences are P second sub-sequences, and the convolutional decoder comprises the following steps: for first round decoding, P Viterbi decoders decode the P second sub-sequences respectively, and update cumulative score vectors of the P second sub-sequences; from second round decoding, a pth Viterbi decoder starts to perform cyclic decoding on the encoded sequence from a starting position of a pth first sub-sequence, and update cumulative score vectors of the P first sub-sequences; P comparators compare the cumulative score vectors of two sub-sequences with the same ending position in the last two rounds of decoding, and if the maximum probability state transition paths of the two sub-sequences with the same ending position are the same, the decoding sequence of the maximum probability state transition path is output.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a convolutional decoder, decoding method, and electronic device. Background Technology

[0002] Convolutional codes are a channel coding technique widely used in various wireless communication scenarios. Tail-biting convolutional codes are an optimized type of convolutional code. For the convolutional encoder on the transmitter side, initializing the registers in the convolutional encoder with multiple bits from the end of the encoded sequence can save coding overhead. However, for the convolutional decoder on the receiver side, the decoding process must go through multiple iterations to determine whether the initial state of the convolutional code state register of the convolutional decoder is correct, resulting in significant time overhead. Summary of the Invention

[0003] This application provides a convolutional decoder, a decoding method, and an electronic device to reduce the time overhead of convolutional code decoding.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] Firstly, a convolutional decoder is provided for decoding an encoded sequence, which is divided into P first subsequences, and the tail sequences of the P first subsequences are P second subsequences. The convolutional decoder includes: P Viterbi decoders and P comparators, where P is an integer greater than 1. For the first round of decoding, at least one of the P Viterbi decoders is used to decode the P second subsequences respectively, updating the cumulative score vector of the P second subsequences. The cumulative score vector of the second subsequences represents the cumulative score of each state transition path obtained by decoding the second subsequences. The cumulative score of each state transition path represents the probability of obtaining a decoded sequence along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second subsequences is all 0. The second round of decoding begins. The p-th Viterbi decoder starts from the beginning position of the p-th first subsequence and performs cyclic decoding on the encoded sequence. In each round of decoding, the cumulative score vectors of the P first subsequences are updated. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence in the first round of decoding. p is an integer less than or equal to P. P comparators are used to compare the cumulative score vectors of the two subsequences with the same ending position obtained in the last two rounds of decoding. If the two subsequences with the same ending position have the same maximum probability state transition path, the decoded sequence corresponding to the maximum probability state transition path is output.

[0006] The convolutional decoder provided in this application has a shorter decoding time in the first round because the sum of the lengths of the P second subsequences is less than the length of the entire encoded sequence. Starting from the second round of decoding, P Viterbi decoders begin with P different first subsequences and perform parallel cyclic decoding of the encoded sequence, updating the cumulative score vectors of the P first subsequences in each round. P comparators compare the cumulative score vectors of two subsequences with the same ending position in the last two rounds of decoding to determine whether the decoding has converged. The decoding time for each round is reduced to 1 / P of the original time, thus reducing the time overhead of convolutional code decoding.

[0007] In one possible implementation, P Viterbi decoders are used to decode the P second subsequences in parallel. This can further reduce the decoding time of the first round.

[0008] In one possible implementation, the P first subsequences have the same length, and / or the P second subsequences have the same length. Each Viterbi decoder decodes the subsequences in the same amount of time, resulting in the highest decoding efficiency for the entire convolutional decoder.

[0009] In one possible implementation, P first registers and P second registers are also included. Each first register stores the cumulative score vector of a subsequence decoded in the current round, and each second register stores the cumulative score vector of a subsequence decoded in the previous round. In the next round of decoding, the cumulative score vector in the first register is moved to the paired second register, and the free first register is used to store the cumulative score vector obtained in the current round of decoding. This can minimize the storage overhead of the cumulative score vector.

[0010] In one possible implementation, P output buffers are also included, each used to store the decoded sequence output by each Viterbi decoder.

[0011] In one possible implementation, an input buffer is also included for storing the encoded sequence.

[0012] In one possible implementation, a timer is also included to trigger the termination of decoding if decoding cannot be completed within a preset time. This can prevent decoding time from becoming too long.

[0013] In a second aspect, a decoding method is provided, applied to a convolutional decoder as described in the first aspect and any embodiment thereof, for decoding an encoded sequence, the encoded sequence being divided into P first sub-sequences, and the tail sequences of the P first sub-sequences being P second sub-sequences. The method includes: for a first round of decoding, at least one of the P Viterbi decoders decodes each of the P second sub-sequences, updating the cumulative score vector of the P second sub-sequences. The cumulative score vector of the second sub-sequences represents the cumulative score of each state transition path obtained by decoding the second sub-sequences, and the cumulative score of each state transition path represents the probability of obtaining a decoded sequence along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second sub-sequences is all 0; from The second round of decoding begins. The p-th Viterbi decoder starts from the beginning position of the p-th first subsequence and performs cyclic decoding on the encoded sequence. In each round of decoding, the cumulative score vectors of the P first subsequences are updated. The cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence. Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is the cumulative score vector of the previous second subsequence in the first round of decoding. p is an integer less than or equal to P. The P comparators compare the cumulative score vectors of the two subsequences with the same ending position obtained in the last two rounds of decoding. If the two subsequences with the same ending position have the same maximum probability state transition path, the decoded sequence corresponding to the maximum probability state transition path is output.

[0014] In one possible implementation, at least one of the P Viterbi decoders decodes the P second subsequences respectively, including: P Viterbi decoders for decoding the P second subsequences in parallel.

[0015] Thirdly, an electronic device is provided, including a receiver that includes a convolutional decoder as described in the first aspect and any embodiment thereof.

[0016] Fourthly, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described in the second aspect and any embodiment thereof.

[0017] Fifthly, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method described in the second aspect and any embodiment thereof.

[0018] In a sixth aspect, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the steps of the method described in the second aspect and any embodiment thereof.

[0019] In a seventh aspect, a chip system is provided, including a processor for supporting electronic devices in implementing the functions described in the second aspect above. In one possible design, the device further includes interface circuitry for receiving signals from other devices (e.g., memory) or sending signals to other devices (e.g., a communication interface). The chip system may include a chip and may also include other discrete devices.

[0020] The technical effects of the second to seventh aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a convolutional encoder provided in an embodiment of this application;

[0022] Figure 2 A schematic diagram of the structure of a convolutional encoder for tail-biting convolutional codes provided in this application embodiment;

[0023] Figure 3 A schematic diagram of a state transition vector provided in an embodiment of this application;

[0024] Figure 4 A schematic diagram of a state transition matrix and a cumulative score vector provided in an embodiment of this application;

[0025] Figure 5 This application provides a schematic diagram of a structure for decoding an encoded sequence.

[0026] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the structure of a mobile communication module provided in an embodiment of this application;

[0028] Figure 8 A schematic diagram of the structure of a convolutional decoder provided in an embodiment of this application;

[0029] Figure 9 A flowchart illustrating a decoding method provided in an embodiment of this application;

[0030] Figure 10 This application provides a schematic diagram illustrating the structure of a first subsequence and a second subsequence of an encoded sequence.

[0031] Figure 11 A schematic diagram illustrating decoding time provided for an embodiment of this application;

[0032] Figure 12A schematic diagram of a multi-round decoding method provided for an embodiment of this application;

[0033] Figure 13 This is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0034] First, some concepts involved in this application will be described.

[0035] The terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0036] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0037] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0038] The meaning of convolutional code is: the encoded sequence output by the convolutional encoder is the result of convolving the input sequence to be encoded with the system impulse response. Convolutional codes are usually denoted as (n, k, m), where n represents the length of the encoded sequence output by the convolutional encoder in each encoding operation, k represents the length of the input sequence to be encoded by the convolutional encoder in each encoding operation, and m represents the encoding storage density, which is equal to the number of registers in the convolutional encoder plus 1.

[0039] The number of registers in a convolutional encoder is also called the memory depth. If we consider a single bit stored in a register as its state, since each bit has two values ​​(0 and 1), there are 2^K possible states when the memory depth is K. When the convolutional encoder receives one bit of the sequence to be encoded, it triggers a transition from the old state to the new state in the registers. This process is called a state transition, and the encoder outputs a two-bit encoded sequence as the result of the convolutional encoding. Since the input sequence can be either 0 or 1, triggering two state transitions in the registers, there are a total of 2*(2^K) possible state transitions. Since the length of the encoded sequence is n, there are 2^n possible encoded sequences. The encoded sequence output by the convolutional encoder in a single encoding operation depends not only on the current input sequence but also on the previous state of the registers, and ultimately on all previous input sequences and the initial state of the registers. Therefore, the convolutional encoder has memory.

[0040] For example, Figure 1 This is the structure of a (2, 1, 4) convolutional encoder, where D1, D2, and D3 are binary registers, each used to store one binary bit. This represents a binary adder (performing addition or XOR operations). For each bit of the sequence to be encoded input to the input port IN of the convolutional encoder, the output ports OUT1 and OUT2 each output one bit of the encoded sequence, meaning the entire convolutional encoder outputs a two-bit encoded sequence as the convolutional encoding result. Therefore, the encoding efficiency of this convolutional encoder is input bits / output bits = 1 / 2. Furthermore, each input bit of the sequence to be encoded triggers a right shift of the sequence stored in the registers to the next register. That is, data in register D2 is shifted into register D3, and data in register D1 is shifted into register D2. Register D1 stores the newly input one bit of the sequence to be encoded. This process is called state transition. If the bits stored in these three registers are used as the states of the registers in the convolutional encoder, then K = 3, so there are 8 states, for example, represented in binary as 000 to 111. Furthermore, there are 16 state transitions. For example, in the convolutional encoder, the register state is 000. Inputting the sequence to be encoded (0) triggers a transition from 000 to 000, while inputting the sequence to be encoded (1) triggers a transition from 000 to 100. Since the encoded sequence length n = 2, there are 4 output encoded sequences, which are represented in binary as 00 to 11. Therefore, there are duplicate encoded sequences for state transitions, meaning that multiple state transitions share the same encoded sequence.

[0041] Before encoding, the registers in the convolutional encoder need to be initialized to a preset state to restore the encoder to a defined state. Similarly, after encoding, the registers in the convolutional encoder also need to be set to a preset state to restore the encoder to a defined state. For the convolutional decoder to decode correctly, it needs to know the number of registers (memory depth) and their preset states in the convolutional encoder. Knowing the structure of the convolutional encoder, the decoder can determine the encoded sequence output by observing the state transitions of the registers in the encoder; however, it cannot deduce the accurate state transitions from the encoded sequence.

[0042] For example, before inputting the valid data sequence to be encoded into the convolutional encoder to generate the valid encoded sequence, a redundant sequence to be encoded (e.g., all zeros) can be input first to generate a redundant encoded sequence. Similarly, after inputting the valid data sequence to be encoded into the convolutional encoder, a redundant sequence to be encoded (e.g., all zeros) can be input to generate a redundant encoded sequence. The length of the redundant sequence to be encoded is equal to the memory length, i.e., the number of registers in the convolutional encoder. For example, for... Figure 1 In the convolutional encoder shown, the length of the redundant sequence to be encoded is 3. For the convolutional decoder, given the number of registers and preset states in the convolutional encoder, after receiving the encoded sequence, the redundant encoded sequence at the beginning can be removed, and the encoded sequence of the valid data can be directly decoded. However, for the convolutional encoder, these redundant sequences to be encoded increase the encoding overhead.

[0043] To address the issue of increased encoding overhead, tail-biting convolutional coding was proposed. This involves inputting a sequence of length equal to the memory length at the end of the valid data sequence into the convolutional encoder as a redundant sequence. This ensures that the registers in the convolutional encoder remain in the same state at the end of encoding. For example, as shown... Figure 2 As shown, before inputting the valid data sequence C1-C8 into the convolutional encoder, the sequence C6-C8 is first input into the convolutional encoder, so that the initial state of register D3 is C6, the initial state of register D2 is C7, and the initial state of register D1 is C8. Although the tail-biting convolutional code saves encoding overhead, the decoding overhead of the convolutional decoder will be greatly increased because the convolutional decoder does not know the initial state of the registers in the convolutional encoder.

[0044] For tail-biting convolutional codes, a commonly used convolutional decoder is the Viterbi decoder. The working principle of the Viterbi decoder, based on the circular Viterbi algorithm (CVA), is explained as follows:

[0045] For example, Figure 1 The (2, 1, 4) convolutional encoder shown encodes each bit of the sequence to be encoded once, resulting in a two-bit encoded sequence. It also triggers a state transition in the encoder's registers from an old state to a new state. Therefore, the Viterbi decoder, during decoding, needs to decode every two bits of the encoded sequence once to obtain a one-bit decoded sequence; that is, the length of the decoded sequence is half the length of the encoded sequence. Ideally, this one-bit decoded sequence is identical to the one-bit sequence to be encoded, indicating correct decoding.

[0046] As mentioned earlier, when the memory depth of the convolutional encoder is K, the registers in the convolutional encoder have a total of 2^K states and 2*(2^K) possible state transitions. For example, ... Figure 3 As shown in A, Figure 1 Taking the (2, 1, 4) convolutional encoder as an example, the register has 8 states, represented in binary as 000 to 111. Since the input sequence to be encoded in the convolutional encoder can be either 0 or 1, there are 16 state transitions from the old state to the new state. Assuming the old state of the register in the convolutional encoder is 010, inputting the sequence to be encoded 0 will trigger the register to transition from the old state 010 to the new state 001 (i.e., state transition a). In other words, the sequence to be encoded 0 is the decoding sequence of state transition a. Inputting the sequence to be encoded 1 will trigger the register to transition from the old state 010 to the new state 101 (i.e., state transition c). In other words, the sequence to be encoded 1 is the decoding sequence of state transition c. Similarly, assuming the old state of the register in the convolutional encoder is 011, inputting the sequence to be encoded, 0, will trigger the register in the convolutional encoder to transition from the old state 011 to the new state 001 (i.e., state transition b). Conversely, the sequence to be encoded, 0, is the decoding sequence for state transition b. Inputting the sequence to be encoded, 1, will trigger the register to transition from the old state 011 to the new state 101 (i.e., state transition d). Conversely, the sequence to be encoded, 1, is the decoding sequence for state transition d. In summary, decoding according to each state transition will yield the corresponding decoding sequence.

[0047] Since the Viterbi decoder is unaware of the state of the registers in the convolutional encoder, it calculates a score for each state transition to assess the probability of these transitions. This score is based on the received encoded sequence and the encoded sequence output by the convolutional encoder under various state transitions (e.g., 16 state transitions). A higher score indicates a more likely correct state transition. The score is calculated as follows: if the received encoded sequence and the output encoded sequence of the convolutional encoder under a given state transition share one bit, the score is 1; two bits share the same bit, the score is 2; and no bits share the same bit, the score is 0.

[0048] For example, such as Figure 3 As shown in Figure A, assuming the Viterbi decoder actually receives a two-bit encoded sequence of 10, the encoded sequence output by state transition a of the convolutional encoder is 01, which is completely different from the received encoded sequence 10. Therefore, the score corresponding to state transition a is 0. The encoded sequence output by state transition b of the convolutional encoder is 10, which is exactly the same as the received encoded sequence 10. Therefore, the score corresponding to state transition b is 2. So state transition b has a higher probability than state transition a. Similarly, assuming the Viterbi decoder actually receives a two-bit encoded sequence of 10, the encoded sequence output by state transition c of the convolutional encoder is 11, which has one bit in common with the received encoded sequence 10. Therefore, the score corresponding to state transition c is 1. The encoded sequence output by state transition d of the convolutional encoder is 00, which has one bit in common with the received encoded sequence 10. Therefore, the score corresponding to state transition d is 1. The probabilities of state transition c and state transition d are equal. That is, the new state 101 may be triggered by the input sequence to be encoded 0 of the convolutional encoder and transitioned from the old state 010, or it may be triggered by the input sequence to be encoded 1 of the convolutional encoder and transitioned from the old state 011.

[0049] To retain the state transition with the highest probability, we can prioritize retaining the state transition with the highest score, and retain the remaining state transitions according to the mutual exclusion principle, so that each new state corresponds to an old state through a single state transition. For example, such as... Figure 3 As shown in Figure B, among state transitions a, b, c, and d, state transition b has the highest score, so it is retained. State transition b can also be called the surviving path, and the sequence to be encoded that triggers state transition b (0) is the decoding sequence. State transitions c and d have the same score, but since state transitions b and d are mutually exclusive, state transition c is retained. State transition c can also be called the surviving path, and the sequence to be encoded that triggers state transition c (1) is the decoding sequence. Based on the same principle, other state transitions can be retained.

[0050] To facilitate the derivation of the old state corresponding to the state transition with the highest probability (i.e., the highest score) from the new state, or simply derivation of the corresponding old state from the new state, we can define a state transition vector of dimension M*1, where M = 2^K. The index of each row of the state transition vector represents a new state in the registers of the convolutional encoder, and the data stored in each row is the index of the old state of the state transition with the highest score corresponding to that new state.

[0051] For example, such as Figure 3 As shown in Figure C, the indices of the first to eighth rows of the state transition vector represent the states 000 to 111 of the register, respectively. For state 001, to facilitate the deduction of the old state 011 corresponding to state transition b from the new state 001, the data stored at index 001 in the state transition vector is the old state 011 corresponding to state transition b. Similarly, for state 101, to facilitate the deduction of the old state 010 corresponding to state transition c from the new state 101, the data stored at index 101 in the state transition vector is the old state 010 corresponding to state transition c. Based on the same principle, other positions in the state transition vector store the indices of the corresponding old states. In this way, the old state corresponding to the state transition with the highest probability (i.e., the highest score) can be deduced from the index of any row of the state transition vector (i.e., the new state).

[0052] Furthermore, when the Viterbi decoder receives a new encoded sequence, it indicates a new state transition, and the original new state becomes the old state. This process continues, with multiple consecutive state transitions forming a state transition path, resulting in a total of 2^K state transition paths. Since decoding according to a state transition yields a decoded sequence (i.e., the sequence to be encoded that triggers the state transition), decoding according to a state transition path yields a set of decoded sequences. For example, such as... Figure 4 As shown in A, following the direction of the arrow, after two rounds of state transitions, state 000 -> state 100 -> state 010 is the first state transition path, state 001 -> state 000 -> state 000 is the second state transition path, and so on.

[0053] To store state transition paths and continuously deduce earlier states from new states, a state transition matrix of dimension M*N is defined based on the state transition vector, where N represents the backtracking length of the state transition, i.e., it can store data for a maximum of N consecutive state transitions. Each column of the state transition matrix is ​​a state transition vector as described above. Similar to the state transition vector, the index of each row of the state transition matrix is ​​a new state in the registers of the convolutional encoder, and the data stored in each row is the index of the old state corresponding to the state with the highest score for that new state. For example, as shown... Figure 4As shown in Figure B, this represents the value of the state transition matrix after two rounds of state transitions. It should be noted that since the backtracking length N is finite, when the state transition matrix is ​​full, and the Viterbi decoder receives a new encoded sequence, the data in the original first column of the state transition matrix is ​​moved out of the matrix, the data in the other columns are shifted one column to the left, and the Nth column is left free to store new data.

[0054] In addition, an M*1 dimensional cumulative score vector is defined to store the sum of the scores of each state transition path. Each state transition path corresponds to a cumulative score, which essentially represents the probability of obtaining a decoded sequence along that path. The index of each row of the cumulative score vector represents a state of a register in the convolutional encoder, i.e., the state of the latest endpoint of a state transition path. Initially, the data in the state transition matrix are all invalid values, and the data in the cumulative score vector are all 0s. For example, as shown... Figure 4 As shown in Figure C, this represents the change in the cumulative score vector after two rounds of state transitions. S1-S8 represent the scores of each state transition in the first round, and s1-s8 represent the scores of each state transition in the second round. The score of the first state transition path (state 000->state 100->state 010) is S5+s3, the score of the second state transition path (state 001->state 000->state 000) is S1+s1, and so on. Since each state transition path corresponds to a set of decoding sequences, when decoding is complete, the state transition path with the highest cumulative score (i.e., the highest probability) is the decoding path, and the set of decoding sequences corresponding to this state transition path is the decoding result.

[0055] During normal decoding in a Viterbi decoder, based on the characteristic that the registers in the convolutional encoder have the same state at the start and end times of the tail-biting convolutional code encoding, the received encoded sequence ( Figure 5 Multiple copies of (as shown in A) are linked end to end to form a long sequence ( Figure 5 As shown in Figure B), this long sequence is then decoded by a Viterbi decoder. Figure 5 As shown in CG, this is equivalent to performing multiple rounds of decoding on the received encoded sequence. Figure 5 As shown in Figure CE, the Viterbi decoder decodes every two bits of the encoded sequence once, obtaining a one-bit decoded sequence corresponding to each state transition path. Each row in the decoded sequence represents the decoded sequence corresponding to one state transition path. Furthermore, as the decoding process progresses, the data in the state transition matrix increases column by column. For example... Figure 5As shown in F and G, at the end of each decoding round, the state transition path (the part marked in bold in the cumulative score vector, i.e., the part with the highest probability) with the largest cumulative score is selected as the decoding path, and the decoding sequence corresponding to this state transition path (the part marked in bold in the decoding sequence) is the decoding result. Furthermore, when the decoding paths eventually converge after multiple decoding rounds, that is, when the state transition paths with the highest probability are the same, for example... Figure 5 When the decoding paths obtained from the two most recent rounds of decoding shown in F and G are the same (i.e., the indices of the largest cumulative scores in the cumulative score vector are the same), the decoding ends and the decoding result is output.

[0056] It's important to note that during the first round of decoding, the accumulated score vector is initialized to 0. Subsequent rounds of decoding do not clear the accumulated score vector obtained from the previous round; rather, the accumulated score vector from the previous round serves as the initial value for the accumulated score vector in the next round. Therefore, for multi-round decoding, the encoded sequence being decoded remains unchanged; only the initial value of the accumulated score vector changes.

[0057] This shows that under poor signal quality, CVA decoding repeats many rounds of decoding to achieve final convergence. Therefore, the decoding time t = NT, where N is the number of decoding rounds and T is the time required to decode the complete encoded sequence in one round. Furthermore, the convergence criterion of CVA decoding is unstable. If the memory depth is small, even if two rounds of decoding follow the same path, it may be a coincidence rather than true convergence. For example, in the case of a memory depth of 3, there are only 8 possible register states, meaning there is a 1 / 8 probability of convergence even with decoding errors.

[0058] The convolutional decoder, decoding method, and electronic device provided in this application decode P subsequences of the encoded sequence in the first round of decoding. Since the sum of the lengths of these P subsequences is less than the length of the entire encoded sequence, the time to complete the first round of decoding is shorter. Starting from the second round of decoding, P Viterbi decoders each begin with P different subsequences and perform parallel cyclic decoding of the encoded sequence, reducing the decoding time of each round to 1 / P of the original. This reduces the time overhead of convolutional code decoding. P is a positive integer greater than 1.

[0059] This application provides an electronic device with wireless communication capabilities. The electronic device can be mobile or fixed. It can be deployed on land (e.g., indoors or outdoors, handheld or vehicle-mounted), on water (e.g., on ships), or in the air (e.g., airplanes, balloons, and satellites). This electronic device can be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device. For example, it can be a mobile phone, tablet computer, laptop computer, smart bracelet, smart screen, smartwatch, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical care, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. This application does not limit the specific type and structure of the electronic device. The following describes one possible structure of the electronic device.

[0060] Taking mobile phones as an example, Figure 6 A possible structure of an electronic device 101 is shown. This electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, antenna 1, antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, it may also include an audio digital signal processor (ADSP) 243.

[0061] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 101. In other embodiments of this application, the electronic device 101 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0062] Processor 210 may include one or more processing units, such as: a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, and a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, processor 210 may be an application processor (AP). Alternatively, processor 210 may be integrated into a system-on-chip (SoC). Or, processor 210 may be integrated into an integrated circuit (IC) chip. The processor 210 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0063] The processor 210 implements the decoding method involved in this application by executing a computer program stored in the internal memory 221.

[0064] The processor 210 may also include a memory for storing computer instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. This memory can store computer instructions or data that the processor 210 has just used or that are being used repeatedly. If the processor 210 needs to use the same computer instructions or data again, it can retrieve them directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 210, and thus improves system efficiency.

[0065] In some embodiments, the processor 210 may include one or more interfaces. These interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0066] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can process audio signals and sensor data. Even when the processor is in sleep mode, the ADSP 243 can remain operational, thereby reducing the power consumption of the electronic device.

[0067] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 101. In other embodiments of this application, the electronic device 101 may also adopt different interface connection methods or a combination of multiple interface connection methods as described in the above embodiments.

[0068] The external storage interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 101. The external memory card communicates with the processor 210 through the external storage interface 220 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0069] Internal memory 221 can be used to store computer executable program code, which includes computer instructions. Processor 210 executes various functional applications and data processing of electronic device 101 by running the computer instructions stored in internal memory 221. In addition, internal memory 221 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0070] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0071] Electronic device 101 can implement audio functions such as music playback and recording through audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone jack 270D, and application processor.

[0072] Audio module 270 is used to convert digital audio information into analog audio signal output, and also to convert analog audio input into digital audio signal. In some embodiments, audio module 270 may be located in processor 210, or some functional modules of audio module 270 may be located in processor 210. Speaker 270A, also called a "loudspeaker," is used to convert audio electrical signals into sound signals. Receiver 270B, also called a "handpiece," is used to convert audio electrical signals into sound signals. Microphone 270C, also called a "microphone" or "microphone," is used to convert sound signals into electrical signals. Electronic device 101 may be equipped with at least one microphone 270C. Headphone jack 270D is used to connect wired headphones. Headphone jack 270D may be a USB interface 230, or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, or a Cellular Telecommunications Industry Association of the USA (CTIA) standard interface.

[0073] Buttons 290 include a power button, volume buttons, etc. Buttons 290 can be mechanical buttons or touch buttons. Electronic device 101 can receive button input and generate key signal inputs related to user settings and function control of electronic device 101. Motor 291 can generate vibration alerts. Motor 291 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 292 can be an indicator light, used to indicate charging status, battery level changes, messages, missed calls, notifications, etc. SIM card interface 295 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with electronic device 101. Electronic device 101 can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. In some embodiments, electronic device 101 employs an embedded SIM (eSIM) card, which can be embedded in electronic device 101 and cannot be separated from electronic device 101.

[0074] Electronic device 101 can implement shooting functions through an ISP, camera 293, video codec, GPU, display 294, and application processor. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be set in the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, electronic device 101 may include one or N cameras 293, where N is a positive integer greater than 1.

[0075] Electronic device 101 can implement display functions through a GPU, display screen 294, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 210 may include one or more GPUs, which execute computer instructions to generate or modify display information.

[0076] The sensor module 280 may include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, an angle sensor, etc. When the display screen 294 is a foldable screen, the angle sensor can detect the folding angle of the display screen 294, which ranges from 0 to 180 degrees.

[0077] Battery 241 may include one or more batteries to power a load.

[0078] The power management module 240 is used to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock, or other electronic device 101 with reverse wireless charging capability. The power management module 240 can receive wireless charging input via the wireless charging coil 242 of the electronic device. The charger can also be a wired charger; for example, the power management module 240 can receive charging input from a wired charger via a USB interface 230. The power management module 240 is also referred to as a charging chip.

[0079] The power management module 240 charges the battery 241 while simultaneously supplying power to the electronic devices. It receives input from the battery 241 and powers the processor 210, internal memory 221, external memory interface 220, display screen 294, camera 293, and wireless communication module 260. The power management module 240 can also monitor parameters such as the battery 241's capacity, voltage, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 240 may also be integrated into the processor 210.

[0080] The display screen 294 is used to display images, videos, etc. The display screen 294 includes a display panel. In some embodiments, the electronic device 101 may include one or more display screens 294.

[0081] The wireless communication function of electronic device 101 can be realized through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, modem processor, etc.

[0082] Antennas 1 and 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 101 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0083] Mobile communication module 250 can provide wireless communication solutions including 2G / 3G / 4G / 5G for use on electronic device 101. Wireless communication module 260 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) for use on electronic device 101. In some embodiments, antenna 1 of electronic device 101 is coupled to mobile communication module 250, and antenna 2 is coupled to wireless communication module 260, enabling electronic device 101 to communicate with networks and other devices via wireless communication technology.

[0084] like Figure 7 As shown, the mobile communication module 250 may include a baseband chip 31, a radio frequency integrated circuit (RFIC) 32, and a radio frequency front-end module (FEM) 33.

[0085] The baseband chip 31 converts data from the processor 210 into baseband signals, including modulation / demodulation, digital filtering, and equalization processing. The RFIC 32 integrates a transmitter and a receiver. The transmitter converts the baseband signal from the baseband chip 31 into a radio frequency (RF) signal, which is then transmitted through the RF front-end module 33 and at least one of the multiple antennas 34. The receiver receives the RF signal through at least one antenna and the RF front-end module 33, converts it back into a baseband signal, and sends it to the baseband chip 31. The receiver in the RFIC 32 includes a convolutional decoder (e.g., a Viterbi decoder) for decoding the received coded sequence. The baseband chip 31 converts the baseband signal into data and sends it to the processor 210. It should be noted that the baseband chip 31 and RFIC 32 can also be integrated with the processor 210 into a single SoC (System-on-a-Chip).

[0086] like Figure 8 As shown, the convolutional decoder includes an input buffer 801, P (P is a positive integer greater than 1) Viterbi decoders (e.g., Viterbi decoder 8021-8023), P comparators (e.g., comparator 8031-8033), P first registers (e.g., first register 8041-8043), P second registers (e.g., second register 8051-8053), P output buffers (e.g., output buffer 8061-8063), and a timer 807. For example, Figure 8 The example given is P = 3. The following description, based on the decoding method performed by the convolutional decoder, details the function of each component in the convolutional decoder. Figure 9 As shown, the decoding method includes:

[0087] S101. For the first round of decoding, at least one of the P Viterbi decoders decodes the P second subsequences in the encoded sequence to obtain the decoding sequence corresponding to each state transition path of the P second subsequences, and updates the cumulative score vector of the P second subsequences.

[0088] The input buffer 801 can be used to buffer the encoded sequence received by the receiver. By cyclically accessing the encoded sequence, it is equivalent to concatenating multiple copies of the encoded sequence end to end to form a... Figure 5 A is a long sequence shown in Figure A.

[0089] For example, such as Figure 10As shown, the entire encoded sequence can be divided into P first subsequences, such as first subsequence 1, first subsequence 2, and first subsequence 3. The lengths of the P first subsequences can be the same or different. The tail sequence of each first subsequence is a second subsequence, such as second subsequence 1, second subsequence 2, and second subsequence 3. That is, each first subsequence includes one second subsequence, and the second subsequence has the same ending position as the first subsequence. The length of the second subsequence is less than the length of the first subsequence. The tail sequences of the P first subsequences contain a total of P second subsequences, and the lengths of these P second subsequences can be the same or different. Each first subsequence and each second subsequence are continuous sequences.

[0090] This application does not limit the correspondence between P Viterbi decoders and P subsequences (first subsequence or second subsequence); that is, one Viterbi decoder can decode multiple subsequences (e.g., P second subsequences), or it can decode only one subsequence. Figure 11 As shown, for the first round of decoding (i.e., decoding round 1), since the sum of the lengths of the P second sub-sequences is less than the length of the entire encoded sequence, if a Viterbi decoder serially decodes the P second sub-sequences, the time to complete the first round of decoding is shorter compared to existing technologies. Furthermore, the P Viterbi decoders can decode the P second sub-sequences in parallel to further reduce the time of the first round of decoding. For example, Figure 8 The Viterbi decoder 8021 shown can decode the second subsequence 1. Figure 8 The Viterbi decoder 8022 shown can decode the second subsequence 2. Figure 8 The Viterbi decoder 8023 shown can decode the second subsequence 3. When the lengths of the P first subsequences are the same, and / or when the lengths of the P second subsequences are the same, for the same round of decoding, each Viterbi decoder takes the same amount of time to decode the subsequence, and the decoding efficiency of the entire convolutional decoder is the highest.

[0091] It should be noted that this application decodes each subsequence to obtain the decoded sequence corresponding to each state transition path of each subsequence. Similarly, as described above, the entire encoded sequence can be decoded to obtain the decoded sequence corresponding to each state transition path. The decoded sequence obtained by the Viterbi decoder for each subsequence (e.g., the first subsequence or the second subsequence) can be buffered in the output buffer corresponding to that Viterbi decoder. For example, Figure 8 The decoded sequence obtained by the Viterbi decoder 8021 decoding the subsequence shown can be cached in... Figure 8 The output buffer 8061 is shown. Figure 8 The decoded sequence obtained by the Viterbi decoder 8022 decoding the subsequence shown can be cached in... Figure 8 The output buffer 8062 is shown. Figure 8 The decoded sequence obtained by the Viterbi decoder 8023 decoding the subsequence shown can be cached in... Figure 8 The output buffer 8063 shown is different from the prior art in that the decoding start position is different, the decoding end position is different, the number of state transition paths is different, and the initial value of the cumulative score vector is different.

[0092] In existing technologies, for each round of decoding, decoding begins at the beginning of the entire encoded sequence and continues until the end of the entire encoded sequence. This application, for each round of decoding, begins decoding at the beginning of each sub-sequence and continues until the end of that sub-sequence.

[0093] Assuming the number of registered states is M, existing technologies can obtain M state transition paths by decoding the entire encoded sequence. In this application, decoding each subsequence can yield M state transition paths, therefore, decoding P subsequences results in a total of P*M state transition paths.

[0094] In existing technologies, the cumulative score vector represents the cumulative score of each state transition path obtained by decoding the entire encoded sequence. In this application, the cumulative score vector of the first subsequence represents the cumulative score of each state transition path obtained by decoding the first subsequence; the cumulative score vector of the second subsequence represents the cumulative score of each state transition path obtained by decoding the second subsequence. The cumulative score of each state transition path essentially represents the probability of obtaining a decoded sequence along that state transition path. In this application, the cumulative score vector Sab represents the cumulative score vector of the b-th subsequence (either the first or second subsequence) obtained from the a-th round of decoding. For example, as... Figure 12 As shown, before the first round of decoding, the initial value of the cumulative score vector of each second subsequence is all 0. Decoding second subsequence 1 in the first round yields its cumulative score vector S11; decoding second subsequence 2 yields its cumulative score vector S12; and decoding second subsequence 3 yields its cumulative score vector S13. For an example of how to update the cumulative score vector, refer to [link to example]. Figure 4 The relevant descriptions of C will not be repeated here.

[0095] Each first register stores the cumulative score vector of a subsequence (either the first or second subsequence) from the current decoding round, and each second register stores the cumulative score vector of a subsequence (either the first or second subsequence) from the previous decoding round. Therefore, the first and second registers are paired, used to store the cumulative score vectors of two subsequences with the same ending position obtained from the most recent two rounds (the current and previous rounds) of decoding. In a new decoding round, the cumulative score vectors in the first registers are moved to their paired second registers, freeing up the first registers to store the cumulative score vector obtained from the current decoding round. In the first decoding round, each first register stores the cumulative score vector of one second subsequence. This minimizes the storage overhead of the cumulative score vectors. For example, in the first decoding round... Figure 8 The first register 8041 shown is used to store the cumulative score vector S11 of the second subsequence 1. Figure 8 The first register 8042 shown is used to store the cumulative score vector S12 of the second subsequence 2. Figure 8 The first register 8043 shown is used to store the cumulative score vector S13 of the second subsequence 3.

[0096] S102. Starting from the second round of decoding, the p-th Viterbi decoder starts from the beginning position of the p-th first subsequence and performs cyclic decoding on the encoded sequence. In each round of decoding, the decoded sequences corresponding to each state transition path of the P first subsequences are obtained, and the cumulative score vector of the P first subsequences is updated, where p is an integer less than or equal to P.

[0097] Before the second round of decoding, the initial value of the cumulative score vector of any first subsequence is taken from the cumulative score vector of the previous second subsequence in the first round of decoding. Specifically, the initial value of the cumulative score vector of the first first subsequence (first subsequence 1) in the second round of decoding is taken from the cumulative score vector of the last second subsequence (second subsequence 3) in the first round of decoding. For example, as shown... Figure 12 As shown, for the second round of decoding, the initial value of the cumulative score vector of the first subsequence 1 is the cumulative score vector S13 of the second subsequence 3 in the first round of decoding.

[0098] For example, starting from the second round of decoding, the first Viterbi decoder ( Figure 8 The Viterbi decoder 8021 shown starts cyclically decoding the encoded sequence from the beginning of the first subsequence (first subsequence 1). The second Viterbi decoder ( Figure 8 The Viterbi decoder 8022 shown starts cyclically decoding the encoded sequence from the beginning position of the second first subsequence (first subsequence 2). The third Viterbi decoder ( Figure 8The Viterbi decoder 8023 shown starts cyclically decoding the encoded sequence from the beginning position of the third first subsequence (first subsequence 3). Each Viterbi decoder performs cyclic decoding of the encoded sequence, which is compatible with cyclic decoding in the prior art and eliminates the need for frequent data transfer between Viterbi decoders, thus reducing implementation complexity.

[0099] Starting from the second round of decoding, each round of decoding involves P Viterbi decoders decoding a different first subsequence, and these P first subsequences can be concatenated to form a complete encoded sequence. Therefore, as... Figure 11 As shown, starting from the second round of decoding (i.e., decoding rounds 2, 3, 4, 5, etc.), the time increase for each round of decoding is equal to the time required for a Viterbi decoder to decode a first subsequence. For example, when P is 3, it is equivalent to one-third of the decoding time for the entire encoded sequence in the prior art.

[0100] Cyclic decoding of a coded sequence means decoding the sequence sequentially from the first subsequence. The initial value of the cumulative score vector of the next first subsequence is equal to the cumulative score vector of the previous first subsequence. After decoding the last first subsequence of the coded sequence, decoding restarts from the first first subsequence.

[0101] Figure 8 The Viterbi decoder 8021 shown decodes the first subsequence 1 to obtain the decoded sequences corresponding to each state transition path of the second subsequence 1, and updates the cumulative score vector of the first subsequence 1 to S21. The initial value of the cumulative score vector of the first subsequence 2 is the cumulative score vector S11 of the second subsequence 1 in the first round of decoding. Figure 8 The Viterbi decoder 8022 shown decodes the first subsequence 2 to obtain the decoded sequences corresponding to each state transition path of the second subsequence 2, and updates the cumulative score vector of the first subsequence 2 to S22. The initial value of the cumulative score vector of the first subsequence 3 is the cumulative score vector S12 of the second subsequence 2 in the first round of decoding. Figure 8 The Viterbi decoder 8023 shown decodes the first subsequence 3 to obtain the decoding sequence corresponding to each state transition path of the second subsequence 3, and updates the cumulative score vector of the first subsequence 3 to S23.

[0102] During the second round of decoding, the accumulated score vector in the first register is moved to the paired second register, freeing up the first register to store the accumulated score vector obtained from the second round of decoding. Starting from the second round of decoding, each first register stores the accumulated score vector of one first subsequence.

[0103] For example, during the second round of decoding, Figure 8The first register 8041 shown is used to store the cumulative score vector S21 of the first subsequence 1 of the second round of decoding. Figure 8 The second register 8051 shown is used to store the cumulative score vector S11 of the second subsequence 1 of the first round of decoding. Figure 8 The first register 8042 shown is used to store the cumulative score vector S22 of the first subsequence 2 of the second round of decoding. Figure 8 The second register 8052 shown is used to store the cumulative score vector S12 of the second subsequence 2 of the first round of decoding. Figure 8 The first register 8043 shown is used to store the cumulative score vector S23 of the first subsequence 3 of the second round of decoding. Figure 8 The second register 8053 shown is used to store the cumulative score vector S13 of the second subsequence 3 of the first round of decoding.

[0104] For example, during the third round of decoding, Figure 8 The first register 8041 shown is used to store the cumulative score vector S31 of the first subsequence 1 of the third round of decoding. Figure 8 The second register 8051 shown is used to store the cumulative score vector S21 of the first subsequence 1 of the second round of decoding. Figure 8 The first register 8042 shown is used to store the cumulative score vector S32 of the first subsequence 2 of the third round of decoding. Figure 8 The second register 8052 shown is used to store the cumulative score vector S22 of the first subsequence 2 of the second round of decoding. Figure 8 The first register 8043 shown is used to store the cumulative score vector S33 of the first subsequence 3 of the third round of decoding. Figure 8 The second register 8053 shown is used to store the cumulative score vector S23 of the first subsequence 3 of the second round of decoding.

[0105] Similarly, in the fourth round of decoding, we can obtain the cumulative score vector S41 of the first subsequence 1, the cumulative score vector S42 of the first subsequence 2, and the cumulative score vector S43 of the first subsequence 3. In the fifth round of decoding, we can obtain the cumulative score vector S51 of the first subsequence 1, the cumulative score vector S52 of the first subsequence 2, and the cumulative score vector S53 of the first subsequence 3. Further details are omitted.

[0106] Starting from the second round of decoding, the S103 judgment process is executed once after each round of decoding.

[0107] S103, P comparators, starting from the second round of decoding, after each round of decoding, compare the cumulative score vectors of the two subsequences with the same ending position obtained from the last two rounds of decoding. If the maximum probability state transition path of the two subsequences with the same ending position is the same, then output the decoding sequence corresponding to the maximum probability state transition path (i.e., end the decoding); otherwise, continue to the next round of decoding.

[0108] The two subsequences with the same ending position can be the first subsequence and the second subsequence with the same ending position in the last two rounds of decoding (for example, in the second round of decoding, the first subsequence 1 of the second round of decoding and the second subsequence 1 of the first round of decoding), or they can be the two first subsequences with the same ending position in the last two rounds of decoding (for example, in the third round of decoding, the first subsequence 1 of the second round of decoding and the first subsequence 1 of the third round of decoding).

[0109] For example, such as Figure 12 As shown, during the second round of decoding, Figure 8 The comparator 8031 ​​shown can compare the cumulative score vector S21 of the first subsequence 1 of the second round of decoding with the cumulative score vector S11 of the second subsequence 1 of the first round of decoding. Figure 8 The comparator 8032 shown can compare the cumulative score vector S22 of the first subsequence 2 in the second round of decoding with the cumulative score vector S12 of the second subsequence 2 in the first round of decoding. Figure 8 The comparator 8033 shown can compare the cumulative score vector S23 of the first subsequence 3 in the second round of decoding with the cumulative score vector S13 of the second subsequence 3 in the first round of decoding. If comparator 8031 ​​determines that the maximum probability state transition path of the first subsequence 1 in the second round of decoding is the same as that of the second subsequence 1 in the first round of decoding, and if comparator 8032 determines that the maximum probability state transition path of the first subsequence 2 in the second round of decoding is the same as that of the second subsequence 2 in the first round of decoding, and if comparator 8033 determines that the maximum probability state transition path of the first subsequence 3 in the second round of decoding is the same as that of the second subsequence 3 in the first round of decoding, then the decoding converges, and comparator 8031 ​​will... Figure 8 The output buffer 8061 shows the decoded sequence output corresponding to the highest probability state transition path of the first subsequence 1, which is buffered in the output buffer 8061. The comparator 8032 will... Figure 8 The output buffer 8062 shows the decoded sequence output corresponding to the maximum probability state transition path of the first subsequence 2, which is buffered in the output buffer 8062. The comparator 8033 will... Figure 8 The output buffer 8063 shows the output of the decoding sequence corresponding to the highest probability state transition path of the first subsequence 3. These three decoding sequences are merged into the final decoding result, and decoding ends. Otherwise, the next round of decoding continues.

[0110] For example, such as Figure 12 As shown, during the third round of decoding, Figure 8 The comparator 8032 shown can compare the cumulative score vector S32 of the first subsequence 2 in the third round of decoding with the cumulative score vector S22 of the first subsequence 2 in the second round of decoding. Figure 8 The comparator 8033 shown can compare the cumulative score vector S33 of the first subsequence 3 in the third round of decoding with the cumulative score vector S33 of the first subsequence 3 in the second round of decoding. Figure 8 The comparator 8031 ​​shown can compare the cumulative score vector S31 of the first subsequence 1 of the third round of decoding with the cumulative score vector S31 of the first subsequence 1 of the second round of decoding. If comparator 8031 ​​determines that the maximum probability state transition path of the first subsequence 1 of the third round of decoding is the same as that of the first subsequence 1 of the second round of decoding, and if comparator 8032 determines that the maximum probability state transition path of the first subsequence 2 of the third round of decoding is the same as that of the first subsequence 2 of the second round of decoding, and if comparator 8033 determines that the maximum probability state transition path of the first subsequence 3 of the third round of decoding is the same as that of the first subsequence 3 of the second round of decoding, then the decoding converges, and comparator 8031 ​​will... Figure 8 The output buffer 8061 shows the decoded sequence output corresponding to the highest probability state transition path of the first subsequence 1, which is buffered in the output buffer 8061. The comparator 8032 will... Figure 8 The output buffer 8062 shows the decoded sequence output corresponding to the maximum probability state transition path of the first subsequence 2, which is buffered in the output buffer 8062. The comparator 8033 will... Figure 8 The output buffer 8063 shows the output of the decoded sequence corresponding to the highest probability state transition path of the first subsequence 3. These three decoded sequences are merged into the final decoded result, and decoding ends. Otherwise, the next round of decoding continues. And so on. The comparison between the fourth and fifth rounds of decoding will not be described again.

[0111] Compared to existing technologies, which only determine the state transition path once at the end of each decoding round, this application determines the state transition path at point P in each decoding round. Furthermore, these points P are evenly distributed throughout the entire encoded sequence, thus resulting in higher accuracy in determining whether the decoding has converged.

[0112] Figure 8 The timer shown is used for timing. If decoding cannot be completed within the preset time, the timer will trigger the termination of decoding, and the decoding sequence obtained from the last round of decoding will be used as the decoding result. This can avoid decoding time being too long.

[0113] The convolutional decoder, decoding method, and electronic device provided in this application have the following advantages: In the first round of decoding, the sum of the lengths of the P second sub-sequences is less than the length of the entire encoded sequence. Therefore, decoding the P second sub-sequences takes less time to complete the first round of decoding. Starting from the second round of decoding, P Viterbi decoders begin with P different first sub-sequences and perform parallel cyclic decoding of the encoded sequence, updating the cumulative score vectors of the P first sub-sequences in each round. P comparators compare the cumulative score vectors of two sub-sequences with the same ending position in the last two rounds of decoding to determine whether the decoding has converged. The decoding time for each round becomes 1 / P of the original. This reduces the time overhead of convolutional code decoding, greatly improves decoding efficiency, and shortens decoding delay even with poor signal quality. It can be applied to any scenario that decodes tail-biting convolutional codes, such as the geostationary earth orbit mobile radio interface 1 (GMR-1) for satellite communication protocols, the world interoperability for microwave access (WiMAX) protocol for connecting Wi-Fi hotspots, and the long term evolution (LTE) protocol for cellular communication.

[0114] like Figure 13 As shown, this application embodiment also provides a chip system. The chip system 130 includes at least one processor 1301 and at least one interface circuit 1302. The at least one processor 1301 and at least one interface circuit 1302 are interconnected via lines. The processor 1301 is used to support an electronic device in implementing the various steps in the above method embodiments, for example... Figure 9 The method shown allows at least one interface circuit 1302 to be used to receive signals from other devices (e.g., memory) or to send signals to other devices (e.g., a communication interface). The chip system may include a chip and may also include other discrete components.

[0115] This application also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it causes the electronic device to perform the various steps in the above method embodiments, such as executing... Figure 9 The method shown.

[0116] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, it causes the electronic device to perform the steps described in the method embodiments above, such as executing... Figure 9 The method shown.

[0117] The technical effects of the chip system, computer-readable storage medium, and computer program product are described in the preceding method embodiments.

[0118] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0119] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0122] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0124] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0125] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A convolutional decoder, characterized in that, The convolutional decoder is used to decode an encoded sequence, which is divided into P first subsequences and P second subsequences as the tail sequences of the P first subsequences. The convolutional decoder includes P Viterbi decoders and P comparators, where P is an integer greater than 1. For the first round of decoding, at least one of the P Viterbi decoders is used to decode the P second subsequences respectively and update the cumulative score vector of the P second subsequences. The cumulative score vector of the second subsequences represents the cumulative score of each state transition path obtained by decoding the second subsequences. The cumulative score of each state transition path represents the probability of obtaining a set of decoded sequences along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second subsequences is all 0. Starting from the second round of decoding, the p-th Viterbi decoder begins cyclically decoding the encoded sequence from the starting position of the p-th first sub-sequence. In each round of decoding, the cumulative score vectors of the P first sub-sequences are updated. The cumulative score vector of the first sub-sequence represents the cumulative score of each state transition path obtained by decoding the first sub-sequence. Before the second round of decoding, the initial value of the cumulative score vector of any first sub-sequence is the cumulative score vector of the previous second sub-sequence in the first round of decoding; p is an integer less than or equal to P. The P comparators are used to compare the cumulative score vectors of two subsequences with the same ending position obtained from the two most recent rounds of decoding. If the maximum probability state transition path of the two subsequences with the same ending position is the same, the decoding sequence corresponding to the maximum probability state transition path is output.

2. The convolutional decoder according to claim 1, characterized in that, The P Viterbi decoders are used to decode the P second subsequences in parallel.

3. The convolutional decoder according to claim 1 or 2, characterized in that, The P first subsequences have the same length, and / or the P second subsequences have the same length.

4. The convolutional decoder according to any one of claims 1-3, characterized in that, It also includes P first registers and P second registers. Each first register is used to store the cumulative score vector of a subsequence decoded in the current round, and each second register is used to store the cumulative score vector of a subsequence decoded in the previous round. In the new round of decoding, the cumulative score vector in the first register is moved to the paired second register, and the free first register is used to store the cumulative score vector obtained in the current round of decoding.

5. The convolutional decoder according to any one of claims 1-4, characterized in that, It also includes P output buffers, each used to store the decoded sequence output by each Viterbi decoder.

6. The convolutional decoder according to any one of claims 1-5, characterized in that, It also includes an input buffer for storing the encoded sequence.

7. The convolutional decoder according to any one of claims 1-6, characterized in that, It also includes a timer, which triggers the end of decoding if decoding cannot be completed within a preset time.

8. A decoding method, characterized in that, An application to the convolutional decoder as described in any one of claims 1-7, used for decoding an encoded sequence, wherein the encoded sequence is divided into P first sub-sequences, and the tail sequences of the P first sub-sequences are P second sub-sequences, the method comprising: For the first round of decoding, at least one of the P Viterbi decoders decodes each of the P second subsequences, updating the cumulative score vector of the P second subsequences. The cumulative score vector of the second subsequences represents the cumulative score of each state transition path obtained by decoding the second subsequences. The cumulative score of each state transition path represents the probability of obtaining a decoded sequence along each state transition path. Before the first round of decoding, the initial value of the cumulative score vector of the P second subsequences is all 0. Starting from the second round of decoding, the p-th Viterbi decoder begins cyclically decoding the encoded sequence from the starting position of the p-th first sub-sequence. In each round of decoding, the cumulative score vectors of the P first sub-sequences are updated. The cumulative score vector of the first sub-sequence represents the cumulative score of each state transition path obtained by decoding the first sub-sequence. Before the second round of decoding, the initial value of the cumulative score vector of any first sub-sequence is the cumulative score vector of the previous second sub-sequence in the first round of decoding; p is an integer less than or equal to P. P comparators compare the cumulative score vectors of two subsequences with the same ending position obtained from the last two rounds of decoding. If the maximum probability state transition path of the two subsequences with the same ending position is the same, the decoded sequence corresponding to the maximum probability state transition path is output.

9. The method according to claim 8, characterized in that, At least one of the P Viterbi decoders decodes the P second subsequences respectively, including: the P Viterbi decoders are used to decode the P second subsequences respectively in parallel.

10. An electronic device, characterized in that, The receiver includes a convolutional decoder as described in any one of claims 1-7.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method of claim 8 or 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 8 or 9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 8 or 9.

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