Hyperchaotic model circuit based on memristor coupling and image encryption method

Abstract

The invention relates to the technical field of hyper-chaotic circuits, in particular to a hyper-chaotic model circuit based on memristor coupling and an image encryption method, and the hyper-chaotic model circuit comprises a first cosine memristor circuit, a second cosine memristor circuit, a first integrating circuit, a second integrating circuit and a memristor coupling circuit; wherein the first cosine memristor circuit is connected with the first integrating circuit, the second cosine memristor circuit is connected with the second integrating circuit, and the memristor coupling circuit is connected with the first integrating circuit and the second integrating circuit; by setting the coupling strength and the initial state value, heterogeneous and homogeneous offset attractors are generated. The problem that in the prior art, there is no chaotic system with heterogeneous and homogeneous extreme multi-stability at the same time is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of hyperchaotic circuits, and in particular to a memristor-coupled hyperchaotic model circuit and an image encryption method. Background Art

[0002] In recent years, chaotic systems have attracted widespread attention due to their great application potential in secure communications, image encryption and other fields.

[0003] Memristors, as a new type of nonlinear circuit element, have the characteristics of memory resistance or conductance and can bring new dimensions to the design of chaotic systems;

[0004] However, there is currently no research on chaotic systems that exhibit both heterogeneous and homogeneous extreme multistability. In addition, hyperchaotic systems, because they have at least two positive Lyapunov exponents, exhibit more complex nonlinear phenomena than chaotic systems, and have important application value, especially in the field of secure communications. Therefore, designing a hyperchaotic system that can simultaneously exhibit heterogeneous and homogeneous extreme multistability and applying it to image encryption has important theoretical and practical significance. Summary of the Invention

[0005] In view of the shortcomings of the existing methods, the present invention solves the problem in the prior art of lacking a chaotic system with both heterogeneous and homogeneous extreme multistability.

[0006] The technical solution adopted by the present invention is: based on the memristor coupling hyperchaotic model circuit, it includes:

[0007] a first cosine memristor circuit, a second cosine memristor circuit, a first integration circuit, a second integration circuit, and a memristive coupling circuit; wherein the first cosine memristive circuit is electrically connected to the first integration circuit, the second cosine memristive circuit is electrically connected to the second integration circuit, and the memristive coupling circuit is electrically connected to the first integration circuit and the second integration circuit;

[0008] By setting the coupling strength and initial state value, heterogeneous and homogeneous offset attractors are generated.

[0009] As a preferred embodiment of the present invention, the first cosine memristor circuit includes: a resistor R1, a multiplier M1, a cosine function generator COS1, an operational amplifier U1 and a capacitor C1, the right end of R1 is connected to the common end of U1 and C1, the right end of C1 is connected to the common end of U1 and COS1, the left end of R1 is connected to an input end of M1, the output end of COS1 is connected to an input end of M1, and the output end of M1 is connected to R1. m1 The left end of the connection.

[0010] As a preferred embodiment of the present invention, the second cosine memristor circuit includes: a resistor R7, a multiplier M2, a cosine function generator COS2, an operational amplifier U7 and a capacitor C5, the right end of R7 is connected to the common end of U7 and C5, the right end of C5 is connected to the common end of U7 and COS2, the left end of R7 is connected to an input end of M2, the output end of COS2 is connected to an input end of M2, and the output end of M2 is connected to R7. m2 The left end of the connection.

[0011] As a preferred embodiment of the present invention, the first integration circuit includes: resistors R2 to R6, a resistor R n1 to R n4 , resistor R m3 , operational amplifiers U2 to U6, capacitors C2 to C4 and the first cosine memristor circuit W1, the inverting input terminal of U4 is connected to the common terminal of C2, R2 and R3 respectively, the right end of C2 and R3 is connected to the common terminal of U4, R5 and R n2 The common terminal connection, R n2 The upper end of U2 and R n1 The right end of R5 is connected to the common end of U5 and C3, and the right end of C3 is connected to the common end of U5, R6, and R n4 The common terminal connection, R n4 The upper end of U3 and R n3 The common terminal connection, R n3 The right end of R6 is connected to the common end of U3 and W1, and the right end of R6 is connected to W1, U6, C4, R m3 , the common end of R4 is connected, the upper end of R4 is connected to R n1 , and the common end of U2, and the right end of C4 is connected to the common end of U6 and R2.

[0012] As a preferred embodiment of the present invention, the second integrating circuit includes: resistors R8 to R 12 , resistor R n5 to R n8 , resistor R m4 , operational amplifier U8 to U 12 , capacitors C6 to C8 and the second cosine memristor circuit W2, U 10 The reverse input end of the resistor is connected to the common end of C6, R8 and R9 respectively, and the right end of C6 and R9 is connected to the common end of U 10 、R 11 、R n6 The common terminal connection, R n6 The upper end of U8, R n5 The common terminal connection, R 11 The right end of U 11 , the common end of C7 is connected, the right end of C7 is connected to U 11 、R 12 、Rn8 The common terminal connection, R n8 The upper end of U9, R n7 The common terminal connection, R n7 The right end is connected to the common end of U9 and W2, R 12 The right end of W2, U 12 、C8、R m4 、R 10 The common terminal connection, R 10 The upper end and R n5 , the common end of U8 is connected, the right end of C8 is connected to U 12 , the common terminal connection of R8.

[0013] As a preferred embodiment of the present invention, the memristive coupling circuit includes: a resistor R 13 , resistor R n9 to R n17 , multiplier M3, operational amplifier U 13 to U 16 and capacitor C9, R n9 The left end is connected to the output of the first integration circuit, R n10 The left end is connected to the output of the second integrator circuit, R n9 The right end of R n12 、U 13 The common terminal connection, R n10 With R n11 The right common terminal is connected to the same direction input terminal of U13, R n12 The right end of U 13 、R 13 The common terminal connection, R 13 The right end of U 14 , the common end of C9 is connected, the right end of C9 is connected to U 14 、R n13 The common terminal connection, R n13 With R n14 The right common terminal and U 15 The same-direction input terminal of 15 The inverting input terminal and R n15 The left end of the connection, R n15 The right end of U 15 , the common end of M3 is connected, and the other end of M3 input is connected to U 13 、R n12 、R 13 The common end of M3 is connected to the R n16 , the common terminal of the first integration circuit is connected, R n16 The right end of R n17 、U 16 The common terminal connection, R n17 The right end of U16 , the common end of the second integration circuit is connected.

[0014] As a preferred embodiment of the present invention, the operational amplifier is AD711JN.

[0015] As a preferred embodiment of the present invention, an image encryption method based on a memristor-coupled hyperchaotic model circuit includes the following steps:

[0016] Step 1: Obtain the original image to be encrypted, convert it to grayscale and perform two-dimensional matrix conversion;

[0017] Step 2: Using the initial state value of the memristor-coupled hyperchaotic circuit as a security key to obtain a chaotic sequence; placing the chaotic sequence into a chaotic matrix; amplifying and biasing the chaotic matrix and then taking the modulus to obtain a chaotic sequence matrix;

[0018] Step 3: Add the chaotic sequence matrix after modular operation to the original image; perform modular operation on the added image to obtain the key sequence m=unit8(C(:)), where C is the chaotic sequence matrix after modular operation;

[0019] Step 4: Serialize the original grayscale image and convert it to double precision; perform an XOR operation on the double-precision image and the key sequence to obtain a diffused pseudo-random sequence CL;

[0020] As a preferred embodiment of the present invention, the formula of the pseudo-random sequence CL is:

[0021] CL=bitxor(uint8(P'(i)),m(i));

[0022] Where bitxor represents the exclusive OR operation, uint8 is an unsigned 8-bit integer, P'(i)) is the serialized image, and m(i) is the key sequence.

[0023] Step 5: Obtain a pseudo-random sequence by scrambling: V = floor(D) + 1; remove duplicates from V to obtain a unique element S V , find the sequence A=[1,2,…,MN] but not in U SV The elements in are sorted in ascending order and saved to U E End of; swap CL V (U E (i)) and CL V (U E (MN-i+1));

[0024] Step 6: Transform the pixel sequence CL of the ciphertext image V Convert to a two-dimensional matrix;

[0025] As a preferred embodiment of the present invention, the encrypted original image is decrypted.

[0026] Beneficial effects of the present invention:

[0027] 1. The nine-dimensional memristor-coupled cosine-memristor hyperchaotic system proposed in this paper can simultaneously exhibit heterogeneous and homogeneous extreme multistability, enriching the research content of chaotic systems and providing a new perspective for the development of chaos theory.

[0028] 2. The image encryption method based on chaotic system has high security and anti-attack capabilities. It can effectively resist various attack methods such as statistical analysis attacks and key sensitivity attacks, providing a new solution for the field of image encryption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The circuit for realizing equation (3) of the memristor-coupled hyperchaotic system;

[0030] Figure 2 is the coexistence attractor behavior under different initial state values;

[0031] Figure 3 For PSIM circuit simulation;

[0032] Figure 4 This is a schematic diagram of the image encryption process;

[0033] Figure 5 To experiment with image encryption scheme for Clock;

[0034] Figure 6 To use Clock images for key sensitivity analysis;

[0035] Figure 7 are adjacent pixel pairs of the Clock image and its ciphertext image. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. This figure is a simplified schematic diagram, which only illustrates the basic structure of the present invention in a schematic manner, and therefore only shows the components related to the present invention.

[0037] like Figure 1 As shown, the circuit based on the memristor coupling hyperchaotic model includes:

[0038] A memristive-coupled hyperchaotic circuit is constructed by a first cosine-memristive circuit, a second cosine-memristive circuit, a first integration circuit, a second integration circuit, and a memristive coupling circuit; wherein the first cosine-memristive circuit is electrically connected to the first integration circuit, the second cosine-memristive circuit is electrically connected to the second integration circuit, and the memristive coupling circuit is electrically connected to the first integration circuit and the second integration circuit;

[0039] By setting the coupling strength and initial state value of the memristor-coupled hyperchaotic circuit, heterogeneous and homogeneous offset attractors are generated.

[0040] The first cosine memristor circuit includes: a resistor R1, a multiplier M1, a cosine function generator COS1, an operational amplifier U1 and a capacitor C1, the right end of R1 is connected to the inverting input end of U1 and the left end of C1 respectively, the right end of C1 is connected to the output end of U1 and the input end of COS1, the left end of R1 is connected to one input end of M1, the output end of COS1 is connected to one input end of M1, and the output end of M1 is connected to R1. m1 The left end of the connection, R m1 The right end (A3) of R1 is connected to the reverse input terminal (A3) of U6; the left end of R1 is the voltage v x2 , the left end of R1 (A2) is connected to the output end of U3 (A2); the output end of U1 is the voltage -v x4 .

[0041] The second cosine memristor circuit includes: a resistor R7, a multiplier M2, a cosine function generator COS2, an operational amplifier U7 and a capacitor C5, the right end of R7 is connected to the inverting input end of U7 and the left end of C5 respectively, the right end of C5 is connected to the output end of U7 and the input end of COS2, the left end of R7 is connected to one input end of M2, the output end of COS2 is connected to one input end of M2, and the output end of M2 is connected to R7. m2 The left end of the connection, R m2 The right end (B3) and U 12 The reverse input terminal (B3) is connected; the left end of R7 is the voltage v y2 , the left end of R7 (B2) is connected to the output end of U9 (B2); the output end of U7 is voltage -v y4 .

[0042] The first integration circuit includes: resistors R2 to R6, a resistor R n1 to R n4 , resistor R m3 , operational amplifiers U2 to U6, capacitors C2 to C4 and memristor W1 (i.e., the first cosine memristor circuit), the inverting input terminal of U4 is connected to the left ends of C2, R2, and R3 respectively, and the right ends of C2 and R3 are connected to the output terminal of U4, the left end of R5, and R n2 The lower end of the connection, R n2 The upper end of the U2 is connected to the reverse input terminal and R n1 The left end of R5 is connected to the reverse input end of U5 and the left end of C3 respectively. The right end of C3 is connected to the output end of U5, the left end of R6, and R n4 The lower end of the connection, R n4 The upper end of the U3 is connected to the reverse input terminal and R n3The left end of the connection, R n3 The right end of R6 is connected to the output of U3 and the upper end of W1 respectively, and the right end of R6 is connected to the lower end of W1, the reverse input end of U6, the left end of C4, and the left end of R m3 The lower end of R4 is connected to the reverse input terminal of U6 (A3) and R m1 The left end (A3) is connected to the upper end of R4 and R n1 The right end of C4 is connected to the output end of U6 and the right end of R2 respectively; m3 The upper end is A1 (i.e. the output end of M3); the output voltage of U2 is -v x3 ; U3 output voltage is v x2 ; U4 output voltage is v x3 ; U5 output voltage is -v x2 ; U6 output voltage is v x1 , U6 output (A4) and R n9 Connect the left end of the

[0043] The second integrating circuit includes resistors R8 to R 12 , resistor R n5 to R n8 , resistor R m4 , operational amplifier U8 to U 12 , capacitors C6 to C8 and memristor W2 (i.e., the second cosine memristor circuit), U 10 The reverse input end of the resistor is connected to the left end of C6, R8 and R9 respectively, and the right end of C6 and R9 is connected to U 10 The output terminal, R 11 The left end of R n6 The lower end of the connection, R n6 The upper end of the U8 is connected to the reverse input terminal and R n5 The left end of the connection, R 11 The right end of U 11 The reverse input terminal of C7 is connected to the left end of C7, and the right end of C7 is connected to U 11 The output terminal, R 12 The left end of R n8 The lower end of the connection, R n8 The upper end of the U9 is connected to the reverse input terminal and R n7 The left end of the connection, R n7 The right end is connected to the output end of U9 and the upper end of W2 respectively, R 12 The right end of W2 is connected to the lower end of U 12 The reverse input terminal, the left end of C8, R m4 The lower end of R 10 The lower end connection, U 12 The inverting input terminal (B3) and R m2The right end (B3) is connected to R 10 The upper end and R n5 The right end of C8 is connected to the output end of U8, and the right end of C8 is connected to the output end of U 12 The output end of R8 is connected to the right end; R m4 The upper end is the B1 end (i.e. U 16 Output terminal of U8); the output voltage of U8 is -v y3 ; U9 output voltage is v y2 , the output end (B2) of U9 is connected to the left end (B2) of R7; U 10 The output voltage is v y3 ;U 11 The output voltage is -v y2 ;U 12 The output voltage is v y1 , U 12 Output terminal (B4) and R n10 Connect to the left end (B4).

[0044] The memristor coupling circuit is used for coupling the first integration circuit and the second integration circuit; it includes: a resistor R 13 , resistor R n9 to R n17 , multiplier M3, operational amplifier U 13 to U 16 and capacitor C9, R n9 The right end of R n12 The left end of U 13 The inverting input terminal is connected to R n10 With R n11 The right common terminal is connected to the same direction input terminal of U13, R n12 The right end of U 13 The output terminal and R 13 The left end of the connection, R 13 The right end of U 14 The reverse input terminal of C9 is connected to the left end of C9, and the right end of C9 is connected to U 14 The output terminal and R n13 The left end of the connection, R n13 With R n14 The right common terminal and U 15 The same-direction input terminal of 15 The inverting input terminal and R n15 The left end of the connection, R n15 The right end of U 15 The output end of M3 is connected to the input end of M3, and the other end of M3 is connected to U 13 The output terminal, R n12 The right end and R 13 The left end of M3 is connected to R n16The left end of the connection, R n16 The right end of R n17 The left end of U 16 The inverting input terminal is connected to R n17 The right end of U 16 The output terminal of the R n9 The left end voltage v x1 , R n9 The left end is connected to the output of U6; R n10 The left end voltage v y1 , R n10 The left end and U 12 The output terminal of the R n12 The right end voltage v y1- v x1 ; The voltage at the right end of C9 R n15 The right end voltage The output end of M3 is A1 end; U 16 The output end is B1.

[0045] The system equation of the memristor coupled hyperchaotic model contains 9 state variables x1, x2, x3, x4, y1, y2, y3, y4 and The four variables v corresponding to the circuit state equation x1 、v x2 、v x3 、v x4 、v y1 、v y2 、v y3 、v y4 and

[0046] Mathematical modeling: This invention is based on a four-dimensional autonomous memristor system, whose model can be described as:

[0047]

[0048] Using the model of formula (1), when the system parameter m=3 is fixed, the complex and sensitive initial value displacement control phenomenon can be revealed along the x4 coordinate value.

[0049] The present invention considers coupling two isomorphic memristor chaotic systems (1) with an ideal memristor, which can be described as:

[0050]

[0051] in, v and i represent the internal state variables, input voltage and output current of the memristor respectively; the memristor function is

[0052] By introducing the above-mentioned memristor into system (1), a 9-dimensional memristor-coupled hyperchaotic system can be established. The model can be described by a set of first-order ordinary differential equations:

[0053]

[0054] It is worth noting that with the initial value of the state With the change of , model (3) has different periodic states, stable point states, divergent states and chaotic states, showing complex super multi-stability behavior.

[0055] exist Figure 1 In the 9-dimensional memristor coupled hyperchaotic system, the main circuit has four integral channels, which are used to realize the corresponding equations in formula (3).

[0056] According to Kirchhoff's circuit laws and the electrical characteristics of circuit components, Figure 1 The circuit equation shown can be written as:

[0057]

[0058] Among them, g1R1cos(v x4 )v x2 / R m1 Corresponding to the first cosine memristor M1; g2R7cos(v y4 )v y2 / R m2 Corresponding to the second cosine memristor M2; and Corresponding to the ideal memristor.

[0059] Using analog circuit components such as operational amplifiers, multipliers, capacitors, resistors, and delta converters, a 9-dimensional memristor coupling circuit is constructed using Equation (3). The analog circuit contains a module with a cosine derivative function. It should be noted that the cosine function has an even function characteristic, so the module outputs cos(x4) instead of cos(-x4), where v x1 、v x2 、v x3 、v x4 、v y1 、v y2 、v y3 、v y4 and v φ There are nine circuit variables. τ = RC represents the time constant of the five integrators, and g represents the multiplier gain. We set the time constant τ = RC = 15kΩ × 100nF = 1.5ms and specify the gain g = 1. The circuit parameters are as follows:

[0060] R1=R2=R3=R4=R5=R6=R7=R8=R9=R10 =R 11 =R 12 =R 13 =15kΩ, R n1 =

[0061] R n2 =R n3 =R n4 =R n5 =R n6 =R n7 =R n8 =R n9 =R n10 =R n11 =R n12 =R n13 =R n14 =R n15 =R n16 =R n17 =10kΩ, R m1 =R m2 =150kΩ, R m3 =R m4 =5kΩ, C1=C2=C3=C4=C5=C6=C7=C8=C9=100nf;

[0062] Operational amplifier U1-U 16 Models include: AD711JN; multiplier model is AD633;

[0063] The above models are preferred, and all models that can realize the functions of the present invention are within the protection scope of the present invention.

[0064] like Figure 4 , an image encryption method based on a memristor-coupled hyperchaotic model circuit, comprising:

[0065] Step 1: Get the original image to be encrypted and grayscale it, and save the grayscale image P of size M×N as a two-dimensional matrix;

[0066] Step 2: Use the initial state value IC of the memristor coupled hyperchaotic circuit as the security key K1, and use the Runge-Kutta method to solve the first-order ordinary differential equation system (3) to obtain the chaotic sequence Sx1, Sx2, Sx3,

[0067] Then, use the equations A = reshape(Sx1, M, N) and B = reshape(Sx2, M, N) to put the sequences Sx1 and Sx2 into the M × N chaotic matrices A and B respectively. A and B are normalized signals with too small amplitudes, which need to be amplified and offset before taking the modulus to obtain the M × N chaotic sequence matrices A1 and B1.

[0068] A1=mod(A×k+b,256), B1=mod(B×k+b,256);

[0069] Where k is the amplification factor and b is the bias;

[0070] Step 3: After adding the chaotic sequence matrices A1 and B1 to the original image signal P, perform modular operations on the 256*256 encrypted images C and D using the formulas C=mod(double(P)+A1,256) and D=mod(double(P)+B1,256); thus, the key sequence m is obtained using the formula m=unit8(C(:));

[0071] Step 4: Serialize the image P into P' and convert it to double precision using P'=double(P(:)); then perform an XOR operation on the image sequence P' and the key sequence m to obtain the diffused pseudo-random sequence CL using CL=bitxor(uint8(P'(i)),m(i)); where bitxor represents the XOR operation of P'(i) and m(i), and i is the number of iterations;

[0072] Step 5: Obtain a pseudo-random sequence by scrambling. The corresponding calibration equation can be expressed as V=floor(D)+1. Using equation U E = unique(V) to get the unique element S V , find the sequence A=[1,2,…,MN] but not in U SV The elements in the array are sorted in ascending order and stored in U E At the end; finally, exchange CL V (U E (i)) and CL V (U E (MN-i+1));

[0073] Step 6: To create an 8-bit unsigned ciphertext image C', transform the pixel sequence CL of the one-dimensional ciphertext image C' into V Convert to a two-dimensional matrix of size M×N;

[0074] During decryption, each step in the encryption operation is reversed.

[0075] Numerical simulation: When the initial value of the state When the value of ΔH is changed, the dynamic behavior of the new memristor-coupled hyperchaotic system is numerically studied using the MATLAB ODE45 algorithm.

[0076] When the coupling strength is set to k = 0.1 and k = 4, IC = (10 -6,0,0,x4(0),0,0,0,0), the homogeneous coexistence attractors under different memristor initial values are projected onto the x4-x1 plane for simulation; the phase diagram of the attractor controlled by the initial value displacement of x4(0) is shown as follows Figure 2 As shown, Figure 3 is the corresponding PSIM circuit simulation diagram; in order to prevent the phase trajectory overlap due to the nonlinear movement of these attractors along the x4 coordinate, the initial value x4(0) of the memristor is selected in the range of [-11,11]; these findings indicate that there are countless homogeneous coexisting attractors, each with different dynamic categories, topologies and locations; in other words, the memristor-coupled hyperchaotic system (3) has an initial value displacement-controlled attractor and has similar super-multistability.

[0077] Encryption application: Image encryption based on the above-mentioned memristor-coupled hyperchaotic circuit;

[0078] The image encryption system was tested using grayscale clocks to verify the legitimacy of the image encryption strategy. The experimental parameters specified that the test image should be 256×256, the security key K1 should be IC=(10-6, 0, 0, 0, 0, 0, 0, 0), the magnification factor was k=1014, and the bias was b=100. The security of the encryption technology was evaluated using histograms, key sensitivity, correlation coefficient, and information entropy.

[0079] Figure 5 Experiments demonstrating encryption schemes, Figure 5 (Above) shows the (a) plaintext image, (b) ciphertext image, and (c) decrypted image of the Clock image. Figure 5 (below) shows Figure 5 (above) The corresponding histogram of the image; from Figure 5 It can be seen that the histogram of the plaintext image has a variety of distribution patterns, and the proposed encryption algorithm can obtain a ciphertext image with a uniform histogram distribution; Figure 6 The experiment of key sensitivity analysis is shown. It can be seen from the figure that only the correct key can completely restore the original image (such as Figure 6 Using a key with a slight error, the decrypted result does not contain any information of the original image (as shown in a); Figure 6 c, d and e); therefore, the proposed image encryption scheme is extremely sensitive to its key; Figure 7 Adjacent pairs of pixels are drawn; from Figure 7 A level, Figure 7 The vertical sum of b Figure 7 By plotting adjacent pixel pairs of the plaintext image in the diagonal direction of c, it can be seen that most of the adjacent pixel pairs in the plaintext image are distributed on the diagonal of the phase plane. Figure 7 d、 Figure 7 e and Figure 7 f represents the random distribution of adjacent pixel pairs in the horizontal, vertical and diagonal directions in the ciphertext image on the entire phase plane; experimental results show that the encryption scheme has good security against various possible attacks.

[0080] With the above-described preferred embodiments of the present invention as a guide, and with reference to the above description, relevant personnel are fully capable of making various changes and modifications without departing from the technical scope of this invention. The technical scope of this invention is not limited to the contents of the specification and must be determined according to the scope of the claims.

Claims

1. Based on the memristor coupling hyperchaotic model circuit, it is characterized by: include: a first cosine memristor circuit, a second cosine memristor circuit, a first integration circuit, a second integration circuit, and a memristive coupling circuit; wherein the first cosine memristive circuit is electrically connected to the first integration circuit, the second cosine memristive circuit is electrically connected to the second integration circuit, and the memristive coupling circuit is electrically connected to the first integration circuit and the second integration circuit; By setting the coupling strength and initial state value, heterogeneous and homogeneous offset attractors are generated.

2. The memristor-coupled hyperchaotic model circuit according to claim 1, characterized in that: The first cosine memristor circuit includes: a resistor R1, a multiplier M1, a cosine function generator COS1, an operational amplifier U1 and a capacitor C1, the right end of R1 is connected to the common end of U1 and C1, the right end of C1 is connected to the common end of U1 and COS1, the left end of R1 is connected to an input end of M1, the output end of COS1 is connected to an input end of M1, and the output end of M1 is connected to R1. m1 The left end of the connection.

3. The memristor-coupled hyperchaotic model circuit according to claim 1, characterized in that: The second cosine memristor circuit includes: a resistor R7, a multiplier M2, a cosine function generator COS2, an operational amplifier U7 and a capacitor C5, the right end of R7 is connected to the common end of U7 and C5, the right end of C5 is connected to the common end of U7 and COS2, the left end of R7 is connected to an input end of M2, the output end of COS2 is connected to an input end of M2, and the output end of M2 is connected to R7. m2 The left end of the connection.

4. The memristor-coupled hyperchaotic model circuit according to claim 2, characterized in that: The first integration circuit includes: resistors R2 to R6, resistor R n1 to R n4 , resistor R m3 , operational amplifiers U2 to U6, capacitors C2 to C4 and the first cosine memristor circuit W1, the inverting input terminal of U4 is connected to the common terminal of C2, R2 and R3 respectively, the right end of C2 and R3 is connected to the common terminal of U4, R5 and R n2 The common terminal connection, R n2 The upper end of U2 and R n1 The right end of R5 is connected to the common end of U5 and C3, and the right end of C3 is connected to the common end of U5, R6, and R n4 The common terminal connection, R n4 The upper end of U3 and R n3 The common terminal connection, R n3 The right end of R6 is connected to the common end of U3 and W1, and the right end of R6 is connected to W1, U6, C4, R m3 , the common end of R4 is connected, the upper end of R4 is connected to R n1 , and the common end of U2, and the right end of C4 is connected to the common end of U6 and R2.

5. The memristor-coupled hyperchaotic model circuit according to claim 3, characterized in that: The second integration circuit includes: The second integration circuit includes: resistors R8 to R 12 , resistor R n5 to R n8 , resistor R m4 , operational amplifier U8 to U 12 , capacitors C6 to C8 and the second cosine memristor circuit W2, U 10 The reverse input end of the resistor is connected to the common end of C6, R8 and R9 respectively, and the right end of C6 and R9 is connected to the common end of U 10 、R 11 、R n6 The common terminal connection, R n6 The upper end of U8, R n5 The common terminal connection, R 11 The right end of U 11 , the common end of C7 is connected, the right end of C7 is connected to U 11 、R 12 、R n8 The common terminal connection, R n8 The upper end of U9, R n7 The common terminal connection, R n7 The right end is connected to the common end of U9 and W2, R 12 The right end of W2, U 12 、C8、R m4 、R 10 The common terminal connection, R 10 The upper end and R n5 , the common end of U8 is connected, the right end of C8 is connected to U 12 , the common terminal connection of R8.

6. The memristor-coupled hyperchaotic model circuit according to claim 4 or 5, characterized in that: The memristive coupling circuit includes: resistor R 13 , resistor R n9 to R n17 , multiplier M3, operational amplifier U 13 to U 16 and capacitor C9, R n9 The left end is connected to the output of the first integration circuit, R n10 The left end is connected to the output of the second integrator circuit, R n9 The right end of R n12 、U 13 The common terminal connection, R n10 With R n11 The right common terminal is connected to the same direction input terminal of U13, R n12 The right end of U 13 、R 13 The common terminal connection, R 13 The right end of U 14 , the common end of C9 is connected, the right end of C9 is connected to U 14 、R n13 The common terminal connection, R n13 With R n14 The right common terminal and U 15 The same-direction input terminal of 15 The inverting input terminal and R n15 The left end of the connection, R n15 The right end of U 15 , the common end of M3 is connected, and the other end of M3 input is connected to U 13 、R n12 、R 13 The common end of M3 is connected to the R n16 , the common terminal of the first integration circuit is connected, R n16 The right end of R n17 、U 16 The common terminal connection, R n17 The right end of U 16 , the common end of the second integration circuit is connected.

7. The memristor-coupled hyperchaotic model circuit according to claims 2, 3, 4, 5, and 6, characterized in that: The model of the operational amplifier is AD711JN.

8. The image encryption method based on the memristor coupled hyperchaotic model circuit according to claim 1 is characterized in that: The steps include: Step 1: Obtain the original image to be encrypted, convert it to grayscale and perform two-dimensional matrix conversion; Step 2: Using the initial state value of the memristor-coupled hyperchaotic circuit as a security key to obtain a chaotic sequence; placing the chaotic sequence into a chaotic matrix; amplifying and biasing the chaotic matrix and then taking the modulus to obtain a chaotic sequence matrix; Step 3: Add the chaotic sequence matrix after modular operation to the original image; perform modular operation on the added image to obtain the key sequence m=unit8(C(:)), where C is the chaotic sequence matrix after modular operation; Step 4: Serialize the original grayscale image and convert it to double precision; perform an XOR operation on the double-precision image and the key sequence to obtain a diffused pseudo-random sequence CL; Step 5: Obtain a pseudo-random sequence by scrambling: V = floor(D) + 1; remove duplicates from V to obtain a unique element S V , find the sequence A=[1,2,…,MN] but not in U SV The elements in are sorted in ascending order and saved to U E End of; swap CL V (U E (i)) and CL V (U E (MN-i+1)); Step 6: Transform the pixel sequence CL of the ciphertext image V Convert to a two-dimensional matrix.

9. The method based on the memristor-coupled hyperchaotic model circuit according to claim 8, characterized in that: The formula for the pseudo-random sequence CL is: CL=bitxor(uint8(P'(i)),m(i)); Where bitxor represents the exclusive OR operation, uint8 is an unsigned 8-bit integer, P'(i)) is the serialized image, and m(i) is the key sequence.

10. The image encryption method based on the memristor coupled hyperchaotic model circuit according to claim 8, characterized in that: Decrypt the encrypted original image.

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